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# Getting started with switch gateware development
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This page provide information for people who want to contribute to the
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development of switch's HDL. It is meant to explain first steps to get
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going with simulation and synthesis assuming a developer
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uses and has installed HDLmake (explained below), Xilinx ISE, ModelSim
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(supporting multi-language simulation) on Linux PC.
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This page provides information for people who want to contribute to the
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development of the WR switch gateware (HDL). It is meant to explain
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first steps to get going with the simulation and synthesis assuming a
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developer installed HDLmake (explained below), Xilinx ISE, ModelSim
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(supporting mixed-language simulation) in the Linux environment.
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A sketch (unfinished) depicting architecture of switch HDL can be found
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[here](https://www.ohwr.org/project/wr-switch-hdl/uploads/63a1d6b10a371fb27f72cb6c5b41ac3c/SwitchGWarchitecture.jpg).
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... | ... | @@ -18,60 +18,43 @@ software can be found [here](https://www.ohwr.org/project/wr-switch-hdl/wikis/Do |
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([v3.3](https://www.ohwr.org/project/wr-switch-hdl/uploads/adda9585b266bddbe32b55595cdb694b/switch_hdl-sw.pdf) and
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[v4](https://www.ohwr.org/project/white-rabbit/uploads/0e90236d5e9b48b41424dfc695d23cc4/switch_hdl-sw-v4.0.pdf))
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HDLmake tool is used for WR switch HDL development to make developers'
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life easier.
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## HDLmake
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- It is a tool for generating multi-purpose makefiles for FPGA
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projects that is used to simulate and synthesize switch HDL
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- The below explanation of the switch HDL simulation/synthesis assumes
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that you are familiar with HDLmake, have it installed, added to your
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PATH and can use it.
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- The website of the HDLmake project is
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[here](https://www.ohwr.org/project/hdl-make)
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- Handful information about using HDLmake can be found in Chapter
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3.4.2 of the [Getting Started with the
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*HDLmake* is a tool for generating multi-purpose Makefiles for FPGA
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projects that are used to simulate and synthesize gateware. The
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instructions in the following sections assume that you have *HDLmake*
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already installed and its location is added to your *PATH* environment
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variable. If you need more information on this tool, please visit one of
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the following places:
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- [*HDLmake* project page on
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OHWR](https://www.ohwr.org/project/hdl-make)
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- Chapter 3.4.2 of the [Getting Started with the
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SPEC](https://www.ohwr.org/project/white-rabbit/uploads/e747a4d84a62dcb0f9d784621137b003/spec-getting-started-v1.0-201403.pdf)
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tutorial that is part of [Getting Started with
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tutorial that is part of the [Getting Started with
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SPEC](https://www.ohwr.org/project/spec-getting-started) project
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- Beware: we are currently using ISYP branch of HDLmake
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## HDL directory structure
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-----
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ip\_cores - contains external cores used by the project (included in the
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git repo as submodules)
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modules - include switch-specific & FPGA-independent VHDL modules
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platform - contains FPGA-dependent VHDL code
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sim - contains SystemVerilog models, drivers and register layouts used
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by testbenches
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syn - contains ISE project files for synthesis (e.g. if you want to
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synthesize for 18-port switch, you should go into syn/scb\_18ports)
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testbench - contains testbenches for top-level of the switch and some
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modules, also for a network of switches
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top - contains top-levels and constraint (UCF) files
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-----
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The top/bare\_top/ contains scb\_top\_bare.vhd which is a configurable
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top level entity of the switch. This entity is used by both, synthesis
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and testbench top levels. In other words, this is a configurable IP
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which needs some more VHDL to simulate or synthesize.
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*Beware: we are currently using ISYP branch of HDLmake**
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### Switch Testbench
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## HDL directory structure
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The testbench of the switch is written in SystemVerilog and is located
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in testbench/scb\_top/main.sv. It uses top/bare\_top/scb\_top\_bare.vhd
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indirectly:
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- scb\_top\_bare.vhd is instantiated in
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top/bare\_top/scb\_top\_sim.vhd
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- scb\_top\_sim.vhd is wrapped by
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testbench/scb\_top/scb\_top\_sim\_svwrap.svh
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- scb\_top\_sim\_svwrap.svh is used in the main testbench:
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testbench/scb\_top/main.sv
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- *ip\_cores* - contains external cores used by the project (included
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in the git repo as submodules)
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- *modules* - include switch-specific & FPGA-independent VHDL modules
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- *platform* - contains FPGA-dependent VHDL code
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- *sim* - contains SystemVerilog models, drivers and register layouts
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used by testbenches
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- *syn* - contains ISE project files for synthesis, e.g. if you want
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to synthesize 18-port WRS version, you should go to
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*syn/scb\_18ports*
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- *testbench* - contains testbenches for the top-level of the switch,
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some of the modules and a network of switches
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- *top* - contains top-level and constraint files
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The *top/bare\_top/* contains *scb\_top\_bare.vhd* which is a
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configurable top level entity of the switch. This entity is used by
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both, synthesis and testbench top levels. In other words, this is a
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configurable IP which needs some more VHDL to simulate or synthesize.
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## WRS gateware synthesis (v4.2)
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... | ... | @@ -129,7 +112,18 @@ gateware |
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1. Reboot the switch so that your new gateware is loaded
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## Steps to run switch simulation
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## WRS gateware simulation
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The testbench of the switch is written in SystemVerilog and is located
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in testbench/scb\_top/main.sv. It uses top/bare\_top/scb\_top\_bare.vhd
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indirectly:
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- scb\_top\_bare.vhd is instantiated in
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top/bare\_top/scb\_top\_sim.vhd
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- scb\_top\_sim.vhd is wrapped by
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testbench/scb\_top/scb\_top\_sim\_svwrap.svh
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- scb\_top\_sim\_svwrap.svh is used in the main testbench:
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testbench/scb\_top/main.sv
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### Version of HDL compatible with v3.3 software, tag: wr-switch-sw-v3.3
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