... | @@ -24,6 +24,14 @@ Fig. 2: Internal layout of Real-Time Subsystem component |
... | @@ -24,6 +24,14 @@ Fig. 2: Internal layout of Real-Time Subsystem component |
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## Getting Started with switch gateware (HDL) development
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If you want to simulate or synthesize WR switch gateware, have a look at
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[this page](/ForDevelopers) which should make it easier for you to get
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started.
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# Roadmap for gateware releases
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# Roadmap for gateware releases
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<table>
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<table>
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