The main ingredient of the PSP is the FPGA gateware, which comes in the
form of a parametrisable VHDL module, to be instantiated in your own
By using this module, the user gains the benefit of instantiating all
the platform-specific support components for the WR PTP core (PHY, PLLs,
etc.) in one go, without having to delve into the implementation
details, using a setup that has been tested and is known to work well on
Arria V FPGAs.
The FPGA gateware is available on the
branch of the wr-cores repository (soon to be merged in proposed_master
To use it, set the g_fpga_family to "arria5" when you instantiate
You can also set the generic g_use_default_plls to FALSE if you want
to instantiate your own PLLs and provide the clock signals to the PSP.
Otherwise, the default PLLs will be instantiated inside the platform.
System PLL which takes as input a 125MHz clock signal and generates
a 62.5MHz system clock and a 125MHz reference clock.
DMTD PLL which takes as input a 20MHz clock signal and generates a
62.5MHz clock for DMTD.
External reference PLL (only if g_with_external_clock_input=TRUE)
which takes as input a 10MHz clock signal and generates a 125MHz
multiplied external reference clock.