Development
Coding conventions:*
In general, the OHR VHDL coding guidelines should be followed. However,
due to large complexity of some of the modules, there are some
exceptions:
- you must not prefix signals with
s_
. - if the module inteface comprises multiple repetitive signals, use
structures instead of flattened
std_logic
ports. This makes the interconnections between the modules much easier to understand and less error prone. For compatibility with Verilog and gate-level simulations, you should provide a module with flattened ports. Names of modules with structs in ports are prefixed withx
, for example:
-- version with structs
entity xwr_module is
port (
wb_i : t_wishbone_slave_in;
wb_o : t_wishbone_slave_out
);
end xwr_module;
-- version without structs
entity wr_module is
port (
wb_adr_i : in std_logic_vector;
wb_dat_i : in std_logic_vector;
wb_ack_o : out std_logic;
);
end wr_module;
- do not type in UPPERCASE.