adding BSP for PXIe-FMC board with Xilinx ZU7

f1a2fe27 · Grzegorz Daniluk · 57c9e69e · f1a2fe27 · f1a2fe27 · f1a2fe27
Commit f1a2fe27 authored Aug 17, 2020 by Grzegorz Daniluk
9 changed files
--- a/board/Manifest.py
+++ b/board/Manifest.py
 try:
-    if board in ["spec", "svec", "vfchd", "clbv2", "clbv3", "clbv4", "common"]:
+    if board in ["spec", "svec", "vfchd", "clbv2", "clbv3", "clbv4", "pxie-fmc", "common"]:
        modules = {"local" : [ board ] }
 except NameError:
    pass
--- a/board/pxie-fmc/Manifest.py
+++ b/board/pxie-fmc/Manifest.py
+files = [
+    "wr_pxie_fmc_pkg.vhd",
+    "xwrc_board_pxie_fmc.vhd",
+]
+
+modules = {
+    "local" : [
+        "../common",
+    ]
+}
--- a/board/pxie-fmc/wr_pxie_fmc_pkg.vhd
+++ b/board/pxie-fmc/wr_pxie_fmc_pkg.vhd
+-------------------------------------------------------------------------------
+-- Title      : WRPC Wrapper for SPEC package
+-- Project    : WR PTP Core
+-- URL        : http://www.ohwr.org/projects/wr-cores/wiki/Wrpc_core
+-------------------------------------------------------------------------------
+-- File       : wr_pxie_fmc_pkg.vhd
+-- Author(s)  : Greg Daniluk <grzegorz.daniluk@cern.ch>
+-- Company    : CERN (BE-CO-HT)
+-- Standard   : VHDL'93
+-------------------------------------------------------------------------------
+-- Copyright (c) 2020 CERN
+-------------------------------------------------------------------------------
+-- GNU LESSER GENERAL PUBLIC LICENSE
+--
+-- This source file is free software; you can redistribute it   
+-- and/or modify it under the terms of the GNU Lesser General   
+-- Public License as published by the Free Software Foundation; 
+-- either version 2.1 of the License, or (at your option) any   
+-- later version.                                               
+--
+-- This source is distributed in the hope that it will be       
+-- useful, but WITHOUT ANY WARRANTY; without even the implied   
+-- warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      
+-- PURPOSE.  See the GNU Lesser General Public License for more 
+-- details.                                                     
+--
+-- You should have received a copy of the GNU Lesser General    
+-- Public License along with this source; if not, download it   
+-- from http://www.gnu.org/licenses/lgpl-2.1.html
+-- 
+-------------------------------------------------------------------------------
+
+library ieee;
+use ieee.std_logic_1164.all;
+
+library work;
+use work.wishbone_pkg.all;
+use work.wrcore_pkg.all;
+use work.wr_fabric_pkg.all;
+use work.endpoint_pkg.all;
+use work.wr_board_pkg.all;
+use work.wr_xilinx_pkg.all;
+use work.streamers_pkg.all;
+
+package wr_pxie_fmc_pkg is
+
+  component xwrc_board_pxie_fmc is
+    generic(
+      g_simulation                : integer              := 0;
+      g_aux_clks                  : integer              := 0;
+      g_dpram_initf               : string               := "default_xilinx";
+      g_aux_sdb                   : t_sdb_device         := c_wrc_periph3_sdb
+      );
+    port (
+      areset_n_i             : in  std_logic;
+      areset_edge_n_i        : in  std_logic := '1';
+      wr_clk_helper_125m_p_i : in  std_logic;
+      wr_clk_helper_125m_n_i : in  std_logic;
+      wr_clk_main_125m_p_i   : in  std_logic;
+      wr_clk_main_125m_n_i   : in  std_logic;
+      wr_clk_sfp_125m_p_i    : in  std_logic;
+      wr_clk_sfp_125m_n_i    : in  std_logic;
+  
+      clk_sys_62m5_o      : out std_logic;
+      clk_ref_125m_o      : out std_logic;
+      rst_sys_62m5_n_o    : out std_logic;
+      rst_ref_125m_n_o    : out std_logic;
+  
+      plldac_sclk_o   : out std_logic;
+      plldac_din_o    : out std_logic;
+      pll25dac_cs_n_o : out std_logic;
+      pll20dac_cs_n_o : out std_logic;
+  
+      sfp_txp_o         : out std_logic;
+      sfp_txn_o         : out std_logic;
+      sfp_rxp_i         : in  std_logic;
+      sfp_rxn_i         : in  std_logic;
+      sfp_det_i         : in  std_logic := '1';
+      sfp_sda_i         : in  std_logic;
+      sfp_sda_o         : out std_logic;
+      sfp_scl_i         : in  std_logic;
+      sfp_scl_o         : out std_logic;
+      sfp_rate_select_o : out std_logic;
+      sfp_tx_fault_i    : in  std_logic := '0';
+      sfp_tx_disable_o  : out std_logic;
+      sfp_los_i         : in  std_logic := '0';
+  
+      eeprom_sda_i : in  std_logic;
+      eeprom_sda_o : out std_logic;
+      eeprom_scl_i : in  std_logic;
+      eeprom_scl_o : out std_logic;
+      uart_rxd_i : in  std_logic;
+      uart_txd_o : out std_logic;
+  
+      wb_slave_o   : out t_wishbone_slave_out;
+      wb_slave_i   : in  t_wishbone_slave_in := cc_dummy_slave_in;
+      aux_master_o : out t_wishbone_master_out;
+      aux_master_i : in  t_wishbone_master_in := cc_dummy_master_in;
+  
+      wrf_src_o    : out t_wrf_source_out;
+      wrf_src_i    : in  t_wrf_source_in := c_dummy_src_in;
+      wrf_snk_o    : out t_wrf_sink_out;
+      wrf_snk_i    : in  t_wrf_sink_in   := c_dummy_snk_in;
+  
+      tm_link_up_o    : out std_logic;
+      tm_time_valid_o : out std_logic;
+      tm_tai_o        : out std_logic_vector(39 downto 0);
+      tm_cycles_o     : out std_logic_vector(27 downto 0);
+  
+      led_act_o  : out std_logic;
+      led_link_o : out std_logic;
+      pps_p_o    : out std_logic;
+      pps_led_o  : out std_logic;
+      link_ok_o  : out std_logic);
+  
+  end component xwrc_board_pxie_fmc;
+
+end wr_pxie_fmc_pkg;
--- a/board/pxie-fmc/xwrc_board_pxie_fmc.vhd
+++ b/board/pxie-fmc/xwrc_board_pxie_fmc.vhd
+-------------------------------------------------------------------------------
+-- Title      : WRPC Wrapper for PXIe-FMC Carrier
+-- Project    : WR PTP Core
+-- URL        : http://www.ohwr.org/projects/wr-cores/wiki/Wrpc_core
+-------------------------------------------------------------------------------
+-- File       : xwrc_board_pxie_fmc.vhd
+-- Author(s)  : Greg Daniluk <grzegorz.daniluk@cern.ch>
+-- Company    : CERN (BE-CO-HT)
+-- Standard   : VHDL'93
+-------------------------------------------------------------------------------
+-- Description: Top-level wrapper for WR PTP core including all the modules
+-- needed to operate the core on the EN-SMM PXIe-FMC board.
+-- https://ohwr.org/project/pxie-fmc
+-------------------------------------------------------------------------------
+-- Copyright (c) 2020 CERN
+-------------------------------------------------------------------------------
+-- GNU LESSER GENERAL PUBLIC LICENSE
+--
+-- This source file is free software; you can redistribute it   
+-- and/or modify it under the terms of the GNU Lesser General   
+-- Public License as published by the Free Software Foundation; 
+-- either version 2.1 of the License, or (at your option) any   
+-- later version.                                               
+--
+-- This source is distributed in the hope that it will be       
+-- useful, but WITHOUT ANY WARRANTY; without even the implied   
+-- warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      
+-- PURPOSE.  See the GNU Lesser General Public License for more 
+-- details.                                                     
+--
+-- You should have received a copy of the GNU Lesser General    
+-- Public License along with this source; if not, download it   
+-- from http://www.gnu.org/licenses/lgpl-2.1.html
+-- 
+-------------------------------------------------------------------------------
+
+library ieee;
+use ieee.std_logic_1164.all;
+
+library work;
+use work.gencores_pkg.all;
+use work.wrcore_pkg.all;
+use work.wishbone_pkg.all;
+use work.wr_fabric_pkg.all;
+use work.endpoint_pkg.all;
+use work.streamers_pkg.all;
+use work.wr_xilinx_pkg.all;
+use work.wr_board_pkg.all;
+use work.wr_pxie_fmc_pkg.all;
+
+library unisim;
+use unisim.vcomponents.all;
+
+entity xwrc_board_pxie_fmc is
+  generic(
+    -- set to 1 to speed up some initialization processes during simulation
+    g_simulation                : integer              := 0;
+    -- Number of aux clocks syntonized by WRPC to WR timebase
+    g_aux_clks                  : integer              := 0;
+    -- memory initialisation file for embedded CPU
+    g_dpram_initf               : string               := "default_xilinx";
+    g_aux_sdb                   : t_sdb_device         := c_wrc_periph3_sdb
+    );
+  port (
+    ---------------------------------------------------------------------------
+    -- Clocks/resets
+    ---------------------------------------------------------------------------
+    -- Reset input (active low, can be async)
+    areset_n_i          : in  std_logic;
+    -- Optional reset input active low with rising edge detection. Does not
+    -- reset PLLs.
+    areset_edge_n_i        : in  std_logic := '1';
+    -- Clock inputs from the board
+    wr_clk_helper_125m_p_i : in  std_logic;
+    wr_clk_helper_125m_n_i : in  std_logic;
+    wr_clk_main_125m_p_i   : in  std_logic;
+    wr_clk_main_125m_n_i   : in  std_logic;
+    wr_clk_sfp_125m_p_i    : in  std_logic;
+    wr_clk_sfp_125m_n_i    : in  std_logic;
+
+    -- 62.5MHz sys clock output
+    clk_sys_62m5_o      : out std_logic;
+    -- 125MHz ref clock output
+    clk_ref_125m_o      : out std_logic;
+    -- active low reset outputs, synchronous to 62m5 and 125m clocks
+    rst_sys_62m5_n_o    : out std_logic;
+    rst_ref_125m_n_o    : out std_logic;
+
+    ---------------------------------------------------------------------------
+    -- Shared SPI interface to DACs
+    ---------------------------------------------------------------------------
+    plldac_sclk_o   : out std_logic;
+    plldac_din_o    : out std_logic;
+    pll25dac_cs_n_o : out std_logic;
+    pll20dac_cs_n_o : out std_logic;
+
+    ---------------------------------------------------------------------------
+    -- SFP I/O for transceiver and SFP management info
+    ---------------------------------------------------------------------------
+    sfp_txp_o         : out std_logic;
+    sfp_txn_o         : out std_logic;
+    sfp_rxp_i         : in  std_logic;
+    sfp_rxn_i         : in  std_logic;
+    sfp_det_i         : in  std_logic := '1';
+    sfp_sda_i         : in  std_logic;
+    sfp_sda_o         : out std_logic;
+    sfp_scl_i         : in  std_logic;
+    sfp_scl_o         : out std_logic;
+    sfp_rate_select_o : out std_logic;
+    sfp_tx_fault_i    : in  std_logic := '0';
+    sfp_tx_disable_o  : out std_logic;
+    sfp_los_i         : in  std_logic := '0';
+
+    ---------------------------------------------------------------------------
+    -- I2C EEPROM
+    ---------------------------------------------------------------------------
+    eeprom_sda_i : in  std_logic;
+    eeprom_sda_o : out std_logic;
+    eeprom_scl_i : in  std_logic;
+    eeprom_scl_o : out std_logic;
+
+    ---------------------------------------------------------------------------
+    -- UART
+    ---------------------------------------------------------------------------
+    uart_rxd_i : in  std_logic;
+    uart_txd_o : out std_logic;
+
+    ---------------------------------------------------------------------------
+    -- External WB interface
+    ---------------------------------------------------------------------------
+    wb_slave_o : out t_wishbone_slave_out;
+    wb_slave_i : in  t_wishbone_slave_in := cc_dummy_slave_in;
+
+    aux_master_o : out t_wishbone_master_out;
+    aux_master_i : in  t_wishbone_master_in := cc_dummy_master_in;
+
+    ---------------------------------------------------------------------------
+    -- WR fabric interface (when g_fabric_iface = "plainfbrc")
+    ---------------------------------------------------------------------------
+    wrf_src_o : out t_wrf_source_out;
+    wrf_src_i : in  t_wrf_source_in := c_dummy_src_in;
+    wrf_snk_o : out t_wrf_sink_out;
+    wrf_snk_i : in  t_wrf_sink_in   := c_dummy_snk_in;
+
+    ---------------------------------------------------------------------------
+    -- Timecode I/F
+    ---------------------------------------------------------------------------
+    tm_link_up_o    : out std_logic;
+    tm_time_valid_o : out std_logic;
+    tm_tai_o        : out std_logic_vector(39 downto 0);
+    tm_cycles_o     : out std_logic_vector(27 downto 0);
+
+    ---------------------------------------------------------------------------
+    -- Buttons, LEDs and PPS output
+    ---------------------------------------------------------------------------
+    led_act_o  : out std_logic;
+    led_link_o : out std_logic;
+    -- 1PPS output
+    pps_p_o    : out std_logic;
+    pps_led_o  : out std_logic;
+    -- Link ok indication
+    link_ok_o  : out std_logic
+    );
+
+end entity xwrc_board_pxie_fmc;
+
+
+architecture struct of xwrc_board_pxie_fmc is
+
+  -- PLLs, clocks
+  signal clk_125m_pllref_buf : std_logic;
+  signal clk_125m_dmtd_buf   : std_logic;
+  signal clk_pll_62m5        : std_logic;
+  signal clk_pll_125m        : std_logic;
+  signal clk_pll_dmtd        : std_logic;
+  signal pll_locked          : std_logic;
+
+  -- Reset logic
+  signal areset_edge_ppulse : std_logic;
+  signal rst_62m5_n         : std_logic;
+  signal rstlogic_arst      : std_logic;
+  signal rstlogic_clk_in    : std_logic_vector(1 downto 0);
+  signal rstlogic_rst_out   : std_logic_vector(1 downto 0);
+
+  -- PLL DAC ARB
+  signal dac_hpll_load_p1 : std_logic;
+  signal dac_hpll_data    : std_logic_vector(15 downto 0);
+  signal dac_dpll_load_p1 : std_logic;
+  signal dac_dpll_data    : std_logic_vector(15 downto 0);
+
+  -- PHY
+  signal phy16_to_wrc   : t_phy_16bits_to_wrc;
+  signal phy16_from_wrc : t_phy_16bits_from_wrc;
+
+begin  -- architecture struct
+
+  -----------------------------------------------------------------------------
+  -- Platform-dependent part (PHY, PLLs, buffers, etc)
+  -----------------------------------------------------------------------------
+
+  cmp_ibufgds_pllmain : IBUFDS
+    generic map (
+      DQS_BIAS     => "FALSE")
+    port map (
+      O  => clk_125m_pllref_buf,
+      I  => wr_clk_main_125m_p_i,
+      IB => wr_clk_main_125m_n_i);
+
+  cmp_ibufgds_dmtd : IBUFDS
+    generic map (
+      DQS_BIAS     => "FALSE")
+    port map (
+      O  => clk_125m_dmtd_buf,
+      I  => wr_clk_helper_125m_p_i,
+      IB => wr_clk_helper_125m_n_i);
+
+  cmp_xwrc_platform : xwrc_platform_xilinx
+    generic map (
+      g_fpga_family               => "zynqus",
+      g_with_external_clock_input => FALSE,
+      g_use_default_plls          => TRUE,
+      g_simulation                => g_simulation)
+    port map (
+      areset_n_i            => areset_n_i,
+      clk_125m_pllref_i     => clk_125m_pllref_buf,
+      clk_125m_gtp_p_i      => wr_clk_sfp_125m_p_i,
+      clk_125m_gtp_n_i      => wr_clk_sfp_125m_n_i,
+      clk_125m_dmtd_i       => clk_125m_dmtd_buf,
+      sfp_txn_o             => sfp_txn_o,
+      sfp_txp_o             => sfp_txp_o,
+      sfp_rxn_i             => sfp_rxn_i,
+      sfp_rxp_i             => sfp_rxp_i,
+      sfp_tx_fault_i        => sfp_tx_fault_i,
+      sfp_los_i             => sfp_los_i,
+      sfp_tx_disable_o      => sfp_tx_disable_o,
+      clk_62m5_sys_o        => clk_pll_62m5,
+      clk_125m_ref_o        => clk_pll_125m,
+      clk_62m5_dmtd_o       => clk_pll_dmtd,
+      pll_locked_o          => pll_locked,
+      phy16_o               => phy16_to_wrc,
+      phy16_i               => phy16_from_wrc);
+
+  clk_ref_125m_o <= clk_pll_125m;
+  clk_sys_62m5_o <= clk_pll_62m5;
+
+  -----------------------------------------------------------------------------
+  -- Reset logic
+  -----------------------------------------------------------------------------
+  -- Detect when areset_edge_n_i goes high (end of reset) and use this edge to
+  -- generate rstlogic_arst. This is needed to connect optional reset like PCIe
+  -- reset. When baord runs standalone, we need to ignore PCIe reset being
+  -- constantly low.
+  cmp_arst_edge: gc_sync_ffs
+    generic map (
+      g_sync_edge => "positive")
+    port map (
+      clk_i    => clk_pll_62m5,
+      rst_n_i  => '1',
+      data_i   => areset_edge_n_i,
+      ppulse_o => areset_edge_ppulse);
+
+  -- logic AND of all async reset sources (active high)
+  rstlogic_arst <= (not pll_locked) and (not areset_n_i) and areset_edge_ppulse;
+
+  -- concatenation of all clocks required to have synced resets
+  rstlogic_clk_in(0)          <= clk_pll_62m5;
+  rstlogic_clk_in(1)          <= clk_pll_125m;
+
+  cmp_rstlogic_reset : gc_reset_multi_aasd
+    generic map (
+      g_CLOCKS  => 2,   -- 62.5MHz, 125MHz
+      g_RST_LEN => 16)  -- 16 clock cycles
+    port map (
+      arst_i  => rstlogic_arst,
+      clks_i  => rstlogic_clk_in,
+      rst_n_o => rstlogic_rst_out);
+
+  -- distribution of resets (already synchronized to their clock domains)
+  rst_62m5_n <= rstlogic_rst_out(0);
+
+  rst_sys_62m5_n_o <= rst_62m5_n;
+  rst_ref_125m_n_o <= rstlogic_rst_out(1);
+
+  -----------------------------------------------------------------------------
+  -- 2x SPI DAC
+  -----------------------------------------------------------------------------
+
+  cmp_dac_arb : spec_serial_dac_arb
+    generic map (
+      g_invert_sclk    => FALSE,
+      g_num_extra_bits => 8)
+    port map (
+      clk_i         => clk_pll_62m5,
+      rst_n_i       => rst_62m5_n,
+      val1_i        => dac_dpll_data,
+      load1_i       => dac_dpll_load_p1,
+      val2_i        => dac_hpll_data,
+      load2_i       => dac_hpll_load_p1,
+      dac_cs_n_o(0) => pll25dac_cs_n_o,
+      dac_cs_n_o(1) => pll20dac_cs_n_o,
+      dac_sclk_o    => plldac_sclk_o,
+      dac_din_o     => plldac_din_o);
+
+  -----------------------------------------------------------------------------
+  -- The WR PTP Core
+  -----------------------------------------------------------------------------
+
+  cmp_board_common : xwrc_board_common
+    generic map (
+      g_simulation                => g_simulation,
+      g_verbose                   => TRUE,
+      g_with_external_clock_input => FALSE,
+      g_board_name                => "PXIE",
+      g_phys_uart                 => TRUE,
+      g_virtual_uart              => TRUE,
+      g_ep_rxbuf_size             => 1024,
+      g_tx_runt_padding           => TRUE,
+      g_dpram_initf               => g_dpram_initf,
+      g_dpram_size                => 131072/4,
+      g_interface_mode            => PIPELINED,
+      g_address_granularity       => BYTE,
+      g_aux_sdb                   => g_aux_sdb,
+      g_softpll_enable_debugger   => FALSE,
+      g_vuart_fifo_size           => 1024,
+      g_pcs_16bit                 => TRUE,
+      g_fabric_iface              => PLAIN)
+    port map (
+      clk_sys_i            => clk_pll_62m5,
+      clk_dmtd_i           => clk_pll_dmtd,
+      clk_ref_i            => clk_pll_125m,
+      rst_n_i              => rst_62m5_n,
+      dac_hpll_load_p1_o   => dac_hpll_load_p1,
+      dac_hpll_data_o      => dac_hpll_data,
+      dac_dpll_load_p1_o   => dac_dpll_load_p1,
+      dac_dpll_data_o      => dac_dpll_data,
+      phy16_o              => phy16_from_wrc,
+      phy16_i              => phy16_to_wrc,
+      scl_o                => eeprom_scl_o,
+      scl_i                => eeprom_scl_i,
+      sda_o                => eeprom_sda_o,
+      sda_i                => eeprom_sda_i,
+      sfp_scl_o            => sfp_scl_o,
+      sfp_scl_i            => sfp_scl_i,
+      sfp_sda_o            => sfp_sda_o,
+      sfp_sda_i            => sfp_sda_i,
+      sfp_det_i            => sfp_det_i,
+      uart_rxd_i           => uart_rxd_i,
+      uart_txd_o           => uart_txd_o,
+      wb_slave_i           => wb_slave_i,
+      wb_slave_o           => wb_slave_o,
+      aux_master_o         => aux_master_o,
+      aux_master_i         => aux_master_i,
+      wrf_src_o            => wrf_src_o,
+      wrf_src_i            => wrf_src_i,
+      wrf_snk_o            => wrf_snk_o,
+      wrf_snk_i            => wrf_snk_i,
+      tm_link_up_o         => tm_link_up_o,
+      tm_time_valid_o      => tm_time_valid_o,
+      tm_tai_o             => tm_tai_o,
+      tm_cycles_o          => tm_cycles_o,
+      led_act_o            => led_act_o,
+      led_link_o           => led_link_o,
+      pps_p_o              => pps_p_o,
+      pps_led_o            => pps_led_o,
+      link_ok_o            => link_ok_o);
+
+  sfp_rate_select_o <= '1';
+
+end architecture struct;
--- a/syn/pxie_fmc_ref_design/Manifest.py
+++ b/syn/pxie_fmc_ref_design/Manifest.py
+board  = "pxie-fmc"
+target = "xilinx"
+action = "synthesis"
+
+syn_device = "xczu7cg"
+syn_grade = "-1"
+syn_package = "ffvf1517"
+
+syn_top = "pxie_fmc_ref_top"
+syn_project = "pxie_fmc_ref_top"
+syn_tool = "vivado"
+
+files = [
+    "pxie_fmc_ref_design.xdc",
+]
+
+modules = {
+    "local" : [
+        "../../top/pxie_fmc_ref_design/",
+    ],
+}
+
--- a/syn/pxie_fmc_ref_design/pxie_fmc.tcl
+++ b/syn/pxie_fmc_ref_design/pxie_fmc.tcl
+set projDir [file dirname [info script]]
+
+set_param general.maxThreads 8
+get_param general.maxThreads
+
+# Xilinx speed grades: 1,2,3: 1 = slowest, 3 = fastest
+set speed   1
+set fpga xczu7cg-ffvf1517-${speed}-e
+set device  ${fpga}
+
+set top     pxie_fmc_ref_top
+
+# Check hdlmake has generated file dependencies
+if {![file exists files.tcl]} {
+    puts "File: files.tcl not found, please check hdlmake has generated the file dependencies."
+    exit 1
+}
+
+source files.tcl
+
+# constraint files
+read_xdc $projDir/pxie_fmc_ref_design.xdc
+
+set start_time [clock seconds]
+
+synth_design -top ${top} -part ${device} > ${top}_synth.log
+write_checkpoint -force ${top}_synth
+
+opt_design -directive Explore -verbose > ${top}_opt.log
+write_checkpoint -force ${top}_opt
+
+place_design -directive Explore > ${top}_place.log
+write_checkpoint -force ${projDir}/${top}_place
+
+phys_opt_design -directive Explore > ${top}_phys_opt.log
+write_checkpoint -force ${projDir}/${top}_phys_opt
+
+route_design -directive Explore > ${top}_route.log
+write_checkpoint -force ${projDir}/${top}_route
+
+report_timing_summary -file ${top}_timing_summary.rpt
+report_timing -sort_by group -max_paths 100 -path_type full -file ${top}_timing.rpt
+report_utilization -hierarchical -file ${top}_utilization.rpt
+report_io -file ${top}_pin.rpt
+
+# bitstream configuration...
+write_bitstream -force ${projDir}/${top}.bit
+
+set end_time [clock seconds]
+set total_time [ expr { $end_time - $start_time} ]
+set absolute_time [clock format $total_time -format {%H:%M:%S} -gmt true ]
+puts "\ntotal build time: $absolute_time\n"
--- a/syn/pxie_fmc_ref_design/pxie_fmc_ref_design.xdc
+++ b/syn/pxie_fmc_ref_design/pxie_fmc_ref_design.xdc
+##################
+# Clocks
+##################
+create_clock -period 8.000 -name wr_clk_helper_125m -waveform {0.000  4.000} [get_ports {wr_clk_helper_125m_p_i}]
+create_clock -period 8.000 -name wr_clk_main_125m   -waveform {0.000  4.000} [get_ports {wr_clk_main_125m_p_i}]
+create_clock -period 8.000 -name wr_clk_sfp_125m    -waveform {0.000  4.000} [get_ports {wr_clk_sfp_125m_p_i}]
+create_clock -period 16.000 -name gth_txclk         -waveform {0.000 8.000} [get_nets cmp_xwrc_board_pxie_fmc/cmp_xwrc_platform/gen_phy_zynqus.cmp_gth/tx_out_clk_o]
+create_clock -period 16.000 -name gth_rxclk         -waveform {0.000 8.000} [get_nets cmp_xwrc_board_pxie_fmc/cmp_xwrc_platform/gen_phy_zynqus.cmp_gth/rx_rbclk_o]
+
+create_generated_clock -name clk_dmtd -source [get_ports {wr_clk_helper_125m_p_i}] -divide_by 2 [get_pins cmp_xwrc_board_pxie_fmc/cmp_xwrc_platform/gen_default_plls.gen_zynqus_default_plls.cmp_clk_dmtd_buf_o/O]
+
+set_clock_groups -asynchronous -group {wr_clk_main_125m wr_clk_sfp_125m} -group {wr_clk_helper_125m clk_dmtd} -group {gth_txclk} -group {gth_rxclk}
+
+
+##################
+# I/O constraints
+##################
+
+set_property PACKAGE_PIN AU9 [get_ports {user_led_o[0]}]
+set_property PACKAGE_PIN AW9 [get_ports {user_led_o[1]}]
+set_property PACKAGE_PIN AV9 [get_ports {user_led_o[2]}]
+set_property PACKAGE_PIN AW10 [get_ports eeprom_scl_b]
+set_property PACKAGE_PIN AW11 [get_ports eeprom_sda_b]
+set_property PACKAGE_PIN K14 [get_ports pll25dac_cs_n_o]
+set_property PACKAGE_PIN L12 [get_ports pll20dac_cs_n_o]
+set_property PACKAGE_PIN K13 [get_ports plldac_din_o]
+set_property PACKAGE_PIN J14 [get_ports plldac_sclk_o]
+set_property PACKAGE_PIN A11 [get_ports pps_p_o]
+set_property PACKAGE_PIN K12 [get_ports ps_por_i]
+set_property PACKAGE_PIN G10 [get_ports sfp_det_i]
+set_property PACKAGE_PIN K10 [get_ports sfp_los_i]
+set_property PACKAGE_PIN AM2 [get_ports sfp_rxp_i]
+set_property PACKAGE_PIN AH10 [get_ports wr_clk_sfp_125m_p_i]
+set_property PACKAGE_PIN AU21 [get_ports sfp_scl_b]
+set_property PACKAGE_PIN AT21 [get_ports sfp_sda_b]
+set_property PACKAGE_PIN D12 [get_ports sfp_tx_disable_o]
+set_property PACKAGE_PIN C12 [get_ports uart_txd_o]
+set_property PACKAGE_PIN C14 [get_ports uart_rxd_i]
+set_property PACKAGE_PIN AP20 [get_ports wr_clk_helper_125m_p_i]
+set_property PACKAGE_PIN AN19 [get_ports wr_clk_main_125m_p_i]
+
+set_property IOSTANDARD LVCMOS33 [get_ports pll20dac_cs_n_o]
+set_property IOSTANDARD LVCMOS33 [get_ports pll25dac_cs_n_o]
+set_property IOSTANDARD LVCMOS18 [get_ports eeprom_sda_b]
+set_property IOSTANDARD LVCMOS18 [get_ports eeprom_scl_b]
+set_property IOSTANDARD LVCMOS18 [get_ports {user_led_o[0]}]
+set_property IOSTANDARD LVCMOS18 [get_ports {user_led_o[1]}]
+set_property IOSTANDARD LVCMOS18 [get_ports {user_led_o[2]}]
+set_property IOSTANDARD LVCMOS33 [get_ports plldac_din_o]
+set_property IOSTANDARD LVCMOS33 [get_ports plldac_sclk_o]
+set_property IOSTANDARD LVCMOS33 [get_ports pps_p_o]
+set_property IOSTANDARD LVCMOS33 [get_ports ps_por_i]
+set_property IOSTANDARD LVCMOS33 [get_ports sfp_det_i]
+set_property IOSTANDARD LVCMOS18 [get_ports sfp_scl_b]
+set_property IOSTANDARD LVCMOS33 [get_ports sfp_los_i]
+set_property IOSTANDARD LVCMOS18 [get_ports sfp_sda_b]
+set_property IOSTANDARD LVCMOS33 [get_ports sfp_tx_disable_o]
+set_property IOSTANDARD LVCMOS33 [get_ports uart_txd_o]
+set_property IOSTANDARD LVCMOS33 [get_ports uart_rxd_i]
+set_property IOSTANDARD LVDS [get_ports wr_clk_helper_125m_p_i]
+set_property IOSTANDARD LVDS [get_ports wr_clk_main_125m_p_i]
+
+set_property OFFCHIP_TERM NONE [get_ports eeprom_scl_b]
+set_property OFFCHIP_TERM NONE [get_ports eeprom_sda_b]
+set_property OFFCHIP_TERM NONE [get_ports pll20dac_cs_n_o]
+set_property OFFCHIP_TERM NONE [get_ports pll25dac_cs_n_o]
+set_property OFFCHIP_TERM NONE [get_ports plldac_din_o]
+set_property OFFCHIP_TERM NONE [get_ports plldac_sclk_o]
+set_property OFFCHIP_TERM NONE [get_ports pps_p_o]
+set_property OFFCHIP_TERM NONE [get_ports sfp_scl_b]
+set_property OFFCHIP_TERM NONE [get_ports sfp_sda_b]
+set_property OFFCHIP_TERM NONE [get_ports sfp_tx_disable_o]
+set_property OFFCHIP_TERM NONE [get_ports uart_txd_o]
+set_property OFFCHIP_TERM NONE [get_ports user_led_o[2]]
+set_property OFFCHIP_TERM NONE [get_ports user_led_o[1]]
+set_property OFFCHIP_TERM NONE [get_ports user_led_o[0]]
+
+
+#revert back to original instance
+current_instance -quiet
--- a/top/pxie_fmc_ref_design/Manifest.py
+++ b/top/pxie_fmc_ref_design/Manifest.py
+fetchto = "../../ip_cores"
+
+files = [ "pxie_fmc_ref_top.vhd", ]
+
+modules = {
+    "local" : [
+        "../../",
+    ],
+    "git" : [
+        "git://ohwr.org/hdl-core-lib/general-cores.git",
+        "git://ohwr.org/hdl-core-lib/gn4124-core.git",
+        "git://ohwr.org/hdl-core-lib/etherbone-core.git",
+    ],
+}
--- a/top/pxie_fmc_ref_design/pxie_fmc_ref_top.vhd
+++ b/top/pxie_fmc_ref_design/pxie_fmc_ref_top.vhd
+-------------------------------------------------------------------------------
+-- Title      : WRPC reference design for PXIe-FMC board
+-- Project    : WR PTP Core
+-- URL        : http://www.ohwr.org/projects/wr-cores/wiki/Wrpc_core
+-------------------------------------------------------------------------------
+-- File       : pxie_fmc_ref_top.vhd
+-- Author(s)  : Greg Daniluk <grzegorz.daniluk@cern.ch>
+-- Company    : CERN (BE-CO-HT)
+-- Standard   : VHDL'93
+-------------------------------------------------------------------------------
+-- Description: Top-level file for the WRPC reference design on the PXIe-FMC
+-- board.
+--
+-- This is a reference top HDL that instanciates the WR PTP Core together with
+-- its peripherals to be run on a PXIe-FMC board.
+--
+-- There are two main usecases for this HDL file:
+-- * let new users easily synthesize a WR PTP Core bitstream that can be run on
+--   reference hardware
+-- * provide a reference top HDL file showing how the WRPC can be instantiated
+--   in HDL projects.
+--
+-- PXIe-FMC: https://ohwr.org/project/pxie-fmc
+--
+-------------------------------------------------------------------------------
+-- Copyright (c) 2020 CERN
+-------------------------------------------------------------------------------
+-- GNU LESSER GENERAL PUBLIC LICENSE
+--
+-- This source file is free software; you can redistribute it
+-- and/or modify it under the terms of the GNU Lesser General
+-- Public License as published by the Free Software Foundation;
+-- either version 2.1 of the License, or (at your option) any
+-- later version.
+--
+-- This source is distributed in the hope that it will be
+-- useful, but WITHOUT ANY WARRANTY; without even the implied
+-- warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR
+-- PURPOSE.  See the GNU Lesser General Public License for more
+-- details.
+--
+-- You should have received a copy of the GNU Lesser General
+-- Public License along with this source; if not, download it
+-- from http://www.gnu.org/licenses/lgpl-2.1.html
+--
+-------------------------------------------------------------------------------
+
+library ieee;
+use ieee.std_logic_1164.all;
+use ieee.numeric_std.all;
+
+library work;
+use work.gencores_pkg.all;
+use work.wishbone_pkg.all;
+use work.gn4124_core_pkg.all;
+use work.wr_board_pkg.all;
+use work.wr_pxie_fmc_pkg.all;
+
+library unisim;
+use unisim.vcomponents.all;
+
+entity pxie_fmc_ref_top is
+  generic (
+    -- Simulation-mode enable parameter. Set by default (synthesis) to 0, and
+    -- changed to non-zero in the instantiation of the top level DUT in the testbench.
+    -- Its purpose is to reduce some internal counters/timeouts to speed up simulations.
+    g_SIMULATION: integer := 0);
+  port (
+    ---------------------------------------------------------------------------
+    -- Clocks/resets
+    ---------------------------------------------------------------------------
+    ps_por_i               : in std_logic;
+    wr_clk_helper_125m_p_i : in  std_logic;
+    wr_clk_helper_125m_n_i : in  std_logic;
+    wr_clk_main_125m_p_i   : in  std_logic;
+    wr_clk_main_125m_n_i   : in  std_logic;
+    wr_clk_sfp_125m_p_i    : in  std_logic;
+    wr_clk_sfp_125m_n_i    : in  std_logic;
+
+    ---------------------------------------------------------------------------
+    -- SPI interface to DACs
+    ---------------------------------------------------------------------------
+    plldac_sclk_o   : out std_logic;
+    plldac_din_o    : out std_logic;
+    pll25dac_cs_n_o : out std_logic;
+    pll20dac_cs_n_o : out std_logic;
+
+    ---------------------------------------------------------------------------
+    -- SFP I/Os for transceiver
+    ---------------------------------------------------------------------------
+    sfp_txp_o         : out std_logic;
+    sfp_txn_o         : out std_logic;
+    sfp_rxp_i         : in  std_logic;
+    sfp_rxn_i         : in  std_logic;
+    sfp_det_i         : in  std_logic;
+    sfp_sda_b         : inout std_logic;
+    sfp_scl_b         : inout std_logic;
+    sfp_tx_disable_o  : out std_logic;
+    sfp_los_i         : in  std_logic;
+
+    ---------------------------------------------------------------------------
+    -- EEPROM I2C interface for storing configuration and accessing unique ID
+    ---------------------------------------------------------------------------
+    eeprom_sda_b  : inout std_logic;
+    eeprom_scl_b  : inout std_logic;
+    ---------------------------------------------------------------------------
+    -- UART
+    ---------------------------------------------------------------------------
+    uart_rxd_i    : in  std_logic;
+    uart_txd_o    : out std_logic;
+
+    ---------------------------------------------------------------------------
+    -- LEDs
+    ---------------------------------------------------------------------------
+    user_led_o    : out std_logic_vector(2 downto 0);
+    pps_p_o    : out std_logic
+  );
+end entity pxie_fmc_ref_top;
+
+architecture top of pxie_fmc_ref_top is
+
+  signal rst_n : std_logic;
+  signal clk_sys_62m5 : std_logic;
+
+  signal sfp_scl_out, sfp_scl_in : std_logic;
+  signal sfp_sda_out, sfp_sda_in : std_logic;
+  signal eeprom_scl_out, eeprom_scl_in : std_logic;
+  signal eeprom_sda_out, eeprom_sda_in : std_logic;
+
+begin
+
+  -- do not use PS_POR for now
+  rst_n <= '1'; --not ps_por_i;
+
+  user_led_o(2) <= '1';
+
+  cmp_xwrc_board_pxie_fmc : xwrc_board_pxie_fmc
+    generic map (
+      g_simulation   => g_SIMULATION,
+      g_dpram_initf  => "../../bin/wrpc/wrc_pxie.bram")
+    port map (
+      areset_n_i             => rst_n,
+      wr_clk_helper_125m_p_i => wr_clk_helper_125m_p_i,
+      wr_clk_helper_125m_n_i => wr_clk_helper_125m_n_i, 
+      wr_clk_main_125m_p_i   => wr_clk_main_125m_p_i, 
+      wr_clk_main_125m_n_i   => wr_clk_main_125m_n_i, 
+      wr_clk_sfp_125m_p_i    => wr_clk_sfp_125m_p_i, 
+      wr_clk_sfp_125m_n_i    => wr_clk_sfp_125m_n_i, 
+      clk_sys_62m5_o         => clk_sys_62m5,
+  
+      plldac_sclk_o   => plldac_sclk_o,
+      plldac_din_o    => plldac_din_o,
+      pll25dac_cs_n_o => pll25dac_cs_n_o,
+      pll20dac_cs_n_o => pll20dac_cs_n_o,
+  
+      sfp_txp_o       => sfp_txp_o,
+      sfp_txn_o       => sfp_txn_o,
+      sfp_rxp_i       => sfp_rxp_i,
+      sfp_rxn_i       => sfp_rxn_i,
+      sfp_det_i       => sfp_det_i,
+      sfp_sda_i       => sfp_sda_in,
+      sfp_sda_o       => sfp_sda_out,
+      sfp_scl_i       => sfp_scl_in,
+      sfp_scl_o       => sfp_scl_out,
+      sfp_tx_disable_o => sfp_tx_disable_o,
+      sfp_los_i        => sfp_los_i,
+  
+      eeprom_sda_i => eeprom_sda_in, 
+      eeprom_sda_o => eeprom_sda_out, 
+      eeprom_scl_i => eeprom_scl_in, 
+      eeprom_scl_o => eeprom_scl_out, 
+      uart_rxd_i   => uart_rxd_i, 
+      uart_txd_o   => uart_txd_o, 
+  
+      led_act_o  => user_led_o(0),
+      led_link_o => user_led_o(1),
+      pps_p_o    => pps_p_o);
+
+
+  sfp_scl_b <= '0' when sfp_scl_out = '0' else 'Z';
+  sfp_sda_b <= '0' when sfp_sda_out = '0' else 'Z';
+  sfp_scl_in <= sfp_scl_b;
+  sfp_sda_in <= sfp_sda_b;
+
+  eeprom_scl_b <= '0' when eeprom_scl_out = '0' else 'Z';
+  eeprom_sda_b <= '0' when eeprom_sda_out = '0' else 'Z';
+  eeprom_scl_in <= eeprom_scl_b;
+  eeprom_sda_in <= eeprom_sda_b;
+
+end top;