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White Rabbit core collection
Commits
cb5f3337
Commit
cb5f3337
authored
Aug 22, 2013
by
Wesley W. Terpstra
Browse files
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Plain Diff
arria5: add plls and fixup phy
parent
74caf3bc
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Showing
32 changed files
with
746 additions
and
798 deletions
+746
-798
Manifest.py
platform/altera/Manifest.py
+3
-7
altera_pkg.vhd
platform/altera/altera_pkg.vhd
+51
-25
.gitignore
platform/altera/arria2_pll/.gitignore
+12
-0
Manifest.py
platform/altera/arria2_pll/Manifest.py
+3
-0
arria2_pll.qip
platform/altera/arria2_pll/arria2_pll.qip
+3
-0
arria2_pll.tcl
platform/altera/arria2_pll/arria2_pll.tcl
+15
-0
dmtd_pll.txt
platform/altera/arria2_pll/dmtd_pll.txt
+0
-202
ref_pll.txt
platform/altera/arria2_pll/ref_pll.txt
+0
-202
sys_pll.txt
platform/altera/arria2_pll/sys_pll.txt
+0
-226
.gitignore
platform/altera/arria5_pll/.gitignore
+30
-0
Manifest.py
platform/altera/arria5_pll/Manifest.py
+3
-0
arria5_pll.qip
platform/altera/arria5_pll/arria5_pll.qip
+4
-0
arria5_pll.tcl
platform/altera/arria5_pll/arria5_pll.tcl
+15
-0
dmtd_pll5.txt
platform/altera/arria5_pll/dmtd_pll5.txt
+182
-0
dual_region5.txt
platform/altera/arria5_pll/dual_region5.txt
+30
-0
ref_pll5.txt
platform/altera/arria5_pll/ref_pll5.txt
+182
-0
sys_pll5.txt
platform/altera/arria5_pll/sys_pll5.txt
+182
-0
Manifest.py
platform/altera/dmtd_pll/Manifest.py
+0
-1
dmtd_pll.cmp
platform/altera/dmtd_pll/dmtd_pll.cmp
+0
-23
dmtd_pll.ppf
platform/altera/dmtd_pll/dmtd_pll.ppf
+0
-10
dmtd_pll.qip
platform/altera/dmtd_pll/dmtd_pll.qip
+0
-5
Manifest.py
platform/altera/ref_pll/Manifest.py
+0
-1
ref_pll.cmp
platform/altera/ref_pll/ref_pll.cmp
+0
-23
ref_pll.ppf
platform/altera/ref_pll/ref_pll.ppf
+0
-10
ref_pll.qip
platform/altera/ref_pll/ref_pll.qip
+0
-5
Manifest.py
platform/altera/sys_pll/Manifest.py
+0
-1
sys_pll.cmp
platform/altera/sys_pll/sys_pll.cmp
+0
-25
sys_pll.ppf
platform/altera/sys_pll/sys_pll.ppf
+0
-12
sys_pll.qip
platform/altera/sys_pll/sys_pll.qip
+0
-5
arria5_phy.txt
platform/altera/wr_arria5_phy/arria5_phy.txt
+3
-2
arria5_rxclkout.txt
platform/altera/wr_arria5_phy/arria5_rxclkout.txt
+3
-3
wr_arria5_phy.vhd
platform/altera/wr_arria5_phy/wr_arria5_phy.vhd
+25
-10
No files found.
platform/altera/Manifest.py
View file @
cb5f3337
def
__helper
():
dirs
=
[
"dmtd_pll"
,
"ref_pll"
,
"sys_pll"
,
]
if
syn_device
[:
1
]
==
"5"
:
dirs
.
extend
([
"wr_arria5_phy"
])
if
syn_device
[:
4
]
==
"ep2a"
:
dirs
.
extend
([
"wr_arria2_phy"
])
dirs
=
[]
if
syn_device
[:
1
]
==
"5"
:
dirs
.
extend
([
"wr_arria5_phy"
,
"arria5_pll"
])
if
syn_device
[:
4
]
==
"ep2a"
:
dirs
.
extend
([
"wr_arria2_phy"
,
"arria2_pll"
])
return
dirs
files
=
[
"altera_pkg.vhd"
]
...
...
platform/altera/altera_pkg.vhd
View file @
cb5f3337
...
...
@@ -3,33 +3,60 @@ use ieee.std_logic_1164.all;
package
wr_altera_pkg
is
component
dmtd_pll
port
(
component
dmtd_pll
is
-- arria2
port
(
inclk0
:
in
std_logic
:
=
'0'
;
-- 20 MHz
c0
:
out
std_logic
;
-- 62.5 MHz
locked
:
out
std_logic
);
locked
:
out
std_logic
);
end
component
;
component
ref_pll
port
(
component
dmtd_pll5
is
-- arria5
port
(
refclk
:
in
std_logic
:
=
'X'
;
-- 20 MHz
outclk_0
:
out
std_logic
;
-- 62.5 MHz
rst
:
in
std_logic
:
=
'X'
;
locked
:
out
std_logic
);
end
component
;
component
ref_pll
is
-- arria2
port
(
inclk0
:
in
std_logic
:
=
'0'
;
-- 125 MHz
c0
:
out
std_logic
;
-- 125 MHz
locked
:
out
std_logic
);
locked
:
out
std_logic
);
end
component
;
component
sys_pll
port
(
component
ref_pll5
is
-- arria5
port
(
refclk
:
in
std_logic
:
=
'X'
;
-- 125 MHz
outclk_0
:
out
std_logic
;
-- 125 MHz
rst
:
in
std_logic
:
=
'X'
;
locked
:
out
std_logic
);
end
component
;
component
sys_pll
is
-- arria2
port
(
inclk0
:
in
std_logic
:
=
'0'
;
-- 125 MHz
c0
:
out
std_logic
;
-- 62.5 MHz
c1
:
out
std_logic
;
-- 50 MHz
c2
:
out
std_logic
;
-- 20 MHz
locked
:
out
std_logic
);
locked
:
out
std_logic
);
end
component
;
component
sys_pll5
is
-- arria5
port
(
refclk
:
in
std_logic
:
=
'X'
;
-- 125 MHz
outclk_0
:
out
std_logic
;
-- 62.5 MHz
outclk_1
:
out
std_logic
;
-- 20 MHz
outclk_2
:
out
std_logic
;
-- 100 MHz
outclk_3
:
out
std_logic
;
-- 100 MHz
rst
:
in
std_logic
:
=
'X'
;
locked
:
out
std_logic
);
end
component
;
component
dual_region5
port
(
inclk
:
in
std_logic
;
outclk
:
out
std_logic
);
end
component
;
component
wr_arria2_phy
...
...
@@ -61,11 +88,10 @@ package wr_altera_pkg is
component
wr_arria5_phy
is
generic
(
g_tx_latch_edge
:
std_logic
:
=
'1'
;
g_rx_latch_edge
:
std_logic
:
=
'
0
'
);
g_rx_latch_edge
:
std_logic
:
=
'
1
'
);
port
(
clk_reconf_i
:
in
std_logic
;
clk_pll_i
:
in
std_logic
;
clk_cru_i
:
in
std_logic
;
clk_sys_i
:
in
std_logic
;
rstn_sys_i
:
in
std_logic
;
locked_o
:
out
std_logic
;
...
...
platform/altera/arria2_pll/.gitignore
0 → 100644
View file @
cb5f3337
dmtd_pll.cmp
dmtd_pll.ppf
dmtd_pll.qip
dmtd_pll.vhd
ref_pll.cmp
ref_pll.ppf
ref_pll.qip
ref_pll.vhd
sys_pll.cmp
sys_pll.ppf
sys_pll.qip
sys_pll.vhd
platform/altera/arria2_pll/Manifest.py
0 → 100644
View file @
cb5f3337
files
=
[
"arria2_pll.qip"
]
platform/altera/arria2_pll/arria2_pll.qip
0 → 100644
View file @
cb5f3337
set_global_assignment -name QIP_FILE [file join $::quartus(qip_path) "sys_pll.qip"]
set_global_assignment -name QIP_FILE [file join $::quartus(qip_path) "ref_pll.qip"]
set_global_assignment -name QIP_FILE [file join $::quartus(qip_path) "dmtd_pll.qip"]
platform/altera/arria2_pll/arria2_pll.tcl
0 → 100644
View file @
cb5f3337
set
files
{
sys_pll ref_pll dmtd_pll
}
set
dir
[
file
dirname
[
info
script
]]
post_message
"Testing for megawizard regeneration in
$dir:$files
"
foreach
i
$files
{
if
{
!
[
file
exists
"
$dir
/
$i.qip
"
]
||
[
file
mtime
"
$dir
/
$i.txt
"
]
>
[
file
mtime
"
$dir
/
$i.qip
"
]}
{
post_message
"Regenerating
$i
using qmegawiz"
file copy -force
"
$dir
/
$i.txt
"
"
$dir
/
$i.vhd
"
set sf
[
open
"| qmegawiz -silent
$dir
/
$i.vhd
"
"r"
]
while
{[
gets
$sf
line
]
>= 0
}
{
post_message
"
$line
"
}
close
$sf
file mtime
"
$dir
/
$i.qip
"
[
file
mtime
"
$dir
/
$i.vhd
"
]
}
}
platform/altera/
dmtd_pll/dmtd_pll.vhd
→
platform/altera/
arria2_pll/dmtd_pll.txt
View file @
cb5f3337
...
...
@@ -3,208 +3,6 @@
-- VERSION: WM1.0
-- MODULE: altpll
-- ============================================================
-- File Name: dmtd_pll.vhd
-- Megafunction Name(s):
-- altpll
--
-- Simulation Library Files(s):
-- altera_mf
-- ============================================================
-- ************************************************************
-- THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
--
-- 11.1 Build 216 11/23/2011 SP 1 SJ Full Version
-- ************************************************************
--Copyright (C) 1991-2011 Altera Corporation
--Your use of Altera Corporation's design tools, logic functions
--and other software and tools, and its AMPP partner logic
--functions, and any output files from any of the foregoing
--(including device programming or simulation files), and any
--associated documentation or information are expressly subject
--to the terms and conditions of the Altera Program License
--Subscription Agreement, Altera MegaCore Function License
--Agreement, or other applicable license agreement, including,
--without limitation, that your use is for the sole purpose of
--programming logic devices manufactured by Altera and sold by
--Altera or its authorized distributors. Please refer to the
--applicable agreement for further details.
LIBRARY
ieee
;
USE
ieee
.
std_logic_1164
.
all
;
LIBRARY
altera_mf
;
USE
altera_mf
.
all
;
ENTITY
dmtd_pll
IS
PORT
(
inclk0
:
IN
STD_LOGIC
:
=
'0'
;
c0
:
OUT
STD_LOGIC
;
locked
:
OUT
STD_LOGIC
);
END
dmtd_pll
;
ARCHITECTURE
SYN
OF
dmtd_pll
IS
SIGNAL
sub_wire0
:
STD_LOGIC_VECTOR
(
6
DOWNTO
0
);
SIGNAL
sub_wire1
:
STD_LOGIC
;
SIGNAL
sub_wire2
:
STD_LOGIC
;
SIGNAL
sub_wire3
:
STD_LOGIC
;
SIGNAL
sub_wire4
:
STD_LOGIC_VECTOR
(
1
DOWNTO
0
);
SIGNAL
sub_wire5_bv
:
BIT_VECTOR
(
0
DOWNTO
0
);
SIGNAL
sub_wire5
:
STD_LOGIC_VECTOR
(
0
DOWNTO
0
);
COMPONENT
altpll
GENERIC
(
bandwidth_type
:
STRING
;
clk0_divide_by
:
NATURAL
;
clk0_duty_cycle
:
NATURAL
;
clk0_multiply_by
:
NATURAL
;
clk0_phase_shift
:
STRING
;
inclk0_input_frequency
:
NATURAL
;
intended_device_family
:
STRING
;
lpm_hint
:
STRING
;
lpm_type
:
STRING
;
operation_mode
:
STRING
;
pll_type
:
STRING
;
port_activeclock
:
STRING
;
port_areset
:
STRING
;
port_clkbad0
:
STRING
;
port_clkbad1
:
STRING
;
port_clkloss
:
STRING
;
port_clkswitch
:
STRING
;
port_configupdate
:
STRING
;
port_fbin
:
STRING
;
port_fbout
:
STRING
;
port_inclk0
:
STRING
;
port_inclk1
:
STRING
;
port_locked
:
STRING
;
port_pfdena
:
STRING
;
port_phasecounterselect
:
STRING
;
port_phasedone
:
STRING
;
port_phasestep
:
STRING
;
port_phaseupdown
:
STRING
;
port_pllena
:
STRING
;
port_scanaclr
:
STRING
;
port_scanclk
:
STRING
;
port_scanclkena
:
STRING
;
port_scandata
:
STRING
;
port_scandataout
:
STRING
;
port_scandone
:
STRING
;
port_scanread
:
STRING
;
port_scanwrite
:
STRING
;
port_clk0
:
STRING
;
port_clk1
:
STRING
;
port_clk2
:
STRING
;
port_clk3
:
STRING
;
port_clk4
:
STRING
;
port_clk5
:
STRING
;
port_clk6
:
STRING
;
port_clk7
:
STRING
;
port_clk8
:
STRING
;
port_clk9
:
STRING
;
port_clkena0
:
STRING
;
port_clkena1
:
STRING
;
port_clkena2
:
STRING
;
port_clkena3
:
STRING
;
port_clkena4
:
STRING
;
port_clkena5
:
STRING
;
self_reset_on_loss_lock
:
STRING
;
using_fbmimicbidir_port
:
STRING
;
width_clock
:
NATURAL
);
PORT
(
clk
:
OUT
STD_LOGIC_VECTOR
(
6
DOWNTO
0
);
inclk
:
IN
STD_LOGIC_VECTOR
(
1
DOWNTO
0
);
locked
:
OUT
STD_LOGIC
);
END
COMPONENT
;
BEGIN
sub_wire5_bv
(
0
DOWNTO
0
)
<=
"0"
;
sub_wire5
<=
To_stdlogicvector
(
sub_wire5_bv
);
sub_wire1
<=
sub_wire0
(
0
);
c0
<=
sub_wire1
;
locked
<=
sub_wire2
;
sub_wire3
<=
inclk0
;
sub_wire4
<=
sub_wire5
(
0
DOWNTO
0
)
&
sub_wire3
;
altpll_component
:
altpll
GENERIC
MAP
(
bandwidth_type
=>
"LOW"
,
clk0_divide_by
=>
8
,
clk0_duty_cycle
=>
50
,
clk0_multiply_by
=>
25
,
clk0_phase_shift
=>
"0"
,
inclk0_input_frequency
=>
50000
,
intended_device_family
=>
"Arria II GX"
,
lpm_hint
=>
"CBX_MODULE_PREFIX=dmtd_pll"
,
lpm_type
=>
"altpll"
,
operation_mode
=>
"NO_COMPENSATION"
,
pll_type
=>
"Left_Right"
,
port_activeclock
=>
"PORT_UNUSED"
,
port_areset
=>
"PORT_UNUSED"
,
port_clkbad0
=>
"PORT_UNUSED"
,
port_clkbad1
=>
"PORT_UNUSED"
,
port_clkloss
=>
"PORT_UNUSED"
,
port_clkswitch
=>
"PORT_UNUSED"
,
port_configupdate
=>
"PORT_UNUSED"
,
port_fbin
=>
"PORT_UNUSED"
,
port_fbout
=>
"PORT_UNUSED"
,
port_inclk0
=>
"PORT_USED"
,
port_inclk1
=>
"PORT_UNUSED"
,
port_locked
=>
"PORT_USED"
,
port_pfdena
=>
"PORT_UNUSED"
,
port_phasecounterselect
=>
"PORT_UNUSED"
,
port_phasedone
=>
"PORT_UNUSED"
,
port_phasestep
=>
"PORT_UNUSED"
,
port_phaseupdown
=>
"PORT_UNUSED"
,
port_pllena
=>
"PORT_UNUSED"
,
port_scanaclr
=>
"PORT_UNUSED"
,
port_scanclk
=>
"PORT_UNUSED"
,
port_scanclkena
=>
"PORT_UNUSED"
,
port_scandata
=>
"PORT_UNUSED"
,
port_scandataout
=>
"PORT_UNUSED"
,
port_scandone
=>
"PORT_UNUSED"
,
port_scanread
=>
"PORT_UNUSED"
,
port_scanwrite
=>
"PORT_UNUSED"
,
port_clk0
=>
"PORT_USED"
,
port_clk1
=>
"PORT_UNUSED"
,
port_clk2
=>
"PORT_UNUSED"
,
port_clk3
=>
"PORT_UNUSED"
,
port_clk4
=>
"PORT_UNUSED"
,
port_clk5
=>
"PORT_UNUSED"
,
port_clk6
=>
"PORT_UNUSED"
,
port_clk7
=>
"PORT_UNUSED"
,
port_clk8
=>
"PORT_UNUSED"
,
port_clk9
=>
"PORT_UNUSED"
,
port_clkena0
=>
"PORT_UNUSED"
,
port_clkena1
=>
"PORT_UNUSED"
,
port_clkena2
=>
"PORT_UNUSED"
,
port_clkena3
=>
"PORT_UNUSED"
,
port_clkena4
=>
"PORT_UNUSED"
,
port_clkena5
=>
"PORT_UNUSED"
,
self_reset_on_loss_lock
=>
"OFF"
,
using_fbmimicbidir_port
=>
"OFF"
,
width_clock
=>
7
)
PORT
MAP
(
inclk
=>
sub_wire4
,
clk
=>
sub_wire0
,
locked
=>
sub_wire2
);
END
SYN
;
-- ============================================================
-- CNX file retrieval info
-- ============================================================
...
...
platform/altera/
ref_pll/ref_pll.vhd
→
platform/altera/
arria2_pll/ref_pll.txt
View file @
cb5f3337
...
...
@@ -3,208 +3,6 @@
-- VERSION: WM1.0
-- MODULE: altpll
-- ============================================================
-- File Name: ref_pll.vhd
-- Megafunction Name(s):
-- altpll
--
-- Simulation Library Files(s):
-- altera_mf
-- ============================================================
-- ************************************************************
-- THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
--
-- 11.1 Build 216 11/23/2011 SP 1 SJ Full Version
-- ************************************************************
--Copyright (C) 1991-2011 Altera Corporation
--Your use of Altera Corporation's design tools, logic functions
--and other software and tools, and its AMPP partner logic
--functions, and any output files from any of the foregoing
--(including device programming or simulation files), and any
--associated documentation or information are expressly subject
--to the terms and conditions of the Altera Program License
--Subscription Agreement, Altera MegaCore Function License
--Agreement, or other applicable license agreement, including,
--without limitation, that your use is for the sole purpose of
--programming logic devices manufactured by Altera and sold by
--Altera or its authorized distributors. Please refer to the
--applicable agreement for further details.
LIBRARY
ieee
;
USE
ieee
.
std_logic_1164
.
all
;
LIBRARY
altera_mf
;
USE
altera_mf
.
all
;
ENTITY
ref_pll
IS
PORT
(
inclk0
:
IN
STD_LOGIC
:
=
'0'
;
c0
:
OUT
STD_LOGIC
;
locked
:
OUT
STD_LOGIC
);
END
ref_pll
;
ARCHITECTURE
SYN
OF
ref_pll
IS
SIGNAL
sub_wire0
:
STD_LOGIC_VECTOR
(
6
DOWNTO
0
);
SIGNAL
sub_wire1
:
STD_LOGIC
;
SIGNAL
sub_wire2
:
STD_LOGIC
;
SIGNAL
sub_wire3
:
STD_LOGIC
;
SIGNAL
sub_wire4
:
STD_LOGIC_VECTOR
(
1
DOWNTO
0
);
SIGNAL
sub_wire5_bv
:
BIT_VECTOR
(
0
DOWNTO
0
);
SIGNAL
sub_wire5
:
STD_LOGIC_VECTOR
(
0
DOWNTO
0
);
COMPONENT
altpll
GENERIC
(
bandwidth_type
:
STRING
;
clk0_divide_by
:
NATURAL
;
clk0_duty_cycle
:
NATURAL
;
clk0_multiply_by
:
NATURAL
;
clk0_phase_shift
:
STRING
;
inclk0_input_frequency
:
NATURAL
;
intended_device_family
:
STRING
;
lpm_hint
:
STRING
;
lpm_type
:
STRING
;
operation_mode
:
STRING
;
pll_type
:
STRING
;
port_activeclock
:
STRING
;
port_areset
:
STRING
;
port_clkbad0
:
STRING
;
port_clkbad1
:
STRING
;
port_clkloss
:
STRING
;
port_clkswitch
:
STRING
;
port_configupdate
:
STRING
;
port_fbin
:
STRING
;
port_fbout
:
STRING
;
port_inclk0
:
STRING
;
port_inclk1
:
STRING
;
port_locked
:
STRING
;
port_pfdena
:
STRING
;
port_phasecounterselect
:
STRING
;
port_phasedone
:
STRING
;
port_phasestep
:
STRING
;
port_phaseupdown
:
STRING
;
port_pllena
:
STRING
;
port_scanaclr
:
STRING
;
port_scanclk
:
STRING
;
port_scanclkena
:
STRING
;
port_scandata
:
STRING
;
port_scandataout
:
STRING
;
port_scandone
:
STRING
;
port_scanread
:
STRING
;
port_scanwrite
:
STRING
;
port_clk0
:
STRING
;
port_clk1
:
STRING
;
port_clk2
:
STRING
;
port_clk3
:
STRING
;
port_clk4
:
STRING
;
port_clk5
:
STRING
;
port_clk6
:
STRING
;
port_clk7
:
STRING
;
port_clk8
:
STRING
;
port_clk9
:
STRING
;
port_clkena0
:
STRING
;
port_clkena1
:
STRING
;
port_clkena2
:
STRING
;
port_clkena3
:
STRING
;
port_clkena4
:
STRING
;
port_clkena5
:
STRING
;
self_reset_on_loss_lock
:
STRING
;
using_fbmimicbidir_port
:
STRING
;
width_clock
:
NATURAL
);
PORT
(
clk
:
OUT
STD_LOGIC_VECTOR
(
6
DOWNTO
0
);
inclk
:
IN
STD_LOGIC_VECTOR
(
1
DOWNTO
0
);
locked
:
OUT
STD_LOGIC
);
END
COMPONENT
;
BEGIN
sub_wire5_bv
(
0
DOWNTO
0
)
<=
"0"
;
sub_wire5
<=
To_stdlogicvector
(
sub_wire5_bv
);
sub_wire1
<=
sub_wire0
(
0
);
c0
<=
sub_wire1
;
locked
<=
sub_wire2
;
sub_wire3
<=
inclk0
;
sub_wire4
<=
sub_wire5
(
0
DOWNTO
0
)
&
sub_wire3
;
altpll_component
:
altpll
GENERIC
MAP
(
bandwidth_type
=>
"LOW"
,
clk0_divide_by
=>
1
,
clk0_duty_cycle
=>
50
,
clk0_multiply_by
=>
1
,
clk0_phase_shift
=>
"0"
,
inclk0_input_frequency
=>
8000
,
intended_device_family
=>
"Arria II GX"
,
lpm_hint
=>
"CBX_MODULE_PREFIX=ref_pll"
,
lpm_type
=>
"altpll"
,
operation_mode
=>
"NO_COMPENSATION"
,
pll_type
=>
"Left_Right"
,
port_activeclock
=>
"PORT_UNUSED"
,
port_areset
=>
"PORT_UNUSED"
,
port_clkbad0
=>
"PORT_UNUSED"
,
port_clkbad1
=>
"PORT_UNUSED"
,
port_clkloss
=>
"PORT_UNUSED"
,
port_clkswitch
=>
"PORT_UNUSED"
,
port_configupdate
=>
"PORT_UNUSED"
,
port_fbin
=>
"PORT_UNUSED"
,
port_fbout
=>
"PORT_UNUSED"
,
port_inclk0
=>
"PORT_USED"
,
port_inclk1
=>
"PORT_UNUSED"
,
port_locked
=>
"PORT_USED"
,
port_pfdena
=>
"PORT_UNUSED"
,
port_phasecounterselect
=>
"PORT_UNUSED"
,
port_phasedone
=>
"PORT_UNUSED"
,
port_phasestep
=>
"PORT_UNUSED"
,
port_phaseupdown
=>
"PORT_UNUSED"
,
port_pllena
=>
"PORT_UNUSED"
,
port_scanaclr
=>
"PORT_UNUSED"
,
port_scanclk
=>
"PORT_UNUSED"
,
port_scanclkena
=>
"PORT_UNUSED"
,
port_scandata
=>
"PORT_UNUSED"
,
port_scandataout
=>
"PORT_UNUSED"
,
port_scandone
=>
"PORT_UNUSED"
,
port_scanread
=>
"PORT_UNUSED"
,
port_scanwrite
=>
"PORT_UNUSED"
,
port_clk0
=>
"PORT_USED"
,
port_clk1
=>
"PORT_UNUSED"
,
port_clk2
=>
"PORT_UNUSED"
,
port_clk3
=>
"PORT_UNUSED"
,
port_clk4
=>
"PORT_UNUSED"
,
port_clk5
=>
"PORT_UNUSED"
,
port_clk6
=>
"PORT_UNUSED"
,
port_clk7
=>
"PORT_UNUSED"
,
port_clk8
=>
"PORT_UNUSED"
,
port_clk9
=>
"PORT_UNUSED"
,
port_clkena0
=>
"PORT_UNUSED"
,
port_clkena1
=>
"PORT_UNUSED"
,
port_clkena2
=>
"PORT_UNUSED"
,
port_clkena3
=>
"PORT_UNUSED"
,
port_clkena4
=>
"PORT_UNUSED"
,
port_clkena5
=>
"PORT_UNUSED"
,
self_reset_on_loss_lock
=>
"OFF"
,
using_fbmimicbidir_port
=>
"OFF"
,
width_clock
=>
7
)
PORT
MAP
(
inclk
=>
sub_wire4
,
clk
=>
sub_wire0
,
locked
=>
sub_wire2
);
END
SYN
;
-- ============================================================
-- CNX file retrieval info
-- ============================================================
...
...
platform/altera/
sys_pll/sys_pll.vhd
→
platform/altera/
arria2_pll/sys_pll.txt
View file @
cb5f3337
...
...
@@ -3,232 +3,6 @@
-- VERSION: WM1.0
-- MODULE: altpll
-- ============================================================
-- File Name: sys_pll.vhd
-- Megafunction Name(s):
-- altpll
--
-- Simulation Library Files(s):
-- altera_mf
-- ============================================================
-- ************************************************************
-- THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
--
-- 12.1 Build 243 01/31/2013 SP 1 SJ Full Version
-- ************************************************************
--Copyright (C) 1991-2012 Altera Corporation
--Your use of Altera Corporation's design tools, logic functions
--and other software and tools, and its AMPP partner logic
--functions, and any output files from any of the foregoing
--(including device programming or simulation files), and any
--associated documentation or information are expressly subject
--to the terms and conditions of the Altera Program License
--Subscription Agreement, Altera MegaCore Function License
--Agreement, or other applicable license agreement, including,
--without limitation, that your use is for the sole purpose of
--programming logic devices manufactured by Altera and sold by
--Altera or its authorized distributors. Please refer to the
--applicable agreement for further details.
LIBRARY
ieee
;
USE
ieee
.
std_logic_1164
.
all
;
LIBRARY
altera_mf
;
USE
altera_mf
.
all
;
ENTITY
sys_pll
IS
PORT
(
inclk0
:
IN
STD_LOGIC
:
=
'0'
;
c0
:
OUT
STD_LOGIC
;
c1
:
OUT
STD_LOGIC
;
c2
:
OUT
STD_LOGIC
;
locked
:
OUT
STD_LOGIC
);
END
sys_pll
;
ARCHITECTURE
SYN
OF
sys_pll
IS
SIGNAL
sub_wire0
:
STD_LOGIC_VECTOR
(
6
DOWNTO
0
);
SIGNAL
sub_wire1
:
STD_LOGIC
;
SIGNAL
sub_wire2
:
STD_LOGIC
;
SIGNAL
sub_wire3
:
STD_LOGIC
;
SIGNAL
sub_wire4
:
STD_LOGIC
;
SIGNAL
sub_wire5
:
STD_LOGIC
;
SIGNAL
sub_wire6
:
STD_LOGIC_VECTOR
(
1
DOWNTO
0
);
SIGNAL
sub_wire7_bv
:
BIT_VECTOR
(
0
DOWNTO
0
);
SIGNAL
sub_wire7
:
STD_LOGIC_VECTOR
(
0
DOWNTO
0
);
COMPONENT
altpll
GENERIC
(
bandwidth_type
:
STRING
;
clk0_divide_by
:
NATURAL
;
clk0_duty_cycle
:
NATURAL
;
clk0_multiply_by
:
NATURAL
;
clk0_phase_shift
:
STRING
;
clk1_divide_by
:
NATURAL
;
clk1_duty_cycle
:
NATURAL
;
clk1_multiply_by
:
NATURAL
;
clk1_phase_shift
:
STRING
;
clk2_divide_by
:
NATURAL
;
clk2_duty_cycle
:
NATURAL
;
clk2_multiply_by
:
NATURAL
;
clk2_phase_shift
:
STRING
;
inclk0_input_frequency
:
NATURAL
;
intended_device_family
:
STRING
;
lpm_hint
:
STRING
;
lpm_type
:
STRING
;
operation_mode
:
STRING
;
pll_type
:
STRING
;
port_activeclock
:
STRING
;
port_areset
:
STRING
;
port_clkbad0
:
STRING
;
port_clkbad1
:
STRING
;
port_clkloss
:
STRING
;
port_clkswitch
:
STRING
;
port_configupdate
:
STRING
;
port_fbin
:
STRING
;
port_fbout
:
STRING
;
port_inclk0
:
STRING
;
port_inclk1
:
STRING
;
port_locked
:
STRING
;
port_pfdena
:
STRING
;
port_phasecounterselect
:
STRING
;
port_phasedone
:
STRING
;
port_phasestep
:
STRING
;
port_phaseupdown
:
STRING
;
port_pllena
:
STRING
;
port_scanaclr
:
STRING
;
port_scanclk
:
STRING
;
port_scanclkena
:
STRING
;
port_scandata
:
STRING
;
port_scandataout
:
STRING
;
port_scandone
:
STRING
;
port_scanread
:
STRING
;
port_scanwrite
:
STRING
;
port_clk0
:
STRING
;
port_clk1
:
STRING
;
port_clk2
:
STRING
;
port_clk3
:
STRING
;
port_clk4
:
STRING
;
port_clk5
:
STRING
;
port_clk6
:
STRING
;
port_clk7
:
STRING
;
port_clk8
:
STRING
;
port_clk9
:
STRING
;
port_clkena0
:
STRING
;
port_clkena1
:
STRING
;
port_clkena2
:
STRING
;
port_clkena3
:
STRING
;
port_clkena4
:
STRING
;
port_clkena5
:
STRING
;
self_reset_on_loss_lock
:
STRING
;
using_fbmimicbidir_port
:
STRING
;
width_clock
:
NATURAL
);
PORT
(
clk
:
OUT
STD_LOGIC_VECTOR
(
6
DOWNTO
0
);
inclk
:
IN
STD_LOGIC_VECTOR
(
1
DOWNTO
0
);
locked
:
OUT
STD_LOGIC
);
END
COMPONENT
;
BEGIN
sub_wire7_bv
(
0
DOWNTO
0
)
<=
"0"
;
sub_wire7
<=
To_stdlogicvector
(
sub_wire7_bv
);
sub_wire4
<=
sub_wire0
(
2
);
sub_wire3
<=
sub_wire0
(
0
);
sub_wire1
<=
sub_wire0
(
1
);
c1
<=
sub_wire1
;
locked
<=
sub_wire2
;
c0
<=
sub_wire3
;
c2
<=
sub_wire4
;
sub_wire5
<=
inclk0
;
sub_wire6
<=
sub_wire7
(
0
DOWNTO
0
)
&
sub_wire5
;
altpll_component
:
altpll
GENERIC
MAP
(
bandwidth_type
=>
"LOW"
,
clk0_divide_by
=>
2
,
clk0_duty_cycle
=>
50
,
clk0_multiply_by
=>
1
,
clk0_phase_shift
=>
"0"
,
clk1_divide_by
=>
5
,
clk1_duty_cycle
=>
50
,
clk1_multiply_by
=>
2
,
clk1_phase_shift
=>
"0"
,
clk2_divide_by
=>
25
,
clk2_duty_cycle
=>
50
,
clk2_multiply_by
=>
4
,
clk2_phase_shift
=>
"0"
,
inclk0_input_frequency
=>
8000
,
intended_device_family
=>
"Arria II GX"
,
lpm_hint
=>
"CBX_MODULE_PREFIX=sys_pll"
,
lpm_type
=>
"altpll"
,
operation_mode
=>
"NO_COMPENSATION"
,
pll_type
=>
"Left_Right"
,
port_activeclock
=>
"PORT_UNUSED"
,
port_areset
=>
"PORT_UNUSED"
,
port_clkbad0
=>
"PORT_UNUSED"
,
port_clkbad1
=>
"PORT_UNUSED"
,
port_clkloss
=>
"PORT_UNUSED"
,
port_clkswitch
=>
"PORT_UNUSED"
,
port_configupdate
=>
"PORT_UNUSED"
,
port_fbin
=>
"PORT_UNUSED"
,
port_fbout
=>
"PORT_UNUSED"
,
port_inclk0
=>
"PORT_USED"
,
port_inclk1
=>
"PORT_UNUSED"
,
port_locked
=>
"PORT_USED"
,
port_pfdena
=>
"PORT_UNUSED"
,
port_phasecounterselect
=>
"PORT_UNUSED"
,
port_phasedone
=>
"PORT_UNUSED"
,
port_phasestep
=>
"PORT_UNUSED"
,
port_phaseupdown
=>
"PORT_UNUSED"
,
port_pllena
=>
"PORT_UNUSED"
,
port_scanaclr
=>
"PORT_UNUSED"
,
port_scanclk
=>
"PORT_UNUSED"
,
port_scanclkena
=>
"PORT_UNUSED"
,
port_scandata
=>
"PORT_UNUSED"
,
port_scandataout
=>
"PORT_UNUSED"
,
port_scandone
=>
"PORT_UNUSED"
,
port_scanread
=>
"PORT_UNUSED"
,
port_scanwrite
=>
"PORT_UNUSED"
,
port_clk0
=>
"PORT_USED"
,
port_clk1
=>
"PORT_USED"
,
port_clk2
=>
"PORT_USED"
,
port_clk3
=>
"PORT_UNUSED"
,
port_clk4
=>
"PORT_UNUSED"
,
port_clk5
=>
"PORT_UNUSED"
,
port_clk6
=>
"PORT_UNUSED"
,
port_clk7
=>
"PORT_UNUSED"
,
port_clk8
=>
"PORT_UNUSED"
,
port_clk9
=>
"PORT_UNUSED"
,
port_clkena0
=>
"PORT_UNUSED"
,
port_clkena1
=>
"PORT_UNUSED"
,
port_clkena2
=>
"PORT_UNUSED"
,
port_clkena3
=>
"PORT_UNUSED"
,
port_clkena4
=>
"PORT_UNUSED"
,
port_clkena5
=>
"PORT_UNUSED"
,
self_reset_on_loss_lock
=>
"OFF"
,
using_fbmimicbidir_port
=>
"OFF"
,
width_clock
=>
7
)
PORT
MAP
(
inclk
=>
sub_wire6
,
clk
=>
sub_wire0
,
locked
=>
sub_wire2
);
END
SYN
;
-- ============================================================
-- CNX file retrieval info
-- ============================================================
...
...
platform/altera/arria5_pll/.gitignore
0 → 100644
View file @
cb5f3337
dmtd_pll5.bsf
dmtd_pll5.cmp
dmtd_pll5.ppf
dmtd_pll5.qip
dmtd_pll5.sip
dmtd_pll5.spd
dmtd_pll5.vhd
dmtd_pll5/
dmtd_pll5_sim/
ref_pll5.bsf
ref_pll5.cmp
ref_pll5.ppf
ref_pll5.qip
ref_pll5.sip
ref_pll5.spd
ref_pll5.vhd
ref_pll5/
ref_pll5_sim/
sys_pll5.bsf
sys_pll5.cmp
sys_pll5.ppf
sys_pll5.qip
sys_pll5.sip
sys_pll5.spd
sys_pll5.vhd
sys_pll5/
sys_pll5_sim/
dual_region5.cmp
dual_region5.qip
dual_region5.vhd
platform/altera/arria5_pll/Manifest.py
0 → 100644
View file @
cb5f3337
files
=
[
"arria5_pll.qip"
]
platform/altera/arria5_pll/arria5_pll.qip
0 → 100644
View file @
cb5f3337
set_global_assignment -name QIP_FILE [file join $::quartus(qip_path) "sys_pll5.qip"]
set_global_assignment -name QIP_FILE [file join $::quartus(qip_path) "ref_pll5.qip"]
set_global_assignment -name QIP_FILE [file join $::quartus(qip_path) "dmtd_pll5.qip"]
set_global_assignment -name QIP_FILE [file join $::quartus(qip_path) "dual_region5.qip"]
platform/altera/arria5_pll/arria5_pll.tcl
0 → 100644
View file @
cb5f3337
set
files
{
sys_pll5 ref_pll5 dmtd_pll5 dual_region5
}
set
dir
[
file
dirname
[
info
script
]]
post_message
"Testing for megawizard regeneration in
$dir:$files
"
foreach
i
$files
{
if
{
!
[
file
exists
"
$dir
/
$i.qip
"
]
||
[
file
mtime
"
$dir
/
$i.txt
"
]
>
[
file
mtime
"
$dir
/
$i.qip
"
]}
{
post_message
"Regenerating
$i
using qmegawiz"
file copy -force
"
$dir
/
$i.txt
"
"
$dir
/
$i.vhd
"
set sf
[
open
"| qmegawiz -silent
$dir
/
$i.vhd
"
"r"
]
while
{[
gets
$sf
line
]
>= 0
}
{
post_message
"
$line
"
}
close
$sf
file mtime
"
$dir
/
$i.qip
"
[
file
mtime
"
$dir
/
$i.vhd
"
]
}
}
platform/altera/arria5_pll/dmtd_pll5.txt
0 → 100644
View file @
cb5f3337
This diff is collapsed.
Click to expand it.
platform/altera/arria5_pll/dual_region5.txt
0 → 100644
View file @
cb5f3337
-- megafunction wizard: %ALTCLKCTRL%
-- GENERATION: STANDARD
-- VERSION: WM1.0
-- MODULE: altclkctrl
--altclkctrl CBX_AUTO_BLACKBOX="ALL" CLOCK_TYPE="Dual-Regional Clock" DEVICE_FAMILY="Arria V" ENA_REGISTER_MODE="always enabled" USE_GLITCH_FREE_SWITCH_OVER_IMPLEMENTATION="OFF" ena inclk outclk
--VERSION_BEGIN 13.0 cbx_altclkbuf 2013:06:12:18:03:33:SJ cbx_cycloneii 2013:06:12:18:03:33:SJ cbx_lpm_add_sub 2013:06:12:18:03:33:SJ cbx_lpm_compare 2013:06:12:18:03:33:SJ cbx_lpm_decode 2013:06:12:18:03:33:SJ cbx_lpm_mux 2013:06:12:18:03:33:SJ cbx_mgl 2013:06:12:18:33:59:SJ cbx_stratix 2013:06:12:18:03:33:SJ cbx_stratixii 2013:06:12:18:03:33:SJ cbx_stratixiii 2013:06:12:18:03:33:SJ cbx_stratixv 2013:06:12:18:03:33:SJ VERSION_END
-- ============================================================
-- CNX file retrieval info
-- ============================================================
-- Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Arria V"
-- Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0"
-- Retrieval info: PRIVATE: clock_inputs NUMERIC "1"
-- Retrieval info: CONSTANT: ENA_REGISTER_MODE STRING "always enabled"
-- Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Arria V"
-- Retrieval info: CONSTANT: USE_GLITCH_FREE_SWITCH_OVER_IMPLEMENTATION STRING "OFF"
-- Retrieval info: CONSTANT: clock_type STRING "Dual-Regional Clock"
-- Retrieval info: USED_PORT: inclk 0 0 0 0 INPUT NODEFVAL "inclk"
-- Retrieval info: USED_PORT: outclk 0 0 0 0 OUTPUT NODEFVAL "outclk"
-- Retrieval info: CONNECT: @ena 0 0 0 0 VCC 0 0 0 0
-- Retrieval info: CONNECT: @inclk 0 0 3 1 GND 0 0 3 0
-- Retrieval info: CONNECT: @inclk 0 0 1 0 inclk 0 0 0 0
-- Retrieval info: CONNECT: outclk 0 0 0 0 @outclk 0 0 0 0
-- Retrieval info: GEN_FILE: TYPE_NORMAL dual_region5.vhd TRUE
-- Retrieval info: GEN_FILE: TYPE_NORMAL dual_region5.inc FALSE
-- Retrieval info: GEN_FILE: TYPE_NORMAL dual_region5.cmp TRUE
-- Retrieval info: GEN_FILE: TYPE_NORMAL dual_region5.bsf FALSE
-- Retrieval info: GEN_FILE: TYPE_NORMAL dual_region5_inst.vhd FALSE
-- Retrieval info: LIB_FILE: arriav
platform/altera/arria5_pll/ref_pll5.txt
0 → 100644
View file @
cb5f3337
This diff is collapsed.
Click to expand it.
platform/altera/arria5_pll/sys_pll5.txt
0 → 100644
View file @
cb5f3337
This diff is collapsed.
Click to expand it.
platform/altera/dmtd_pll/Manifest.py
deleted
100644 → 0
View file @
74caf3bc
files
=
[
"dmtd_pll.vhd"
]
platform/altera/dmtd_pll/dmtd_pll.cmp
deleted
100644 → 0
View file @
74caf3bc
--Copyright (C) 1991-2011 Altera Corporation
--Your use of Altera Corporation's design tools, logic functions
--and other software and tools, and its AMPP partner logic
--functions, and any output files from any of the foregoing
--(including device programming or simulation files), and any
--associated documentation or information are expressly subject
--to the terms and conditions of the Altera Program License
--Subscription Agreement, Altera MegaCore Function License
--Agreement, or other applicable license agreement, including,
--without limitation, that your use is for the sole purpose of
--programming logic devices manufactured by Altera and sold by
--Altera or its authorized distributors. Please refer to the
--applicable agreement for further details.
component dmtd_pll
PORT
(
inclk0 : IN STD_LOGIC := '0';
c0 : OUT STD_LOGIC ;
locked : OUT STD_LOGIC
);
end component;
platform/altera/dmtd_pll/dmtd_pll.ppf
deleted
100644 → 0
View file @
74caf3bc
<?xml version="1.0" encoding="UTF-8" ?>
<!DOCTYPE pinplan>
<pinplan
intended_family=
"Arria II GX"
variation_name=
"dmtd_pll"
megafunction_name=
"ALTPLL"
specifies=
"all_ports"
>
<global>
<pin
name=
"inclk0"
direction=
"input"
scope=
"external"
source=
"clock"
/>
<pin
name=
"c0"
direction=
"output"
scope=
"external"
source=
"clock"
/>
<pin
name=
"locked"
direction=
"output"
scope=
"external"
/>
</global>
</pinplan>
platform/altera/dmtd_pll/dmtd_pll.qip
deleted
100644 → 0
View file @
74caf3bc
set_global_assignment -name IP_TOOL_NAME "ALTPLL"
set_global_assignment -name IP_TOOL_VERSION "11.1"
set_global_assignment -name VHDL_FILE [file join $::quartus(qip_path) "dmtd_pll.vhd"]
set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "dmtd_pll.cmp"]
set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "dmtd_pll.ppf"]
platform/altera/ref_pll/Manifest.py
deleted
100644 → 0
View file @
74caf3bc
files
=
[
"ref_pll.vhd"
]
platform/altera/ref_pll/ref_pll.cmp
deleted
100644 → 0
View file @
74caf3bc
--Copyright (C) 1991-2011 Altera Corporation
--Your use of Altera Corporation's design tools, logic functions
--and other software and tools, and its AMPP partner logic
--functions, and any output files from any of the foregoing
--(including device programming or simulation files), and any
--associated documentation or information are expressly subject
--to the terms and conditions of the Altera Program License
--Subscription Agreement, Altera MegaCore Function License
--Agreement, or other applicable license agreement, including,
--without limitation, that your use is for the sole purpose of
--programming logic devices manufactured by Altera and sold by
--Altera or its authorized distributors. Please refer to the
--applicable agreement for further details.
component ref_pll
PORT
(
inclk0 : IN STD_LOGIC := '0';
c0 : OUT STD_LOGIC ;
locked : OUT STD_LOGIC
);
end component;
platform/altera/ref_pll/ref_pll.ppf
deleted
100644 → 0
View file @
74caf3bc
<?xml version="1.0" encoding="UTF-8" ?>
<!DOCTYPE pinplan>
<pinplan
intended_family=
"Arria II GX"
variation_name=
"ref_pll"
megafunction_name=
"ALTPLL"
specifies=
"all_ports"
>
<global>
<pin
name=
"inclk0"
direction=
"input"
scope=
"external"
source=
"clock"
/>
<pin
name=
"c0"
direction=
"output"
scope=
"external"
source=
"clock"
/>
<pin
name=
"locked"
direction=
"output"
scope=
"external"
/>
</global>
</pinplan>
platform/altera/ref_pll/ref_pll.qip
deleted
100644 → 0
View file @
74caf3bc
set_global_assignment -name IP_TOOL_NAME "ALTPLL"
set_global_assignment -name IP_TOOL_VERSION "11.1"
set_global_assignment -name VHDL_FILE [file join $::quartus(qip_path) "ref_pll.vhd"]
set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "ref_pll.cmp"]
set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "ref_pll.ppf"]
platform/altera/sys_pll/Manifest.py
deleted
100644 → 0
View file @
74caf3bc
files
=
[
"sys_pll.vhd"
]
platform/altera/sys_pll/sys_pll.cmp
deleted
100644 → 0
View file @
74caf3bc
--Copyright (C) 1991-2012 Altera Corporation
--Your use of Altera Corporation's design tools, logic functions
--and other software and tools, and its AMPP partner logic
--functions, and any output files from any of the foregoing
--(including device programming or simulation files), and any
--associated documentation or information are expressly subject
--to the terms and conditions of the Altera Program License
--Subscription Agreement, Altera MegaCore Function License
--Agreement, or other applicable license agreement, including,
--without limitation, that your use is for the sole purpose of
--programming logic devices manufactured by Altera and sold by
--Altera or its authorized distributors. Please refer to the
--applicable agreement for further details.
component sys_pll
PORT
(
inclk0 : IN STD_LOGIC := '0';
c0 : OUT STD_LOGIC ;
c1 : OUT STD_LOGIC ;
c2 : OUT STD_LOGIC ;
locked : OUT STD_LOGIC
);
end component;
platform/altera/sys_pll/sys_pll.ppf
deleted
100644 → 0
View file @
74caf3bc
<?xml version="1.0" encoding="UTF-8" ?>
<!DOCTYPE pinplan>
<pinplan
intended_family=
"Arria II GX"
variation_name=
"sys_pll"
megafunction_name=
"ALTPLL"
specifies=
"all_ports"
>
<global>
<pin
name=
"inclk0"
direction=
"input"
scope=
"external"
source=
"clock"
/>
<pin
name=
"c0"
direction=
"output"
scope=
"external"
source=
"clock"
/>
<pin
name=
"c1"
direction=
"output"
scope=
"external"
source=
"clock"
/>
<pin
name=
"c2"
direction=
"output"
scope=
"external"
source=
"clock"
/>
<pin
name=
"locked"
direction=
"output"
scope=
"external"
/>
</global>
</pinplan>
platform/altera/sys_pll/sys_pll.qip
deleted
100644 → 0
View file @
74caf3bc
set_global_assignment -name IP_TOOL_NAME "ALTPLL"
set_global_assignment -name IP_TOOL_VERSION "12.1"
set_global_assignment -name VHDL_FILE [file join $::quartus(qip_path) "sys_pll.vhd"]
set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "sys_pll.cmp"]
set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "sys_pll.ppf"]
platform/altera/wr_arria5_phy/arria5_phy.txt
View file @
cb5f3337
-- megafunction wizard: %Deterministic Latency PHY v12.1%
-- Retrieval info: <instance entity-name="altera_xcvr_det_latency" version="1
2.1
" >
-- Retrieval info: <instance entity-name="altera_xcvr_det_latency" version="1
3.0
" >
-- Retrieval info: <generic name="device_family" value="Arria V" />
-- Retrieval info: <generic name="operation_mode" value="Duplex" />
-- Retrieval info: <generic name="lanes" value="1" />
...
...
@@ -9,6 +9,7 @@
-- Retrieval info: <generic name="data_rate" value="1.25 Gbps" />
-- Retrieval info: <generic name="gui_base_data_rate" value="1228.8 Mbps" />
-- Retrieval info: <generic name="gui_pll_refclk_freq" value="125.0 MHz" />
-- Retrieval info: <generic name="en_cdrref_support" value="0" />
-- Retrieval info: <generic name="gui_pll_feedback_path" value="true" />
-- Retrieval info: <generic name="use_double_data_mode" value="DEPRECATED" />
-- Retrieval info: <generic name="word_aligner_mode" value="manual" />
...
...
@@ -20,7 +21,7 @@
-- Retrieval info: <generic name="gui_use_status" value="false" />
-- Retrieval info: <generic name="gui_pll_reconfig_enable_pll_reconfig" value="false" />
-- Retrieval info: <generic name="gui_pll_reconfig_pll_count" value="1" />
-- Retrieval info: <generic name="gui_pll_reconfig_refclk_count" value="
2
" />
-- Retrieval info: <generic name="gui_pll_reconfig_refclk_count" value="
1
" />
-- Retrieval info: <generic name="gui_pll_reconfig_main_pll_index" value="0" />
-- Retrieval info: <generic name="gui_pll_reconfig_cdr_pll_refclk_sel" value="1" />
-- Retrieval info: <generic name="gui_pll_reconfig_pll0_pll_type" value="CMU" />
...
...
platform/altera/wr_arria5_phy/arria5_rxclkout.txt
View file @
cb5f3337
...
...
@@ -3,8 +3,8 @@
-- VERSION: WM1.0
-- MODULE: altclkctrl
--altclkctrl CBX_AUTO_BLACKBOX="ALL" CLOCK_TYPE="
Glob
al Clock" DEVICE_FAMILY="Arria V" ENA_REGISTER_MODE="always enabled" USE_GLITCH_FREE_SWITCH_OVER_IMPLEMENTATION="OFF" ena inclk outclk
--VERSION_BEGIN 1
2.1SP1 cbx_altclkbuf 2013:01:31:18:04:54:SJ cbx_cycloneii 2013:01:31:18:04:54:SJ cbx_lpm_add_sub 2013:01:31:18:04:54:SJ cbx_lpm_compare 2013:01:31:18:04:54:SJ cbx_lpm_decode 2013:01:31:18:04:54:SJ cbx_lpm_mux 2013:01:31:18:04:54:SJ cbx_mgl 2013:01:31:19:27:12:SJ cbx_stratix 2013:01:31:18:04:54:SJ cbx_stratixii 2013:01:31:18:04:54:SJ cbx_stratixiii 2013:01:31:18:04:54:SJ cbx_stratixv 2013:01:31:18:04:54
:SJ VERSION_END
--altclkctrl CBX_AUTO_BLACKBOX="ALL" CLOCK_TYPE="
Region
al Clock" DEVICE_FAMILY="Arria V" ENA_REGISTER_MODE="always enabled" USE_GLITCH_FREE_SWITCH_OVER_IMPLEMENTATION="OFF" ena inclk outclk
--VERSION_BEGIN 1
3.0 cbx_altclkbuf 2013:06:12:18:03:33:SJ cbx_cycloneii 2013:06:12:18:03:33:SJ cbx_lpm_add_sub 2013:06:12:18:03:33:SJ cbx_lpm_compare 2013:06:12:18:03:33:SJ cbx_lpm_decode 2013:06:12:18:03:33:SJ cbx_lpm_mux 2013:06:12:18:03:33:SJ cbx_mgl 2013:06:12:18:33:59:SJ cbx_stratix 2013:06:12:18:03:33:SJ cbx_stratixii 2013:06:12:18:03:33:SJ cbx_stratixiii 2013:06:12:18:03:33:SJ cbx_stratixv 2013:06:12:18:03:33
:SJ VERSION_END
-- ============================================================
-- CNX file retrieval info
...
...
@@ -15,7 +15,7 @@
-- Retrieval info: CONSTANT: ENA_REGISTER_MODE STRING "always enabled"
-- Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Arria V"
-- Retrieval info: CONSTANT: USE_GLITCH_FREE_SWITCH_OVER_IMPLEMENTATION STRING "OFF"
-- Retrieval info: CONSTANT: clock_type STRING "
Glob
al Clock"
-- Retrieval info: CONSTANT: clock_type STRING "
Region
al Clock"
-- Retrieval info: USED_PORT: inclk 0 0 0 0 INPUT NODEFVAL "inclk"
-- Retrieval info: USED_PORT: outclk 0 0 0 0 OUTPUT NODEFVAL "outclk"
-- Retrieval info: CONNECT: @ena 0 0 0 0 VCC 0 0 0 0
...
...
platform/altera/wr_arria5_phy/wr_arria5_phy.vhd
View file @
cb5f3337
...
...
@@ -36,6 +36,7 @@
-- Revisions :
-- Date Version Author Description
-- 2013-03-12 1.0 terpstra Rewrote using deterministic mode
-- 2013-08-22 1.1 terpstra Now runs on arria5 hardware
-------------------------------------------------------------------------------
...
...
@@ -50,11 +51,10 @@ use work.disparity_gen_pkg.all;
entity
wr_arria5_phy
is
generic
(
g_tx_latch_edge
:
std_logic
:
=
'1'
;
g_rx_latch_edge
:
std_logic
:
=
'
0
'
);
g_rx_latch_edge
:
std_logic
:
=
'
1
'
);
port
(
clk_reconf_i
:
in
std_logic
;
-- 50 MHz
clk_pll_i
:
in
std_logic
;
-- feeds transmitter PLL
clk_cru_i
:
in
std_logic
;
-- trains data recovery clock
clk_sys_i
:
in
std_logic
;
-- Used to reset the core
rstn_sys_i
:
in
std_logic
;
-- must last >= 1us
locked_o
:
out
std_logic
;
-- Is the rx_rbclk valid? (clk_sys domain)
...
...
@@ -113,7 +113,7 @@ architecture rtl of wr_arria5_phy is
phy_mgmt_writedata
:
in
std_logic_vector
(
31
downto
0
);
tx_ready
:
out
std_logic
;
rx_ready
:
out
std_logic
;
pll_ref_clk
:
in
std_logic_vector
(
1
downto
0
);
pll_ref_clk
:
in
std_logic_vector
(
0
downto
0
);
tx_serial_data
:
out
std_logic_vector
(
0
downto
0
);
tx_bitslipboundaryselect
:
in
std_logic_vector
(
4
downto
0
);
pll_locked
:
out
std_logic_vector
(
0
downto
0
);
...
...
@@ -158,6 +158,8 @@ architecture rtl of wr_arria5_phy is
signal
reconfig_busy
:
std_logic
;
signal
sys_locked
:
std_logic_vector
(
2
downto
0
);
signal
sys_drop_count
:
unsigned
(
9
downto
0
);
signal
sys_drop
:
std_logic
;
signal
tx_8b10b_rstn
:
std_logic_vector
(
2
downto
0
);
-- tx domain
signal
rx_8b10b_rstn
:
std_logic_vector
(
2
downto
0
);
-- rx domain
...
...
@@ -204,12 +206,11 @@ begin
phy_mgmt_read
=>
'0'
,
phy_mgmt_readdata
=>
open
,
phy_mgmt_waitrequest
=>
open
,
phy_mgmt_write
=>
'
1
'
,
phy_mgmt_write
=>
'
0
'
,
phy_mgmt_writedata
=>
(
others
=>
'0'
),
tx_ready
=>
tx_ready
,
rx_ready
=>
rx_ready
,
pll_ref_clk
(
0
)
=>
clk_pll_i
,
pll_ref_clk
(
1
)
=>
clk_cru_i
,
tx_serial_data
(
0
)
=>
pad_txp_o
,
tx_bitslipboundaryselect
=>
(
others
=>
'0'
),
pll_locked
(
0
)
=>
pll_locked
,
...
...
@@ -249,9 +250,23 @@ begin
begin
if
rstn_sys_i
=
'0'
then
sys_locked
<=
(
others
=>
'0'
);
sys_drop_count
<=
(
others
=>
'1'
);
sys_drop
<=
'1'
;
elsif
rising_edge
(
clk_sys_i
)
then
sys_locked
(
sys_locked
'left
)
<=
pll_locked
and
rx_ready
and
tx_ready
and
not
reconfig_busy
;
if
drop_link_i
=
'1'
then
sys_drop_count
<=
(
others
=>
'1'
);
sys_drop
<=
'1'
;
else
sys_drop_count
<=
sys_drop_count
-
1
;
if
sys_drop_count
=
0
then
sys_drop
<=
'0'
;
end
if
;
end
if
;
sys_locked
(
sys_locked
'left
)
<=
pll_locked
and
tx_ready
and
not
reconfig_busy
;
sys_locked
(
sys_locked
'left
-1
downto
0
)
<=
sys_locked
(
sys_locked
'left
downto
1
);
end
if
;
end
process
;
...
...
@@ -259,7 +274,7 @@ begin
p_pll_reset
:
process
(
clk_pll_i
)
is
begin
if
rising_edge
(
clk_pll_i
)
then
tx_8b10b_rstn
<=
(
rstn_sys_i
and
not
tx_ready
)
&
tx_8b10b_rstn
(
tx_8b10b_rstn
'left
downto
1
);
tx_8b10b_rstn
<=
(
not
sys_drop
and
tx_ready
)
&
tx_8b10b_rstn
(
tx_8b10b_rstn
'left
downto
1
);
end
if
;
end
process
;
...
...
@@ -268,7 +283,7 @@ begin
p_rx_reset
:
process
(
clk_rx
)
is
begin
if
rising_edge
(
clk_rx
)
then
rx_8b10b_rstn
<=
(
rstn_sys_i
and
not
rx_ready
)
&
rx_8b10b_rstn
(
rx_8b10b_rstn
'left
downto
1
);
rx_8b10b_rstn
<=
(
not
sys_drop
and
rx_ready
)
&
rx_8b10b_rstn
(
rx_8b10b_rstn
'left
downto
1
);
end
if
;
end
process
;
...
...
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