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White Rabbit core collection
Commit a975b77b authored by Tomasz Wlostowski's avatar Tomasz Wlostowski
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hdl: improved softpll-ng

parent 760bd932
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Showing with 1671 additions and 539 deletions
Manifest.py
View file @ a975b77b
files = ["spll_period_detect.vhd",
"spll_wbgen2_pkg.vhd",
# "wr_softpll_ng.vhd",
# "xwr_softpll_ng.vhd",
"spll_wb_slave.vhd"]
\ No newline at end of file
"spll_wbgen2_pkg.vhd",
"wr_softpll_ng.vhd",
"xwr_softpll_ng.vhd",
"spll_wb_slave.vhd"]
spll_period_detect.vhd
View file @ a975b77b
......@@ -6,7 +6,7 @@
-- Author : Tomasz Wlostowski
-- Company : CERN BE-Co-HT
-- Created : 2010-06-14
-- Last update: 2012-01-17
-- Last update: 2012-01-23
-- Platform : FPGA-generic
-- Standard : VHDL'87
-------------------------------------------------------------------------------
......@@ -70,55 +70,84 @@ end spll_period_detect;
architecture rtl of spll_period_detect is
constant c_COUNTER_BITS : integer := 19;
constant c_GATING_PERIOD : integer := 1024;
constant c_GATING_PERIOD_LOG2 : integer := 17;
-- frequency counters: feedback clock & gating counter
signal in_muxed : std_logic;
signal in_sel_onehot : std_logic_vector(g_num_ref_inputs-1 downto 0);
subtype t_counter is unsigned(c_GATING_PERIOD_LOG2+1 downto 0);
type t_counter_array is array(integer range <>) of t_counter;
signal freq : std_logic_vector(19 downto 0);
signal freq_valid_dmtdclk, freq_valid_sysclk : std_logic;
signal freq_valid_dmtdclk_d0, freq_valid_dmtdclk_pulse : std_logic;
signal freq_valid_sysclk : std_logic;
signal gate_counter : t_counter;
signal gate_pulse_dmtdclk : std_logic;
signal gate_pulse_synced : std_logic_vector(g_num_ref_inputs-1 downto 0);
signal fb_counters, fb_freq : t_counter_array(g_num_ref_inputs-1 downto 0);
signal fb_muxpipe : t_counter_array(2 downto 0);
begin -- rtl
p_gate_counter : process(clk_dmtd_i)
begin
if rising_edge(clk_dmtd_i) then
if rst_n_dmtdclk_i = '0' then
gate_counter <= to_unsigned(1, gate_counter'length);
else
if(gate_counter(c_GATING_PERIOD_LOG2) = '1') then
gate_counter <= to_unsigned(1, gate_counter'length);
else
gate_counter <= gate_counter + 1;
end if;
end if;
end if;
end process;
gen_in_sel_mask : for i in 0 to g_num_ref_inputs-1 generate
in_sel_onehot(i) <= '1' when i = to_integer(unsigned(in_sel_i)) else '0';
end generate gen_in_sel_mask; -- i
gate_pulse_dmtdclk <= gate_counter(c_GATING_PERIOD_LOG2);
in_muxed <= '1' when unsigned(in_sel_onehot and clk_ref_i) /= 0 else '0';
gen_feedback_counters : for i in 0 to g_num_ref_inputs-1 generate
U_Gate_Sync : gc_pulse_synchronizer
port map (
clk_in_i => clk_dmtd_i,
clk_out_i => clk_ref_i(i),
rst_n_i => rst_n_sysclk_i,
d_p_i => gate_pulse_dmtdclk,
q_p_o => gate_pulse_synced(i));
p_feedback_counter : process(clk_ref_i(i))
begin
if rst_n_sysclk_i = '0' then
fb_counters(i) <= to_unsigned(1, c_GATING_PERIOD_LOG2+2);
elsif rising_edge(clk_ref_i(i)) then
if(gate_pulse_synced(i) = '1') then
fb_freq(i) <= fb_counters(i);
fb_counters(i) <= to_unsigned(0, c_GATING_PERIOD_LOG2+2);
else
fb_counters(i) <= fb_counters(i) + 1;
end if;
end if;
end process;
end generate gen_feedback_counters;
U_Freq_Meter : gc_frequency_meter
U_Sync_Gate : gc_sync_ffs
generic map (
g_with_internal_timebase => true,
g_clk_sys_freq => c_GATING_PERIOD,
g_counter_bits => 20)
g_sync_edge => "positive")
port map (
clk_sys_i => clk_dmtd_i,
clk_in_i => in_muxed,
rst_n_i => rst_n_dmtdclk_i,
pps_p1_i => '0',
freq_o => freq,
freq_valid_o => freq_valid_dmtdclk);
U_Pulse_Sync : gc_pulse_synchronizer
port map (
clk_in_i => clk_dmtd_i,
clk_out_i => clk_sys_i,
rst_n_i => rst_n_sysclk_i,
d_p_i => freq_valid_dmtdclk_pulse,
q_p_o => freq_valid_sysclk);
clk_i => clk_sys_i,
rst_n_i => rst_n_sysclk_i,
data_i => std_logic(gate_counter(c_GATING_PERIOD_LOG2-1)),
ppulse_o => freq_valid_sysclk);
p_mux_counters : process(clk_sys_i)
begin
if rising_edge(clk_sys_i) then
fb_muxpipe(0) <= fb_freq(to_integer(unsigned(in_sel_i)));
for i in 1 to fb_muxpipe'length-1 loop
fb_muxpipe(i) <= fb_muxpipe(i-1);
end loop; -- i
end if;
end process;
p_edge_detect: process(clk_dmtd_i)
begin
if rising_edge(clk_dmtd_i) then
freq_valid_dmtdclk_d0 <= freq_valid_dmtdclk;
end if;
end process;
freq_valid_dmtdclk_pulse <= freq_valid_dmtdclk and not freq_valid_dmtdclk_d0;
p_output : process(clk_sys_i)
begin
if rising_edge(clk_sys_i) then
......@@ -126,12 +155,12 @@ begin -- rtl
freq_err_o <= (others => '0');
freq_err_stb_p_o <= '0';
elsif(freq_valid_sysclk = '1') then
freq_err_o <= std_logic_vector(resize(unsigned(freq) - c_GATING_PERIOD, freq_err_o'length));
freq_err_o <= std_logic_vector(resize(fb_muxpipe(fb_muxpipe'length-1) - (2 ** c_GATING_PERIOD_LOG2), freq_err_o'length));
freq_err_stb_p_o <= '1';
else
freq_err_stb_p_o <= '0';
end if;
end if;
end process;
end rtl;
spll_wb_slave.vhd
View file @ a975b77b
......@@ -2,11 +2,11 @@
-- Title : Wishbone slave core for WR Softcore PLL
---------------------------------------------------------------------------------------
-- File : spll_wb_slave.vhd
-- Author : auto-generated by wbgen2 from wr_softpll.wb
-- Created : Wed Jan 18 13:13:08 2012
-- Author : auto-generated by wbgen2 from spll_wb_slave.wb
-- Created : Wed Mar 7 11:09:45 2012
-- Standard : VHDL'87
---------------------------------------------------------------------------------------
-- THIS FILE WAS GENERATED BY wbgen2 FROM SOURCE FILE wr_softpll.wb
-- THIS FILE WAS GENERATED BY wbgen2 FROM SOURCE FILE spll_wb_slave.wb
-- DO NOT HAND-EDIT UNLESS IT'S ABSOLUTELY NECESSARY!
---------------------------------------------------------------------------------------
......@@ -15,34 +15,43 @@ use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use work.wbgen2_pkg.all;
use work.SPLL_wbgen2_pkg.all;
use work.spll_wbgen2_pkg.all;
entity spll_wb_slave is
port (
rst_n_i : in std_logic;
wb_clk_i : in std_logic;
wb_addr_i : in std_logic_vector(3 downto 0);
wb_data_i : in std_logic_vector(31 downto 0);
wb_data_o : out std_logic_vector(31 downto 0);
clk_sys_i : in std_logic;
wb_adr_i : in std_logic_vector(4 downto 0);
wb_dat_i : in std_logic_vector(31 downto 0);
wb_dat_o : out std_logic_vector(31 downto 0);
wb_cyc_i : in std_logic;
wb_sel_i : in std_logic_vector(3 downto 0);
wb_stb_i : in std_logic;
wb_we_i : in std_logic;
wb_ack_o : out std_logic;
wb_irq_o : out std_logic;
wb_stall_o : out std_logic;
wb_int_o : out std_logic;
tag_hpll_rd_period_o : out std_logic;
irq_tag_i : in std_logic;
regs_i : in t_SPLL_in_registers;
regs_o : out t_SPLL_out_registers
regs_i : in t_spll_in_registers;
regs_o : out t_spll_out_registers
);
end spll_wb_slave;
architecture syn of spll_wb_slave is
signal spll_csr_per_sel_int : std_logic_vector(5 downto 0);
signal spll_csr_per_en_int : std_logic ;
signal spll_dccr_gate_div_int : std_logic_vector(5 downto 0);
signal spll_occr_out_lock_int : std_logic_vector(7 downto 0);
signal spll_deglitch_thr_int : std_logic_vector(15 downto 0);
signal spll_dfr_host_rst_n : std_logic ;
signal spll_dfr_host_in_int : std_logic_vector(47 downto 0);
signal spll_dfr_host_out_int : std_logic_vector(47 downto 0);
signal spll_dfr_host_rdreq_int : std_logic ;
signal spll_dfr_host_rdreq_int_d0 : std_logic ;
signal spll_trr_rst_n : std_logic ;
signal spll_trr_in_int : std_logic_vector(31 downto 0);
signal spll_trr_out_int : std_logic_vector(31 downto 0);
signal spll_trr_rdreq_int : std_logic ;
......@@ -56,500 +65,666 @@ signal eic_isr_clear_int : std_logic_vector(0 downto 0);
signal eic_isr_status_int : std_logic_vector(0 downto 0);
signal eic_irq_ack_int : std_logic_vector(0 downto 0);
signal eic_isr_write_int : std_logic ;
signal spll_dfr_host_full_int : std_logic ;
signal spll_dfr_host_empty_int : std_logic ;
signal spll_dfr_host_usedw_int : std_logic_vector(12 downto 0);
signal spll_trr_empty_int : std_logic ;
signal irq_inputs_vector_int : std_logic_vector(0 downto 0);
signal ack_sreg : std_logic_vector(9 downto 0);
signal rddata_reg : std_logic_vector(31 downto 0);
signal wrdata_reg : std_logic_vector(31 downto 0);
signal bwsel_reg : std_logic_vector(3 downto 0);
signal rwaddr_reg : std_logic_vector(3 downto 0);
signal rwaddr_reg : std_logic_vector(4 downto 0);
signal ack_in_progress : std_logic ;
signal wr_int : std_logic ;
signal rd_int : std_logic ;
signal bus_clock_int : std_logic ;
signal allones : std_logic_vector(31 downto 0);
signal allzeros : std_logic_vector(31 downto 0);
begin
-- Some internal signals assignments. For (foreseen) compatibility with other bus standards.
wrdata_reg <= wb_data_i;
wrdata_reg <= wb_dat_i;
bwsel_reg <= wb_sel_i;
bus_clock_int <= wb_clk_i;
rd_int <= wb_cyc_i and (wb_stb_i and (not wb_we_i));
wr_int <= wb_cyc_i and (wb_stb_i and wb_we_i);
allones <= (others => '1');
allzeros <= (others => '0');
--
-- Main register bank access process.
process (bus_clock_int, rst_n_i)
process (clk_sys_i, rst_n_i)
begin
if (rst_n_i = '0') then
ack_sreg <= "0000000000";
ack_in_progress <= '0';
rddata_reg <= "00000000000000000000000000000000";
spll_csr_per_sel_int <= "000000";
spll_csr_per_en_int <= '0';
spll_dccr_gate_div_int <= "000000";
regs_o.rcger_gate_sel_wr_o <= '0';
spll_occr_out_lock_int <= "00000000";
regs_o.spll_rcer_load_o <= '0';
regs_o.spll_ocer_load_o <= '0';
regs_o.rcer_load_o <= '0';
regs_o.ocer_load_o <= '0';
tag_hpll_rd_period_o <= '0';
regs_o.spll_dac_hpll_wr_o <= '0';
regs_o.spll_dac_main_value_wr_o <= '0';
regs_o.spll_dac_main_dac_sel_wr_o <= '0';
regs_o.dac_hpll_wr_o <= '0';
regs_o.dac_main_value_wr_o <= '0';
regs_o.dac_main_dac_sel_wr_o <= '0';
spll_deglitch_thr_int <= "0000000000000000";
regs_o.dfr_spll_value_wr_o <= '0';
regs_o.dfr_spll_eos_wr_o <= '0';
eic_idr_write_int <= '0';
eic_ier_write_int <= '0';
eic_isr_write_int <= '0';
spll_dfr_host_rdreq_int <= '0';
spll_trr_rdreq_int <= '0';
elsif rising_edge(bus_clock_int) then
elsif rising_edge(clk_sys_i) then
-- advance the ACK generator shift register
ack_sreg(8 downto 0) <= ack_sreg(9 downto 1);
ack_sreg(9) <= '0';
if (ack_in_progress = '1') then
if (ack_sreg(0) = '1') then
regs_o.spll_rcer_load_o <= '0';
regs_o.spll_ocer_load_o <= '0';
regs_o.rcger_gate_sel_wr_o <= '0';
regs_o.rcer_load_o <= '0';
regs_o.ocer_load_o <= '0';
tag_hpll_rd_period_o <= '0';
regs_o.spll_dac_hpll_wr_o <= '0';
regs_o.spll_dac_main_value_wr_o <= '0';
regs_o.spll_dac_main_dac_sel_wr_o <= '0';
regs_o.dac_hpll_wr_o <= '0';
regs_o.dac_main_value_wr_o <= '0';
regs_o.dac_main_dac_sel_wr_o <= '0';
regs_o.dfr_spll_value_wr_o <= '0';
regs_o.dfr_spll_eos_wr_o <= '0';
eic_idr_write_int <= '0';
eic_ier_write_int <= '0';
eic_isr_write_int <= '0';
ack_in_progress <= '0';
else
regs_o.spll_rcer_load_o <= '0';
regs_o.spll_ocer_load_o <= '0';
regs_o.spll_dac_hpll_wr_o <= '0';
regs_o.spll_dac_main_value_wr_o <= '0';
regs_o.spll_dac_main_dac_sel_wr_o <= '0';
regs_o.rcger_gate_sel_wr_o <= '0';
regs_o.rcer_load_o <= '0';
regs_o.ocer_load_o <= '0';
regs_o.dac_hpll_wr_o <= '0';
regs_o.dac_main_value_wr_o <= '0';
regs_o.dac_main_dac_sel_wr_o <= '0';
regs_o.dfr_spll_value_wr_o <= '0';
regs_o.dfr_spll_eos_wr_o <= '0';
end if;
else
if ((wb_cyc_i = '1') and (wb_stb_i = '1')) then
case rwaddr_reg(3 downto 0) is
when "0000" =>
case rwaddr_reg(4 downto 0) is
when "00000" =>
if (wb_we_i = '1') then
spll_csr_per_sel_int <= wrdata_reg(5 downto 0);
else
rddata_reg(5 downto 0) <= spll_csr_per_sel_int;
rddata_reg(13 downto 8) <= regs_i.spll_csr_n_ref_i;
rddata_reg(18 downto 16) <= regs_i.spll_csr_n_out_i;
rddata_reg(6) <= 'X';
rddata_reg(7) <= 'X';
rddata_reg(14) <= 'X';
rddata_reg(15) <= 'X';
rddata_reg(19) <= 'X';
rddata_reg(20) <= 'X';
rddata_reg(21) <= 'X';
rddata_reg(22) <= 'X';
rddata_reg(23) <= 'X';
rddata_reg(24) <= 'X';
rddata_reg(25) <= 'X';
rddata_reg(26) <= 'X';
rddata_reg(27) <= 'X';
rddata_reg(28) <= 'X';
rddata_reg(29) <= 'X';
rddata_reg(30) <= 'X';
rddata_reg(31) <= 'X';
spll_csr_per_en_int <= wrdata_reg(19);
end if;
rddata_reg(5 downto 0) <= spll_csr_per_sel_int;
rddata_reg(13 downto 8) <= regs_i.csr_n_ref_i;
rddata_reg(18 downto 16) <= regs_i.csr_n_out_i;
rddata_reg(19) <= spll_csr_per_en_int;
rddata_reg(6) <= 'X';
rddata_reg(7) <= 'X';
rddata_reg(14) <= 'X';
rddata_reg(15) <= 'X';
rddata_reg(20) <= 'X';
rddata_reg(21) <= 'X';
rddata_reg(22) <= 'X';
rddata_reg(23) <= 'X';
rddata_reg(24) <= 'X';
rddata_reg(25) <= 'X';
rddata_reg(26) <= 'X';
rddata_reg(27) <= 'X';
rddata_reg(28) <= 'X';
rddata_reg(29) <= 'X';
rddata_reg(30) <= 'X';
rddata_reg(31) <= 'X';
ack_sreg(0) <= '1';
ack_in_progress <= '1';
when "00001" =>
if (wb_we_i = '1') then
spll_dccr_gate_div_int <= wrdata_reg(5 downto 0);
end if;
rddata_reg(5 downto 0) <= spll_dccr_gate_div_int;
rddata_reg(6) <= 'X';
rddata_reg(7) <= 'X';
rddata_reg(8) <= 'X';
rddata_reg(9) <= 'X';
rddata_reg(10) <= 'X';
rddata_reg(11) <= 'X';
rddata_reg(12) <= 'X';
rddata_reg(13) <= 'X';
rddata_reg(14) <= 'X';
rddata_reg(15) <= 'X';
rddata_reg(16) <= 'X';
rddata_reg(17) <= 'X';
rddata_reg(18) <= 'X';
rddata_reg(19) <= 'X';
rddata_reg(20) <= 'X';
rddata_reg(21) <= 'X';
rddata_reg(22) <= 'X';
rddata_reg(23) <= 'X';
rddata_reg(24) <= 'X';
rddata_reg(25) <= 'X';
rddata_reg(26) <= 'X';
rddata_reg(27) <= 'X';
rddata_reg(28) <= 'X';
rddata_reg(29) <= 'X';
rddata_reg(30) <= 'X';
rddata_reg(31) <= 'X';
ack_sreg(0) <= '1';
ack_in_progress <= '1';
when "00010" =>
if (wb_we_i = '1') then
regs_o.rcger_gate_sel_wr_o <= '1';
end if;
rddata_reg(0) <= 'X';
rddata_reg(1) <= 'X';
rddata_reg(2) <= 'X';
rddata_reg(3) <= 'X';
rddata_reg(4) <= 'X';
rddata_reg(5) <= 'X';
rddata_reg(6) <= 'X';
rddata_reg(7) <= 'X';
rddata_reg(8) <= 'X';
rddata_reg(9) <= 'X';
rddata_reg(10) <= 'X';
rddata_reg(11) <= 'X';
rddata_reg(12) <= 'X';
rddata_reg(13) <= 'X';
rddata_reg(14) <= 'X';
rddata_reg(15) <= 'X';
rddata_reg(16) <= 'X';
rddata_reg(17) <= 'X';
rddata_reg(18) <= 'X';
rddata_reg(19) <= 'X';
rddata_reg(20) <= 'X';
rddata_reg(21) <= 'X';
rddata_reg(22) <= 'X';
rddata_reg(23) <= 'X';
rddata_reg(24) <= 'X';
rddata_reg(25) <= 'X';
rddata_reg(26) <= 'X';
rddata_reg(27) <= 'X';
rddata_reg(28) <= 'X';
rddata_reg(29) <= 'X';
rddata_reg(30) <= 'X';
rddata_reg(31) <= 'X';
ack_sreg(0) <= '1';
ack_in_progress <= '1';
when "0001" =>
when "00011" =>
if (wb_we_i = '1') then
spll_occr_out_lock_int <= wrdata_reg(15 downto 8);
else
rddata_reg(7 downto 0) <= regs_i.spll_occr_out_en_i;
rddata_reg(15 downto 8) <= spll_occr_out_lock_int;
rddata_reg(16) <= 'X';
rddata_reg(17) <= 'X';
rddata_reg(18) <= 'X';
rddata_reg(19) <= 'X';
rddata_reg(20) <= 'X';
rddata_reg(21) <= 'X';
rddata_reg(22) <= 'X';
rddata_reg(23) <= 'X';
rddata_reg(24) <= 'X';
rddata_reg(25) <= 'X';
rddata_reg(26) <= 'X';
rddata_reg(27) <= 'X';
rddata_reg(28) <= 'X';
rddata_reg(29) <= 'X';
rddata_reg(30) <= 'X';
rddata_reg(31) <= 'X';
end if;
rddata_reg(7 downto 0) <= regs_i.occr_out_en_i;
rddata_reg(15 downto 8) <= spll_occr_out_lock_int;
rddata_reg(16) <= 'X';
rddata_reg(17) <= 'X';
rddata_reg(18) <= 'X';
rddata_reg(19) <= 'X';
rddata_reg(20) <= 'X';
rddata_reg(21) <= 'X';
rddata_reg(22) <= 'X';
rddata_reg(23) <= 'X';
rddata_reg(24) <= 'X';
rddata_reg(25) <= 'X';
rddata_reg(26) <= 'X';
rddata_reg(27) <= 'X';
rddata_reg(28) <= 'X';
rddata_reg(29) <= 'X';
rddata_reg(30) <= 'X';
rddata_reg(31) <= 'X';
ack_sreg(0) <= '1';
ack_in_progress <= '1';
when "0010" =>
when "00100" =>
if (wb_we_i = '1') then
regs_o.spll_rcer_load_o <= '1';
else
rddata_reg(31 downto 0) <= regs_i.spll_rcer_i;
regs_o.rcer_load_o <= '1';
end if;
rddata_reg(31 downto 0) <= regs_i.rcer_i;
ack_sreg(0) <= '1';
ack_in_progress <= '1';
when "0011" =>
when "00101" =>
if (wb_we_i = '1') then
regs_o.spll_ocer_load_o <= '1';
else
rddata_reg(7 downto 0) <= regs_i.spll_ocer_i;
rddata_reg(8) <= 'X';
rddata_reg(9) <= 'X';
rddata_reg(10) <= 'X';
rddata_reg(11) <= 'X';
rddata_reg(12) <= 'X';
rddata_reg(13) <= 'X';
rddata_reg(14) <= 'X';
rddata_reg(15) <= 'X';
rddata_reg(16) <= 'X';
rddata_reg(17) <= 'X';
rddata_reg(18) <= 'X';
rddata_reg(19) <= 'X';
rddata_reg(20) <= 'X';
rddata_reg(21) <= 'X';
rddata_reg(22) <= 'X';
rddata_reg(23) <= 'X';
rddata_reg(24) <= 'X';
rddata_reg(25) <= 'X';
rddata_reg(26) <= 'X';
rddata_reg(27) <= 'X';
rddata_reg(28) <= 'X';
rddata_reg(29) <= 'X';
rddata_reg(30) <= 'X';
rddata_reg(31) <= 'X';
regs_o.ocer_load_o <= '1';
end if;
rddata_reg(7 downto 0) <= regs_i.ocer_i;
rddata_reg(8) <= 'X';
rddata_reg(9) <= 'X';
rddata_reg(10) <= 'X';
rddata_reg(11) <= 'X';
rddata_reg(12) <= 'X';
rddata_reg(13) <= 'X';
rddata_reg(14) <= 'X';
rddata_reg(15) <= 'X';
rddata_reg(16) <= 'X';
rddata_reg(17) <= 'X';
rddata_reg(18) <= 'X';
rddata_reg(19) <= 'X';
rddata_reg(20) <= 'X';
rddata_reg(21) <= 'X';
rddata_reg(22) <= 'X';
rddata_reg(23) <= 'X';
rddata_reg(24) <= 'X';
rddata_reg(25) <= 'X';
rddata_reg(26) <= 'X';
rddata_reg(27) <= 'X';
rddata_reg(28) <= 'X';
rddata_reg(29) <= 'X';
rddata_reg(30) <= 'X';
rddata_reg(31) <= 'X';
ack_sreg(0) <= '1';
ack_in_progress <= '1';
when "0100" =>
when "00110" =>
if (wb_we_i = '1') then
rddata_reg(16) <= 'X';
else
rddata_reg(15 downto 0) <= regs_i.spll_per_hpll_error_i;
tag_hpll_rd_period_o <= '1';
rddata_reg(16) <= regs_i.spll_per_hpll_valid_i;
rddata_reg(17) <= 'X';
rddata_reg(18) <= 'X';
rddata_reg(19) <= 'X';
rddata_reg(20) <= 'X';
rddata_reg(21) <= 'X';
rddata_reg(22) <= 'X';
rddata_reg(23) <= 'X';
rddata_reg(24) <= 'X';
rddata_reg(25) <= 'X';
rddata_reg(26) <= 'X';
rddata_reg(27) <= 'X';
rddata_reg(28) <= 'X';
rddata_reg(29) <= 'X';
rddata_reg(30) <= 'X';
rddata_reg(31) <= 'X';
end if;
rddata_reg(15 downto 0) <= regs_i.per_hpll_error_i;
tag_hpll_rd_period_o <= '1';
rddata_reg(16) <= regs_i.per_hpll_valid_i;
rddata_reg(17) <= 'X';
rddata_reg(18) <= 'X';
rddata_reg(19) <= 'X';
rddata_reg(20) <= 'X';
rddata_reg(21) <= 'X';
rddata_reg(22) <= 'X';
rddata_reg(23) <= 'X';
rddata_reg(24) <= 'X';
rddata_reg(25) <= 'X';
rddata_reg(26) <= 'X';
rddata_reg(27) <= 'X';
rddata_reg(28) <= 'X';
rddata_reg(29) <= 'X';
rddata_reg(30) <= 'X';
rddata_reg(31) <= 'X';
ack_sreg(0) <= '1';
ack_in_progress <= '1';
when "0101" =>
when "00111" =>
if (wb_we_i = '1') then
regs_o.spll_dac_hpll_wr_o <= '1';
else
rddata_reg(0) <= 'X';
rddata_reg(1) <= 'X';
rddata_reg(2) <= 'X';
rddata_reg(3) <= 'X';
rddata_reg(4) <= 'X';
rddata_reg(5) <= 'X';
rddata_reg(6) <= 'X';
rddata_reg(7) <= 'X';
rddata_reg(8) <= 'X';
rddata_reg(9) <= 'X';
rddata_reg(10) <= 'X';
rddata_reg(11) <= 'X';
rddata_reg(12) <= 'X';
rddata_reg(13) <= 'X';
rddata_reg(14) <= 'X';
rddata_reg(15) <= 'X';
rddata_reg(16) <= 'X';
rddata_reg(17) <= 'X';
rddata_reg(18) <= 'X';
rddata_reg(19) <= 'X';
rddata_reg(20) <= 'X';
rddata_reg(21) <= 'X';
rddata_reg(22) <= 'X';
rddata_reg(23) <= 'X';
rddata_reg(24) <= 'X';
rddata_reg(25) <= 'X';
rddata_reg(26) <= 'X';
rddata_reg(27) <= 'X';
rddata_reg(28) <= 'X';
rddata_reg(29) <= 'X';
rddata_reg(30) <= 'X';
rddata_reg(31) <= 'X';
regs_o.dac_hpll_wr_o <= '1';
end if;
rddata_reg(0) <= 'X';
rddata_reg(1) <= 'X';
rddata_reg(2) <= 'X';
rddata_reg(3) <= 'X';
rddata_reg(4) <= 'X';
rddata_reg(5) <= 'X';
rddata_reg(6) <= 'X';
rddata_reg(7) <= 'X';
rddata_reg(8) <= 'X';
rddata_reg(9) <= 'X';
rddata_reg(10) <= 'X';
rddata_reg(11) <= 'X';
rddata_reg(12) <= 'X';
rddata_reg(13) <= 'X';
rddata_reg(14) <= 'X';
rddata_reg(15) <= 'X';
rddata_reg(16) <= 'X';
rddata_reg(17) <= 'X';
rddata_reg(18) <= 'X';
rddata_reg(19) <= 'X';
rddata_reg(20) <= 'X';
rddata_reg(21) <= 'X';
rddata_reg(22) <= 'X';
rddata_reg(23) <= 'X';
rddata_reg(24) <= 'X';
rddata_reg(25) <= 'X';
rddata_reg(26) <= 'X';
rddata_reg(27) <= 'X';
rddata_reg(28) <= 'X';
rddata_reg(29) <= 'X';
rddata_reg(30) <= 'X';
rddata_reg(31) <= 'X';
ack_sreg(0) <= '1';
ack_in_progress <= '1';
when "0110" =>
when "01000" =>
if (wb_we_i = '1') then
regs_o.spll_dac_main_value_wr_o <= '1';
regs_o.spll_dac_main_dac_sel_wr_o <= '1';
else
rddata_reg(0) <= 'X';
rddata_reg(1) <= 'X';
rddata_reg(2) <= 'X';
rddata_reg(3) <= 'X';
rddata_reg(4) <= 'X';
rddata_reg(5) <= 'X';
rddata_reg(6) <= 'X';
rddata_reg(7) <= 'X';
rddata_reg(8) <= 'X';
rddata_reg(9) <= 'X';
rddata_reg(10) <= 'X';
rddata_reg(11) <= 'X';
rddata_reg(12) <= 'X';
rddata_reg(13) <= 'X';
rddata_reg(14) <= 'X';
rddata_reg(15) <= 'X';
rddata_reg(16) <= 'X';
rddata_reg(17) <= 'X';
rddata_reg(18) <= 'X';
rddata_reg(19) <= 'X';
rddata_reg(20) <= 'X';
rddata_reg(21) <= 'X';
rddata_reg(22) <= 'X';
rddata_reg(23) <= 'X';
rddata_reg(24) <= 'X';
rddata_reg(25) <= 'X';
rddata_reg(26) <= 'X';
rddata_reg(27) <= 'X';
rddata_reg(28) <= 'X';
rddata_reg(29) <= 'X';
rddata_reg(30) <= 'X';
rddata_reg(31) <= 'X';
regs_o.dac_main_value_wr_o <= '1';
regs_o.dac_main_dac_sel_wr_o <= '1';
end if;
rddata_reg(0) <= 'X';
rddata_reg(1) <= 'X';
rddata_reg(2) <= 'X';
rddata_reg(3) <= 'X';
rddata_reg(4) <= 'X';
rddata_reg(5) <= 'X';
rddata_reg(6) <= 'X';
rddata_reg(7) <= 'X';
rddata_reg(8) <= 'X';
rddata_reg(9) <= 'X';
rddata_reg(10) <= 'X';
rddata_reg(11) <= 'X';
rddata_reg(12) <= 'X';
rddata_reg(13) <= 'X';
rddata_reg(14) <= 'X';
rddata_reg(15) <= 'X';
rddata_reg(16) <= 'X';
rddata_reg(17) <= 'X';
rddata_reg(18) <= 'X';
rddata_reg(19) <= 'X';
rddata_reg(20) <= 'X';
rddata_reg(21) <= 'X';
rddata_reg(22) <= 'X';
rddata_reg(23) <= 'X';
rddata_reg(24) <= 'X';
rddata_reg(25) <= 'X';
rddata_reg(26) <= 'X';
rddata_reg(27) <= 'X';
rddata_reg(28) <= 'X';
rddata_reg(29) <= 'X';
rddata_reg(30) <= 'X';
rddata_reg(31) <= 'X';
ack_sreg(0) <= '1';
ack_in_progress <= '1';
when "0111" =>
when "01001" =>
if (wb_we_i = '1') then
spll_deglitch_thr_int <= wrdata_reg(15 downto 0);
else
rddata_reg(15 downto 0) <= spll_deglitch_thr_int;
rddata_reg(16) <= 'X';
rddata_reg(17) <= 'X';
rddata_reg(18) <= 'X';
rddata_reg(19) <= 'X';
rddata_reg(20) <= 'X';
rddata_reg(21) <= 'X';
rddata_reg(22) <= 'X';
rddata_reg(23) <= 'X';
rddata_reg(24) <= 'X';
rddata_reg(25) <= 'X';
rddata_reg(26) <= 'X';
rddata_reg(27) <= 'X';
rddata_reg(28) <= 'X';
rddata_reg(29) <= 'X';
rddata_reg(30) <= 'X';
rddata_reg(31) <= 'X';
end if;
rddata_reg(15 downto 0) <= spll_deglitch_thr_int;
rddata_reg(16) <= 'X';
rddata_reg(17) <= 'X';
rddata_reg(18) <= 'X';
rddata_reg(19) <= 'X';
rddata_reg(20) <= 'X';
rddata_reg(21) <= 'X';
rddata_reg(22) <= 'X';
rddata_reg(23) <= 'X';
rddata_reg(24) <= 'X';
rddata_reg(25) <= 'X';
rddata_reg(26) <= 'X';
rddata_reg(27) <= 'X';
rddata_reg(28) <= 'X';
rddata_reg(29) <= 'X';
rddata_reg(30) <= 'X';
rddata_reg(31) <= 'X';
ack_sreg(0) <= '1';
ack_in_progress <= '1';
when "01010" =>
if (wb_we_i = '1') then
regs_o.dfr_spll_value_wr_o <= '1';
regs_o.dfr_spll_eos_wr_o <= '1';
end if;
rddata_reg(0) <= 'X';
rddata_reg(1) <= 'X';
rddata_reg(2) <= 'X';
rddata_reg(3) <= 'X';
rddata_reg(4) <= 'X';
rddata_reg(5) <= 'X';
rddata_reg(6) <= 'X';
rddata_reg(7) <= 'X';
rddata_reg(8) <= 'X';
rddata_reg(9) <= 'X';
rddata_reg(10) <= 'X';
rddata_reg(11) <= 'X';
rddata_reg(12) <= 'X';
rddata_reg(13) <= 'X';
rddata_reg(14) <= 'X';
rddata_reg(15) <= 'X';
rddata_reg(16) <= 'X';
rddata_reg(17) <= 'X';
rddata_reg(18) <= 'X';
rddata_reg(19) <= 'X';
rddata_reg(20) <= 'X';
rddata_reg(21) <= 'X';
rddata_reg(22) <= 'X';
rddata_reg(23) <= 'X';
rddata_reg(24) <= 'X';
rddata_reg(25) <= 'X';
rddata_reg(26) <= 'X';
rddata_reg(27) <= 'X';
rddata_reg(28) <= 'X';
rddata_reg(29) <= 'X';
rddata_reg(30) <= 'X';
rddata_reg(31) <= 'X';
ack_sreg(0) <= '1';
ack_in_progress <= '1';
when "1000" =>
when "10000" =>
if (wb_we_i = '1') then
eic_idr_write_int <= '1';
else
rddata_reg(0) <= 'X';
rddata_reg(1) <= 'X';
rddata_reg(2) <= 'X';
rddata_reg(3) <= 'X';
rddata_reg(4) <= 'X';
rddata_reg(5) <= 'X';
rddata_reg(6) <= 'X';
rddata_reg(7) <= 'X';
rddata_reg(8) <= 'X';
rddata_reg(9) <= 'X';
rddata_reg(10) <= 'X';
rddata_reg(11) <= 'X';
rddata_reg(12) <= 'X';
rddata_reg(13) <= 'X';
rddata_reg(14) <= 'X';
rddata_reg(15) <= 'X';
rddata_reg(16) <= 'X';
rddata_reg(17) <= 'X';
rddata_reg(18) <= 'X';
rddata_reg(19) <= 'X';
rddata_reg(20) <= 'X';
rddata_reg(21) <= 'X';
rddata_reg(22) <= 'X';
rddata_reg(23) <= 'X';
rddata_reg(24) <= 'X';
rddata_reg(25) <= 'X';
rddata_reg(26) <= 'X';
rddata_reg(27) <= 'X';
rddata_reg(28) <= 'X';
rddata_reg(29) <= 'X';
rddata_reg(30) <= 'X';
rddata_reg(31) <= 'X';
end if;
rddata_reg(0) <= 'X';
rddata_reg(1) <= 'X';
rddata_reg(2) <= 'X';
rddata_reg(3) <= 'X';
rddata_reg(4) <= 'X';
rddata_reg(5) <= 'X';
rddata_reg(6) <= 'X';
rddata_reg(7) <= 'X';
rddata_reg(8) <= 'X';
rddata_reg(9) <= 'X';
rddata_reg(10) <= 'X';
rddata_reg(11) <= 'X';
rddata_reg(12) <= 'X';
rddata_reg(13) <= 'X';
rddata_reg(14) <= 'X';
rddata_reg(15) <= 'X';
rddata_reg(16) <= 'X';
rddata_reg(17) <= 'X';
rddata_reg(18) <= 'X';
rddata_reg(19) <= 'X';
rddata_reg(20) <= 'X';
rddata_reg(21) <= 'X';
rddata_reg(22) <= 'X';
rddata_reg(23) <= 'X';
rddata_reg(24) <= 'X';
rddata_reg(25) <= 'X';
rddata_reg(26) <= 'X';
rddata_reg(27) <= 'X';
rddata_reg(28) <= 'X';
rddata_reg(29) <= 'X';
rddata_reg(30) <= 'X';
rddata_reg(31) <= 'X';
ack_sreg(0) <= '1';
ack_in_progress <= '1';
when "1001" =>
when "10001" =>
if (wb_we_i = '1') then
eic_ier_write_int <= '1';
else
rddata_reg(0) <= 'X';
rddata_reg(1) <= 'X';
rddata_reg(2) <= 'X';
rddata_reg(3) <= 'X';
rddata_reg(4) <= 'X';
rddata_reg(5) <= 'X';
rddata_reg(6) <= 'X';
rddata_reg(7) <= 'X';
rddata_reg(8) <= 'X';
rddata_reg(9) <= 'X';
rddata_reg(10) <= 'X';
rddata_reg(11) <= 'X';
rddata_reg(12) <= 'X';
rddata_reg(13) <= 'X';
rddata_reg(14) <= 'X';
rddata_reg(15) <= 'X';
rddata_reg(16) <= 'X';
rddata_reg(17) <= 'X';
rddata_reg(18) <= 'X';
rddata_reg(19) <= 'X';
rddata_reg(20) <= 'X';
rddata_reg(21) <= 'X';
rddata_reg(22) <= 'X';
rddata_reg(23) <= 'X';
rddata_reg(24) <= 'X';
rddata_reg(25) <= 'X';
rddata_reg(26) <= 'X';
rddata_reg(27) <= 'X';
rddata_reg(28) <= 'X';
rddata_reg(29) <= 'X';
rddata_reg(30) <= 'X';
rddata_reg(31) <= 'X';
end if;
rddata_reg(0) <= 'X';
rddata_reg(1) <= 'X';
rddata_reg(2) <= 'X';
rddata_reg(3) <= 'X';
rddata_reg(4) <= 'X';
rddata_reg(5) <= 'X';
rddata_reg(6) <= 'X';
rddata_reg(7) <= 'X';
rddata_reg(8) <= 'X';
rddata_reg(9) <= 'X';
rddata_reg(10) <= 'X';
rddata_reg(11) <= 'X';
rddata_reg(12) <= 'X';
rddata_reg(13) <= 'X';
rddata_reg(14) <= 'X';
rddata_reg(15) <= 'X';
rddata_reg(16) <= 'X';
rddata_reg(17) <= 'X';
rddata_reg(18) <= 'X';
rddata_reg(19) <= 'X';
rddata_reg(20) <= 'X';
rddata_reg(21) <= 'X';
rddata_reg(22) <= 'X';
rddata_reg(23) <= 'X';
rddata_reg(24) <= 'X';
rddata_reg(25) <= 'X';
rddata_reg(26) <= 'X';
rddata_reg(27) <= 'X';
rddata_reg(28) <= 'X';
rddata_reg(29) <= 'X';
rddata_reg(30) <= 'X';
rddata_reg(31) <= 'X';
ack_sreg(0) <= '1';
ack_in_progress <= '1';
when "1010" =>
when "10010" =>
if (wb_we_i = '1') then
else
rddata_reg(0) <= eic_imr_int(0);
rddata_reg(1) <= 'X';
rddata_reg(2) <= 'X';
rddata_reg(3) <= 'X';
rddata_reg(4) <= 'X';
rddata_reg(5) <= 'X';
rddata_reg(6) <= 'X';
rddata_reg(7) <= 'X';
rddata_reg(8) <= 'X';
rddata_reg(9) <= 'X';
rddata_reg(10) <= 'X';
rddata_reg(11) <= 'X';
rddata_reg(12) <= 'X';
rddata_reg(13) <= 'X';
rddata_reg(14) <= 'X';
rddata_reg(15) <= 'X';
rddata_reg(16) <= 'X';
rddata_reg(17) <= 'X';
rddata_reg(18) <= 'X';
rddata_reg(19) <= 'X';
rddata_reg(20) <= 'X';
rddata_reg(21) <= 'X';
rddata_reg(22) <= 'X';
rddata_reg(23) <= 'X';
rddata_reg(24) <= 'X';
rddata_reg(25) <= 'X';
rddata_reg(26) <= 'X';
rddata_reg(27) <= 'X';
rddata_reg(28) <= 'X';
rddata_reg(29) <= 'X';
rddata_reg(30) <= 'X';
rddata_reg(31) <= 'X';
end if;
rddata_reg(0) <= eic_imr_int(0);
rddata_reg(1) <= 'X';
rddata_reg(2) <= 'X';
rddata_reg(3) <= 'X';
rddata_reg(4) <= 'X';
rddata_reg(5) <= 'X';
rddata_reg(6) <= 'X';
rddata_reg(7) <= 'X';
rddata_reg(8) <= 'X';
rddata_reg(9) <= 'X';
rddata_reg(10) <= 'X';
rddata_reg(11) <= 'X';
rddata_reg(12) <= 'X';
rddata_reg(13) <= 'X';
rddata_reg(14) <= 'X';
rddata_reg(15) <= 'X';
rddata_reg(16) <= 'X';
rddata_reg(17) <= 'X';
rddata_reg(18) <= 'X';
rddata_reg(19) <= 'X';
rddata_reg(20) <= 'X';
rddata_reg(21) <= 'X';
rddata_reg(22) <= 'X';
rddata_reg(23) <= 'X';
rddata_reg(24) <= 'X';
rddata_reg(25) <= 'X';
rddata_reg(26) <= 'X';
rddata_reg(27) <= 'X';
rddata_reg(28) <= 'X';
rddata_reg(29) <= 'X';
rddata_reg(30) <= 'X';
rddata_reg(31) <= 'X';
ack_sreg(0) <= '1';
ack_in_progress <= '1';
when "1011" =>
when "10011" =>
if (wb_we_i = '1') then
eic_isr_write_int <= '1';
else
rddata_reg(0) <= eic_isr_status_int(0);
rddata_reg(1) <= 'X';
rddata_reg(2) <= 'X';
rddata_reg(3) <= 'X';
rddata_reg(4) <= 'X';
rddata_reg(5) <= 'X';
rddata_reg(6) <= 'X';
rddata_reg(7) <= 'X';
rddata_reg(8) <= 'X';
rddata_reg(9) <= 'X';
rddata_reg(10) <= 'X';
rddata_reg(11) <= 'X';
rddata_reg(12) <= 'X';
rddata_reg(13) <= 'X';
rddata_reg(14) <= 'X';
rddata_reg(15) <= 'X';
rddata_reg(16) <= 'X';
rddata_reg(17) <= 'X';
rddata_reg(18) <= 'X';
rddata_reg(19) <= 'X';
rddata_reg(20) <= 'X';
rddata_reg(21) <= 'X';
rddata_reg(22) <= 'X';
rddata_reg(23) <= 'X';
rddata_reg(24) <= 'X';
rddata_reg(25) <= 'X';
rddata_reg(26) <= 'X';
rddata_reg(27) <= 'X';
rddata_reg(28) <= 'X';
rddata_reg(29) <= 'X';
rddata_reg(30) <= 'X';
rddata_reg(31) <= 'X';
end if;
rddata_reg(0) <= eic_isr_status_int(0);
rddata_reg(1) <= 'X';
rddata_reg(2) <= 'X';
rddata_reg(3) <= 'X';
rddata_reg(4) <= 'X';
rddata_reg(5) <= 'X';
rddata_reg(6) <= 'X';
rddata_reg(7) <= 'X';
rddata_reg(8) <= 'X';
rddata_reg(9) <= 'X';
rddata_reg(10) <= 'X';
rddata_reg(11) <= 'X';
rddata_reg(12) <= 'X';
rddata_reg(13) <= 'X';
rddata_reg(14) <= 'X';
rddata_reg(15) <= 'X';
rddata_reg(16) <= 'X';
rddata_reg(17) <= 'X';
rddata_reg(18) <= 'X';
rddata_reg(19) <= 'X';
rddata_reg(20) <= 'X';
rddata_reg(21) <= 'X';
rddata_reg(22) <= 'X';
rddata_reg(23) <= 'X';
rddata_reg(24) <= 'X';
rddata_reg(25) <= 'X';
rddata_reg(26) <= 'X';
rddata_reg(27) <= 'X';
rddata_reg(28) <= 'X';
rddata_reg(29) <= 'X';
rddata_reg(30) <= 'X';
rddata_reg(31) <= 'X';
ack_sreg(0) <= '1';
ack_in_progress <= '1';
when "1100" =>
when "10100" =>
if (wb_we_i = '1') then
end if;
if (spll_dfr_host_rdreq_int_d0 = '0') then
spll_dfr_host_rdreq_int <= not spll_dfr_host_rdreq_int;
else
if (spll_trr_rdreq_int_d0 = '0') then
spll_trr_rdreq_int <= not spll_trr_rdreq_int;
else
rddata_reg(23 downto 0) <= spll_trr_out_int(23 downto 0);
rddata_reg(30 downto 24) <= spll_trr_out_int(30 downto 24);
rddata_reg(31) <= spll_trr_out_int(31);
ack_in_progress <= '1';
ack_sreg(0) <= '1';
end if;
rddata_reg(31 downto 0) <= spll_dfr_host_out_int(31 downto 0);
ack_in_progress <= '1';
ack_sreg(0) <= '1';
end if;
when "10101" =>
if (wb_we_i = '1') then
end if;
rddata_reg(15 downto 0) <= spll_dfr_host_out_int(47 downto 32);
rddata_reg(16) <= 'X';
rddata_reg(17) <= 'X';
rddata_reg(18) <= 'X';
rddata_reg(19) <= 'X';
rddata_reg(20) <= 'X';
rddata_reg(21) <= 'X';
rddata_reg(22) <= 'X';
rddata_reg(23) <= 'X';
rddata_reg(24) <= 'X';
rddata_reg(25) <= 'X';
rddata_reg(26) <= 'X';
rddata_reg(27) <= 'X';
rddata_reg(28) <= 'X';
rddata_reg(29) <= 'X';
rddata_reg(30) <= 'X';
rddata_reg(31) <= 'X';
ack_sreg(0) <= '1';
ack_in_progress <= '1';
when "10110" =>
if (wb_we_i = '1') then
end if;
when "1101" =>
rddata_reg(16) <= spll_dfr_host_full_int;
rddata_reg(17) <= spll_dfr_host_empty_int;
rddata_reg(12 downto 0) <= spll_dfr_host_usedw_int;
rddata_reg(13) <= 'X';
rddata_reg(14) <= 'X';
rddata_reg(15) <= 'X';
rddata_reg(18) <= 'X';
rddata_reg(19) <= 'X';
rddata_reg(20) <= 'X';
rddata_reg(21) <= 'X';
rddata_reg(22) <= 'X';
rddata_reg(23) <= 'X';
rddata_reg(24) <= 'X';
rddata_reg(25) <= 'X';
rddata_reg(26) <= 'X';
rddata_reg(27) <= 'X';
rddata_reg(28) <= 'X';
rddata_reg(29) <= 'X';
rddata_reg(30) <= 'X';
rddata_reg(31) <= 'X';
ack_sreg(0) <= '1';
ack_in_progress <= '1';
when "10111" =>
if (wb_we_i = '1') then
end if;
if (spll_trr_rdreq_int_d0 = '0') then
spll_trr_rdreq_int <= not spll_trr_rdreq_int;
else
rddata_reg(17) <= spll_trr_empty_int;
rddata_reg(0) <= 'X';
rddata_reg(1) <= 'X';
rddata_reg(2) <= 'X';
rddata_reg(3) <= 'X';
rddata_reg(4) <= 'X';
rddata_reg(5) <= 'X';
rddata_reg(6) <= 'X';
rddata_reg(7) <= 'X';
rddata_reg(8) <= 'X';
rddata_reg(9) <= 'X';
rddata_reg(10) <= 'X';
rddata_reg(11) <= 'X';
rddata_reg(12) <= 'X';
rddata_reg(13) <= 'X';
rddata_reg(14) <= 'X';
rddata_reg(15) <= 'X';
rddata_reg(16) <= 'X';
rddata_reg(18) <= 'X';
rddata_reg(19) <= 'X';
rddata_reg(20) <= 'X';
rddata_reg(21) <= 'X';
rddata_reg(22) <= 'X';
rddata_reg(23) <= 'X';
rddata_reg(24) <= 'X';
rddata_reg(25) <= 'X';
rddata_reg(26) <= 'X';
rddata_reg(27) <= 'X';
rddata_reg(28) <= 'X';
rddata_reg(29) <= 'X';
rddata_reg(30) <= 'X';
rddata_reg(31) <= 'X';
rddata_reg(23 downto 0) <= spll_trr_out_int(23 downto 0);
rddata_reg(30 downto 24) <= spll_trr_out_int(30 downto 24);
rddata_reg(31) <= spll_trr_out_int(31);
ack_in_progress <= '1';
ack_sreg(0) <= '1';
end if;
when "11000" =>
if (wb_we_i = '1') then
end if;
rddata_reg(17) <= spll_trr_empty_int;
rddata_reg(0) <= 'X';
rddata_reg(1) <= 'X';
rddata_reg(2) <= 'X';
rddata_reg(3) <= 'X';
rddata_reg(4) <= 'X';
rddata_reg(5) <= 'X';
rddata_reg(6) <= 'X';
rddata_reg(7) <= 'X';
rddata_reg(8) <= 'X';
rddata_reg(9) <= 'X';
rddata_reg(10) <= 'X';
rddata_reg(11) <= 'X';
rddata_reg(12) <= 'X';
rddata_reg(13) <= 'X';
rddata_reg(14) <= 'X';
rddata_reg(15) <= 'X';
rddata_reg(16) <= 'X';
rddata_reg(18) <= 'X';
rddata_reg(19) <= 'X';
rddata_reg(20) <= 'X';
rddata_reg(21) <= 'X';
rddata_reg(22) <= 'X';
rddata_reg(23) <= 'X';
rddata_reg(24) <= 'X';
rddata_reg(25) <= 'X';
rddata_reg(26) <= 'X';
rddata_reg(27) <= 'X';
rddata_reg(28) <= 'X';
rddata_reg(29) <= 'X';
rddata_reg(30) <= 'X';
rddata_reg(31) <= 'X';
ack_sreg(0) <= '1';
ack_in_progress <= '1';
when others =>
......@@ -564,35 +739,74 @@ begin
-- Drive the data output bus
wb_data_o <= rddata_reg;
wb_dat_o <= rddata_reg;
-- Period detector reference select
regs_o.spll_csr_per_sel_o <= spll_csr_per_sel_int;
regs_o.csr_per_sel_o <= spll_csr_per_sel_int;
-- Number of reference channels (max: 32)
-- Number of output channels (max: 8)
-- Enable Period Measurement
regs_o.csr_per_en_o <= spll_csr_per_en_int;
-- DMTD Clock Gate Divider
regs_o.dccr_gate_div_o <= spll_dccr_gate_div_int;
-- Reference Channel Gating Enable
-- pass-through field: Reference Channel Gating Enable in register: Reference Channel Gating Enable Register
regs_o.rcger_gate_sel_o <= wrdata_reg(31 downto 0);
-- Output Channel HW enable flag
-- Output Channel locked flag
regs_o.spll_occr_out_lock_o <= spll_occr_out_lock_int;
regs_o.occr_out_lock_o <= spll_occr_out_lock_int;
-- Reference Channel Enable
regs_o.spll_rcer_o <= wrdata_reg(31 downto 0);
regs_o.rcer_o <= wrdata_reg(31 downto 0);
-- Output Channel Enable
regs_o.spll_ocer_o <= wrdata_reg(7 downto 0);
regs_o.ocer_o <= wrdata_reg(7 downto 0);
-- Period error value
-- Period Error Valid
-- DAC value
-- pass-through field: DAC value in register: Helper DAC Output
regs_o.spll_dac_hpll_o <= wrdata_reg(15 downto 0);
regs_o.dac_hpll_o <= wrdata_reg(15 downto 0);
-- DAC value
-- pass-through field: DAC value in register: Main DAC Output
regs_o.spll_dac_main_value_o <= wrdata_reg(15 downto 0);
regs_o.dac_main_value_o <= wrdata_reg(15 downto 0);
-- DAC select
-- pass-through field: DAC select in register: Main DAC Output
regs_o.spll_dac_main_dac_sel_o <= wrdata_reg(19 downto 16);
regs_o.dac_main_dac_sel_o <= wrdata_reg(19 downto 16);
-- Threshold
regs_o.spll_deglitch_thr_o <= spll_deglitch_thr_int;
regs_o.deglitch_thr_o <= spll_deglitch_thr_int;
-- Debug Value
-- pass-through field: Debug Value in register: Debug FIFO Register - SPLL side
regs_o.dfr_spll_value_o <= wrdata_reg(30 downto 0);
-- End-of-Sample
-- pass-through field: End-of-Sample in register: Debug FIFO Register - SPLL side
regs_o.dfr_spll_eos_o <= wrdata_reg(31);
-- extra code for reg/fifo/mem: Debug FIFO Register - Host side
spll_dfr_host_in_int(31 downto 0) <= regs_i.dfr_host_value_i;
spll_dfr_host_in_int(47 downto 32) <= regs_i.dfr_host_seq_id_i;
spll_dfr_host_rst_n <= rst_n_i;
spll_dfr_host_INST : wbgen2_fifo_sync
generic map (
g_size => 8192,
g_width => 48,
g_usedw_size => 13
)
port map (
wr_req_i => regs_i.dfr_host_wr_req_i,
wr_full_o => regs_o.dfr_host_wr_full_o,
wr_empty_o => regs_o.dfr_host_wr_empty_o,
wr_usedw_o => regs_o.dfr_host_wr_usedw_o,
rd_full_o => spll_dfr_host_full_int,
rd_empty_o => spll_dfr_host_empty_int,
rd_usedw_o => spll_dfr_host_usedw_int,
rd_req_i => spll_dfr_host_rdreq_int,
rst_n_i => spll_dfr_host_rst_n,
clk_i => clk_sys_i,
wr_data_i => spll_dfr_host_in_int,
rd_data_o => spll_dfr_host_out_int
);
-- extra code for reg/fifo/mem: Tag Readout Register
spll_trr_in_int(23 downto 0) <= regs_i.spll_trr_value_i;
spll_trr_in_int(30 downto 24) <= regs_i.spll_trr_chan_id_i;
spll_trr_in_int(31) <= regs_i.spll_trr_disc_i;
spll_trr_in_int(23 downto 0) <= regs_i.trr_value_i;
spll_trr_in_int(30 downto 24) <= regs_i.trr_chan_id_i;
spll_trr_in_int(31) <= regs_i.trr_disc_i;
spll_trr_rst_n <= rst_n_i;
spll_trr_INST : wbgen2_fifo_sync
generic map (
g_size => 32,
......@@ -600,13 +814,13 @@ begin
g_usedw_size => 5
)
port map (
wr_req_i => regs_i.spll_trr_wr_req_i,
wr_full_o => regs_o.spll_trr_wr_full_o,
rd_full_o => open,
wr_req_i => regs_i.trr_wr_req_i,
wr_full_o => regs_o.trr_wr_full_o,
wr_empty_o => regs_o.trr_wr_empty_o,
rd_empty_o => spll_trr_empty_int,
rd_usedw_o => open,
rd_req_i => spll_trr_rdreq_int,
clk_i => bus_clock_int,
rst_n_i => spll_trr_rst_n,
clk_i => clk_sys_i,
wr_data_i => spll_trr_in_int,
rd_data_o => spll_trr_out_int
);
......@@ -655,7 +869,7 @@ begin
g_irq1f_mode => 0
)
port map (
clk_i => bus_clock_int,
clk_i => clk_sys_i,
rst_n_i => rst_n_i,
irq_i => irq_inputs_vector_int,
irq_ack_o => eic_irq_ack_int,
......@@ -667,22 +881,35 @@ begin
reg_isr_o => eic_isr_status_int,
reg_isr_i => eic_isr_clear_int,
reg_isr_wr_stb_i => eic_isr_write_int,
wb_irq_o => wb_irq_o
wb_irq_o => wb_int_o
);
irq_inputs_vector_int(0) <= irq_tag_i;
-- extra code for reg/fifo/mem: FIFO 'Debug FIFO Register - Host side' data output register 0
process (clk_sys_i, rst_n_i)
begin
if (rst_n_i = '0') then
spll_dfr_host_rdreq_int_d0 <= '0';
elsif rising_edge(clk_sys_i) then
spll_dfr_host_rdreq_int_d0 <= spll_dfr_host_rdreq_int;
end if;
end process;
-- extra code for reg/fifo/mem: FIFO 'Debug FIFO Register - Host side' data output register 1
-- extra code for reg/fifo/mem: FIFO 'Tag Readout Register' data output register 0
process (bus_clock_int, rst_n_i)
process (clk_sys_i, rst_n_i)
begin
if (rst_n_i = '0') then
spll_trr_rdreq_int_d0 <= '0';
elsif rising_edge(bus_clock_int) then
elsif rising_edge(clk_sys_i) then
spll_trr_rdreq_int_d0 <= spll_trr_rdreq_int;
end if;
end process;
rwaddr_reg <= wb_addr_i;
rwaddr_reg <= wb_adr_i;
wb_stall_o <= (not ack_sreg(0)) and (wb_stb_i and wb_cyc_i);
-- ACK signal generation. Just pass the LSB of ACK counter.
wb_ack_o <= ack_sreg(0);
end syn;
spll_wb_slave.wb
View file @ a975b77b
......@@ -3,12 +3,13 @@
peripheral {
name = "WR Softcore PLL";
hdl_entity = "spll_wb_slave";
prefix = "SPLL";
prefix = "spll";
reg {
name = "SPLL Control/Status Register";
prefix = "CSR";
field {
align = 8;
name = "Period detector reference select";
......@@ -38,8 +39,45 @@ peripheral {
access_bus = READ_ONLY;
access_dev = WRITE_ONLY;
};
field {
name = "Enable Period Measurement";
prefix = "PER_EN";
type = BIT;
access_bus = READ_WRITE;
access_dev = READ_ONLY;
};
};
reg {
name = "DMTD Clock Control Register";
prefix = "DCCR";
field {
name = "DMTD Clock Gate Divider";
prefix = "GATE_DIV";
size = 6;
type = SLV;
access_bus = READ_WRITE;
access_dev = READ_ONLY;
};
};
reg {
name = "Reference Channel Gating Enable Register";
prefix = "RCGER";
field {
name = "Reference Channel Gating Enable";
prefix = "GATE_SEL";
size = 32;
type = PASS_THROUGH;
};
};
reg {
name = "Output Channel Control Register";
prefix = "OCCR";
......@@ -165,13 +203,56 @@ peripheral {
};
};
reg {
name = "Debug FIFO Register - SPLL side";
prefix = "DFR_SPLL";
field {
name = "Debug Value";
prefix = "VALUE";
size = 31;
type = PASS_THROUGH;
};
field {
name = "End-of-Sample";
prefix = "EOS";
size = 1;
type = PASS_THROUGH;
};
};
fifo_reg {
name = "Debug FIFO Register - Host side";
prefix = "DFR_HOST";
direction = CORE_TO_BUS;
size = 8192;
flags_dev = {FIFO_FULL, FIFO_EMPTY, FIFO_COUNT};
flags_bus = {FIFO_FULL, FIFO_EMPTY, FIFO_COUNT};
field {
name = "Value";
prefix = "VALUE";
type = SLV;
size = 32;
};
field {
name = "Seq ID";
prefix = "SEQ_ID";
type = SLV;
size = 16;
};
};
fifo_reg {
name = "Tag Readout Register";
prefix = "TRR";
direction = CORE_TO_BUS;
size = 32;
flags_dev = {FIFO_FULL};
flags_dev = {FIFO_FULL, FIFO_EMPTY};
flags_bus = {FIFO_EMPTY};
field {
......@@ -196,6 +277,8 @@ peripheral {
};
};
irq {
name = "Got a tag";
prefix = "TAG";
......
spll_wbgen2_pkg.vhd
View file @ a975b77b
......@@ -2,11 +2,11 @@
-- Title : Wishbone slave core for WR Softcore PLL
---------------------------------------------------------------------------------------
-- File : spll_wbgen2_pkg.vhd
-- Author : auto-generated by wbgen2 from wr_softpll.wb
-- Created : Wed Jan 18 13:13:08 2012
-- Author : auto-generated by wbgen2 from spll_wb_slave.wb
-- Created : Wed Mar 7 11:09:45 2012
-- Standard : VHDL'87
---------------------------------------------------------------------------------------
-- THIS FILE WAS GENERATED BY wbgen2 FROM SOURCE FILE wr_softpll.wb
-- THIS FILE WAS GENERATED BY wbgen2 FROM SOURCE FILE spll_wb_slave.wb
-- DO NOT HAND-EDIT UNLESS IT'S ABSOLUTELY NECESSARY!
---------------------------------------------------------------------------------------
......@@ -15,79 +15,110 @@ use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use work.wbgen2_pkg.all;
package SPLL_wbgen2_pkg is
package spll_wbgen2_pkg is
-- Input registers (user design -> WB slave)
type t_SPLL_in_registers is record
spll_csr_n_ref_i : std_logic_vector(5 downto 0);
spll_csr_n_out_i : std_logic_vector(2 downto 0);
spll_occr_out_en_i : std_logic_vector(7 downto 0);
spll_rcer_i : std_logic_vector(31 downto 0);
spll_ocer_i : std_logic_vector(7 downto 0);
spll_per_hpll_error_i : std_logic_vector(15 downto 0);
spll_per_hpll_valid_i : std_logic;
spll_trr_wr_req_i : std_logic;
spll_trr_value_i : std_logic_vector(23 downto 0);
spll_trr_chan_id_i : std_logic_vector(6 downto 0);
spll_trr_disc_i : std_logic;
type t_spll_in_registers is record
csr_n_ref_i : std_logic_vector(5 downto 0);
csr_n_out_i : std_logic_vector(2 downto 0);
occr_out_en_i : std_logic_vector(7 downto 0);
rcer_i : std_logic_vector(31 downto 0);
ocer_i : std_logic_vector(7 downto 0);
per_hpll_error_i : std_logic_vector(15 downto 0);
per_hpll_valid_i : std_logic;
dfr_host_wr_req_i : std_logic;
dfr_host_value_i : std_logic_vector(31 downto 0);
dfr_host_seq_id_i : std_logic_vector(15 downto 0);
trr_wr_req_i : std_logic;
trr_value_i : std_logic_vector(23 downto 0);
trr_chan_id_i : std_logic_vector(6 downto 0);
trr_disc_i : std_logic;
end record;
constant c_SPLL_in_registers_init_value: t_SPLL_in_registers := (
spll_csr_n_ref_i => (others => '0'),
spll_csr_n_out_i => (others => '0'),
spll_occr_out_en_i => (others => '0'),
spll_rcer_i => (others => '0'),
spll_ocer_i => (others => '0'),
spll_per_hpll_error_i => (others => '0'),
spll_per_hpll_valid_i => '0',
spll_trr_wr_req_i => '0',
spll_trr_value_i => (others => '0'),
spll_trr_chan_id_i => (others => '0'),
spll_trr_disc_i => '0'
constant c_spll_in_registers_init_value: t_spll_in_registers := (
csr_n_ref_i => (others => '0'),
csr_n_out_i => (others => '0'),
occr_out_en_i => (others => '0'),
rcer_i => (others => '0'),
ocer_i => (others => '0'),
per_hpll_error_i => (others => '0'),
per_hpll_valid_i => '0',
dfr_host_wr_req_i => '0',
dfr_host_value_i => (others => '0'),
dfr_host_seq_id_i => (others => '0'),
trr_wr_req_i => '0',
trr_value_i => (others => '0'),
trr_chan_id_i => (others => '0'),
trr_disc_i => '0'
);
-- Output registers (WB slave -> user design)
type t_SPLL_out_registers is record
spll_csr_per_sel_o : std_logic_vector(5 downto 0);
spll_occr_out_lock_o : std_logic_vector(7 downto 0);
spll_rcer_o : std_logic_vector(31 downto 0);
spll_rcer_load_o : std_logic;
spll_ocer_o : std_logic_vector(7 downto 0);
spll_ocer_load_o : std_logic;
spll_dac_hpll_o : std_logic_vector(15 downto 0);
spll_dac_hpll_wr_o : std_logic;
spll_dac_main_value_o : std_logic_vector(15 downto 0);
spll_dac_main_value_wr_o : std_logic;
spll_dac_main_dac_sel_o : std_logic_vector(3 downto 0);
spll_dac_main_dac_sel_wr_o : std_logic;
spll_deglitch_thr_o : std_logic_vector(15 downto 0);
spll_trr_wr_full_o : std_logic;
type t_spll_out_registers is record
csr_per_sel_o : std_logic_vector(5 downto 0);
csr_per_en_o : std_logic;
dccr_gate_div_o : std_logic_vector(5 downto 0);
rcger_gate_sel_o : std_logic_vector(31 downto 0);
rcger_gate_sel_wr_o : std_logic;
occr_out_lock_o : std_logic_vector(7 downto 0);
rcer_o : std_logic_vector(31 downto 0);
rcer_load_o : std_logic;
ocer_o : std_logic_vector(7 downto 0);
ocer_load_o : std_logic;
dac_hpll_o : std_logic_vector(15 downto 0);
dac_hpll_wr_o : std_logic;
dac_main_value_o : std_logic_vector(15 downto 0);
dac_main_value_wr_o : std_logic;
dac_main_dac_sel_o : std_logic_vector(3 downto 0);
dac_main_dac_sel_wr_o : std_logic;
deglitch_thr_o : std_logic_vector(15 downto 0);
dfr_spll_value_o : std_logic_vector(30 downto 0);
dfr_spll_value_wr_o : std_logic;
dfr_spll_eos_o : std_logic;
dfr_spll_eos_wr_o : std_logic;
dfr_host_wr_full_o : std_logic;
dfr_host_wr_empty_o : std_logic;
dfr_host_wr_usedw_o : std_logic_vector(12 downto 0);
trr_wr_full_o : std_logic;
trr_wr_empty_o : std_logic;
end record;
constant c_SPLL_out_registers_init_value: t_SPLL_out_registers := (
spll_csr_per_sel_o => (others => '0'),
spll_occr_out_lock_o => (others => '0'),
spll_rcer_o => (others => '0'),
spll_rcer_load_o => '0',
spll_ocer_o => (others => '0'),
spll_ocer_load_o => '0',
spll_dac_hpll_o => (others => '0'),
spll_dac_hpll_wr_o => '0',
spll_dac_main_value_o => (others => '0'),
spll_dac_main_value_wr_o => '0',
spll_dac_main_dac_sel_o => (others => '0'),
spll_dac_main_dac_sel_wr_o => '0',
spll_deglitch_thr_o => (others => '0'),
spll_trr_wr_full_o => '0'
constant c_spll_out_registers_init_value: t_spll_out_registers := (
csr_per_sel_o => (others => '0'),
csr_per_en_o => '0',
dccr_gate_div_o => (others => '0'),
rcger_gate_sel_o => (others => '0'),
rcger_gate_sel_wr_o => '0',
occr_out_lock_o => (others => '0'),
rcer_o => (others => '0'),
rcer_load_o => '0',
ocer_o => (others => '0'),
ocer_load_o => '0',
dac_hpll_o => (others => '0'),
dac_hpll_wr_o => '0',
dac_main_value_o => (others => '0'),
dac_main_value_wr_o => '0',
dac_main_dac_sel_o => (others => '0'),
dac_main_dac_sel_wr_o => '0',
deglitch_thr_o => (others => '0'),
dfr_spll_value_o => (others => '0'),
dfr_spll_value_wr_o => '0',
dfr_spll_eos_o => '0',
dfr_spll_eos_wr_o => '0',
dfr_host_wr_full_o => '0',
dfr_host_wr_empty_o => '0',
dfr_host_wr_usedw_o => (others => '0'),
trr_wr_full_o => '0',
trr_wr_empty_o => '0'
);
function "or" (left, right: t_SPLL_in_registers) return t_SPLL_in_registers;
function "or" (left, right: t_spll_in_registers) return t_spll_in_registers;
function f_x_to_zero (x:std_logic) return std_logic;
function f_x_to_zero (x:std_logic_vector) return std_logic_vector;
end package;
package body SPLL_wbgen2_pkg is
package body spll_wbgen2_pkg is
function f_x_to_zero (x:std_logic) return std_logic is
begin
if(x = 'X' or x = 'U') then
......@@ -96,20 +127,35 @@ else
return x;
end if;
end function;
function "or" (left, right: t_SPLL_in_registers) return t_SPLL_in_registers is
variable tmp: t_SPLL_in_registers;
function f_x_to_zero (x:std_logic_vector) return std_logic_vector is
variable tmp: std_logic_vector(x'length-1 downto 0);
begin
tmp.spll_csr_n_ref_i := left.spll_csr_n_ref_i or right.spll_csr_n_ref_i;
tmp.spll_csr_n_out_i := left.spll_csr_n_out_i or right.spll_csr_n_out_i;
tmp.spll_occr_out_en_i := left.spll_occr_out_en_i or right.spll_occr_out_en_i;
tmp.spll_rcer_i := left.spll_rcer_i or right.spll_rcer_i;
tmp.spll_ocer_i := left.spll_ocer_i or right.spll_ocer_i;
tmp.spll_per_hpll_error_i := left.spll_per_hpll_error_i or right.spll_per_hpll_error_i;
tmp.spll_per_hpll_valid_i := left.spll_per_hpll_valid_i or right.spll_per_hpll_valid_i;
tmp.spll_trr_wr_req_i := left.spll_trr_wr_req_i or right.spll_trr_wr_req_i;
tmp.spll_trr_value_i := left.spll_trr_value_i or right.spll_trr_value_i;
tmp.spll_trr_chan_id_i := left.spll_trr_chan_id_i or right.spll_trr_chan_id_i;
tmp.spll_trr_disc_i := left.spll_trr_disc_i or right.spll_trr_disc_i;
for i in 0 to x'length-1 loop
if(x(i) = 'X' or x(i) = 'U') then
tmp(i):= '0';
else
tmp(i):=x(i);
end if;
end loop;
return tmp;
end function;
function "or" (left, right: t_spll_in_registers) return t_spll_in_registers is
variable tmp: t_spll_in_registers;
begin
tmp.csr_n_ref_i := f_x_to_zero(left.csr_n_ref_i) or f_x_to_zero(right.csr_n_ref_i);
tmp.csr_n_out_i := f_x_to_zero(left.csr_n_out_i) or f_x_to_zero(right.csr_n_out_i);
tmp.occr_out_en_i := f_x_to_zero(left.occr_out_en_i) or f_x_to_zero(right.occr_out_en_i);
tmp.rcer_i := f_x_to_zero(left.rcer_i) or f_x_to_zero(right.rcer_i);
tmp.ocer_i := f_x_to_zero(left.ocer_i) or f_x_to_zero(right.ocer_i);
tmp.per_hpll_error_i := f_x_to_zero(left.per_hpll_error_i) or f_x_to_zero(right.per_hpll_error_i);
tmp.per_hpll_valid_i := f_x_to_zero(left.per_hpll_valid_i) or f_x_to_zero(right.per_hpll_valid_i);
tmp.dfr_host_wr_req_i := f_x_to_zero(left.dfr_host_wr_req_i) or f_x_to_zero(right.dfr_host_wr_req_i);
tmp.dfr_host_value_i := f_x_to_zero(left.dfr_host_value_i) or f_x_to_zero(right.dfr_host_value_i);
tmp.dfr_host_seq_id_i := f_x_to_zero(left.dfr_host_seq_id_i) or f_x_to_zero(right.dfr_host_seq_id_i);
tmp.trr_wr_req_i := f_x_to_zero(left.trr_wr_req_i) or f_x_to_zero(right.trr_wr_req_i);
tmp.trr_value_i := f_x_to_zero(left.trr_value_i) or f_x_to_zero(right.trr_value_i);
tmp.trr_chan_id_i := f_x_to_zero(left.trr_chan_id_i) or f_x_to_zero(right.trr_chan_id_i);
tmp.trr_disc_i := f_x_to_zero(left.trr_disc_i) or f_x_to_zero(right.trr_disc_i);
return tmp;
end function;
end package body;
wr_softpll_ng.vhd 0 → 100644
View file @ a975b77b
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use work.gencores_pkg.all;
use work.wishbone_pkg.all;
use work.spll_wbgen2_pkg.all;
entity wr_softpll_ng is
generic(
g_tag_bits : integer;
g_interface_mode : t_wishbone_interface_mode := PIPELINED;
g_address_granularity : t_wishbone_address_granularity := BYTE;
g_num_ref_inputs : integer := 1;
g_num_outputs : integer := 1;
-- choose which clocks should go to the period detector, to avoid connecting
-- extra calibration signals as clocks (such as PLL status pin, which doesn't
-- drive a BUFG)
g_period_detector_ref_mask : std_logic_vector(31 downto 0) := x"ffffffff"
);
port(
clk_sys_i : in std_logic;
rst_n_i : in std_logic;
-- Reference inputs (i.e. the RX clocks recovered by the PHYs)
clk_ref_i : in std_logic_vector(g_num_ref_inputs-1 downto 0);
-- Feedback clocks (i.e. the outputs of the main or aux oscillator)
clk_fb_i : in std_logic_vector(g_num_outputs-1 downto 0);
-- DMTD Offset clock
clk_dmtd_i : in std_logic;
-- DMTD oscillator drive
dac_dmtd_data_o : out std_logic_vector(15 downto 0);
dac_dmtd_load_o : out std_logic;
-- Output channel DAC value
dac_out_data_o : out std_logic_vector(15 downto 0);
-- Output channel select (0 = channel 0, etc. )
dac_out_sel_o : out std_logic_vector(3 downto 0);
dac_out_load_o : out std_logic;
out_enable_i : in std_logic_vector(g_num_outputs-1 downto 0);
out_locked_o : out std_logic_vector(g_num_outputs-1 downto 0);
wb_adr_i : in std_logic_vector(6 downto 0);
wb_dat_i : in std_logic_vector(31 downto 0);
wb_dat_o : out std_logic_vector(31 downto 0);
wb_cyc_i : in std_logic;
wb_sel_i : in std_logic_vector(3 downto 0);
wb_stb_i : in std_logic;
wb_we_i : in std_logic;
wb_ack_o : out std_logic;
wb_stall_o : out std_logic;
wb_irq_o : out std_logic;
debug_o : out std_logic_vector(3 downto 0);
dbg_fifo_irq_o : out std_logic
);
end wr_softpll_ng;
architecture rtl of wr_softpll_ng is
constant c_log2_replication : integer := 2;
constant c_use_multi_dmtd : boolean := false;
component multi_dmtd_with_deglitcher
generic (
g_counter_bits : natural;
g_log2_replication : natural);
port (
rst_n_dmtdclk_i : in std_logic;
rst_n_sysclk_i : in std_logic;
clk_dmtd_i : in std_logic;
clk_sys_i : in std_logic;
clk_in_i : in std_logic;
tag_o : out std_logic_vector(g_counter_bits-1 downto 0);
tag_stb_p_o : out std_logic;
shift_en_i : in std_logic;
shift_dir_i : in std_logic;
deglitch_threshold_i : in std_logic_vector(15 downto 0);
dbg_dmtdout_o : out std_logic);
end component;
component dmtd_with_deglitcher
generic (
g_counter_bits : natural;
g_chipscope : boolean := false);
port (
rst_n_dmtdclk_i : in std_logic;
rst_n_sysclk_i : in std_logic;
clk_in_i : in std_logic;
clk_dmtd_i : in std_logic;
clk_dmtd_en_i : in std_logic;
clk_sys_i : in std_logic;
shift_en_i : in std_logic;
shift_dir_i : in std_logic;
deglitch_threshold_i : in std_logic_vector(15 downto 0);
dbg_dmtdout_o : out std_logic;
tag_o : out std_logic_vector(g_counter_bits-1 downto 0);
tag_stb_p1_o : out std_logic);
end component;
component spll_period_detect
generic (
g_num_ref_inputs : integer);
port (
clk_ref_i : in std_logic_vector(g_num_ref_inputs-1 downto 0);
clk_dmtd_i : in std_logic;
clk_sys_i : in std_logic;
rst_n_dmtdclk_i : in std_logic;
rst_n_sysclk_i : in std_logic;
freq_err_o : out std_logic_vector(11 downto 0);
freq_err_stb_p_o : out std_logic;
in_sel_i : in std_logic_vector(4 downto 0));
end component;
component spll_wb_slave
port (
clk_sys_i : in std_logic;
rst_n_i : in std_logic;
wb_adr_i : in std_logic_vector(4 downto 0);
wb_dat_i : in std_logic_vector(31 downto 0);
wb_dat_o : out std_logic_vector(31 downto 0);
wb_cyc_i : in std_logic;
wb_sel_i : in std_logic_vector(3 downto 0);
wb_stb_i : in std_logic;
wb_we_i : in std_logic;
wb_ack_o : out std_logic;
wb_int_o : out std_logic;
wb_stall_o : out std_logic;
tag_hpll_rd_period_o : out std_logic;
irq_tag_i : in std_logic;
regs_i : in t_SPLL_in_registers;
regs_o : out t_SPLL_out_registers);
end component;
procedure f_rr_arbitrate (
signal req : in std_logic_vector;
signal pre_grant : in std_logic_vector;
signal grant : out std_logic_vector)is
variable reqs : std_logic_vector(req'length - 1 downto 0);
variable gnts : std_logic_vector(req'length - 1 downto 0);
variable gnt : std_logic_vector(req'length - 1 downto 0);
variable gntM : std_logic_vector(req'length - 1 downto 0);
variable zeros : std_logic_vector(req'length - 1 downto 0);
begin
zeros := (others => '0');
reqs := req;
-- bit twiddling magic :
gnt := reqs and std_logic_vector(unsigned(not reqs) + 1);
reqs := reqs and not (std_logic_vector(unsigned(pre_grant) - 1) or pre_grant);
gnts := reqs and std_logic_vector(unsigned(not reqs) + 1);
if(reqs = zeros) then
gntM := gnt;
else
gntM := gnts;
end if;
if((req and pre_grant) = zeros) then
grant <= gntM;
end if;
end f_rr_arbitrate;
function f_onehot_decode(x : std_logic_vector) return std_logic_vector is
begin
for j in 0 to x'left loop
if x(j) /= '0' then
return std_logic_vector(to_unsigned(j, 6));
end if;
end loop; -- i
return std_logic_vector(to_unsigned(0, 6));
end f_onehot_decode;
type t_tag_array is array (0 to g_num_ref_inputs + g_num_outputs-1) of std_logic_vector(g_tag_bits-1 downto 0);
signal tags, tags_masked : t_tag_array;
signal tags_grant_p, tags_p, tags_req, tags_grant : std_logic_vector(g_num_ref_inputs+ g_num_outputs-1 downto 0);
signal tag_muxed : std_logic_vector(g_tag_bits-1 downto 0);
signal tag_src, tag_src_pre : std_logic_vector (5 downto 0);
signal tag_valid, tag_valid_pre : std_logic;
signal rst_n_refclk : std_logic;
signal rst_n_dmtdclk : std_logic;
signal rst_n_rxclk : std_logic_vector(g_num_ref_inputs-1 downto 0);
signal deglitch_thr_slv : std_logic_vector(15 downto 0);
signal tag_hpll_rd_period_ack : std_logic;
signal irq_tag : std_logic;
signal dmtd_freq_err : std_logic_vector(11 downto 0);
signal dmtd_freq_err_stb_p : std_logic;
signal rcer_int : std_logic_vector(g_num_ref_inputs-1 downto 0);
signal ocer_int : std_logic_vector(g_num_outputs-1 downto 0);
signal clk_ref_buf : std_logic;
signal clk_rx_buf : std_logic;
signal wb_irq_out : std_logic;
component BUFG
port (
O : out std_logic;
I : in std_logic);
end component;
signal resized_addr : std_logic_vector(c_wishbone_address_width-1 downto 0);
signal wb_out : t_wishbone_slave_out;
signal wb_in : t_wishbone_slave_in;
signal regs_in : t_SPLL_out_registers;
signal regs_out : t_SPLL_in_registers;
signal per_clk_ref : std_logic_vector(g_num_ref_inputs downto 0);
signal dmtd_gating_cnt : unsigned(5 downto 0);
signal clk_dmtd_en_gated : std_logic;
signal clk_dmtd_en_ref : std_logic_vector(31 downto 0);
signal clk_dmtd_gate_sel : std_logic_vector(31 downto 0);
signal dbg_fifo_almostfull : std_logic;
signal dbg_seq_id : unsigned(15 downto 0);
signal dbg_fifo_permit_write : std_logic;
constant c_DBG_FIFO_THRESHOLD : integer := 8180;
constant c_DBG_FIFO_COALESCE : integer := 100;
begin -- rtl
-- DMTD Gating counter. Gates the DMTD clock enable for the DDMTDs
-- effectively dividing its frequency by the gating count. This allows for
-- sampling clocks of frequencies lower than 125 / 62.5 MHz, for example the
-- 10 MHz external timing reference.
p_gen_dmtd_gating : process(clk_dmtd_i)
begin
if rising_edge(clk_dmtd_i) then
if rst_n_dmtdclk = '0' then
dmtd_gating_cnt <= (others => '0');
clk_dmtd_en_gated <= '0';
else
if(std_logic_vector(dmtd_gating_cnt) = regs_in.dccr_gate_div_o) then
dmtd_gating_cnt <= (others => '0');
clk_dmtd_en_gated <= '1';
else
dmtd_gating_cnt <= dmtd_gating_cnt + 1;
clk_dmtd_en_gated <= '0';
end if;
end if;
end if;
end process;
-- selects full speed or gated mode for the reference channels
gen_ref_channels_clk_enables : for i in 0 to g_num_ref_inputs-1 generate
p_gating_register : process(clk_sys_i)
begin
if rising_edge(clk_sys_i) then
if(regs_in.rcger_gate_sel_wr_o = '1') then
clk_dmtd_gate_sel(i) <= regs_in.rcger_gate_sel_o(i);
end if;
end if;
end process;
p_select_dmtd_gating_chx : process(clk_dmtd_i)
begin
if rising_edge(clk_dmtd_i) then
if(clk_dmtd_gate_sel(i) = '1') then
clk_dmtd_en_ref(i) <= clk_dmtd_en_gated;
else
clk_dmtd_en_ref(i) <= '1';
end if;
end if;
end process;
end generate gen_ref_channels_clk_enables;
resized_addr(6 downto 0) <= wb_adr_i;
resized_addr(c_wishbone_address_width-1 downto 7) <= (others => '0');
U_Adapter : wb_slave_adapter
generic map(
g_master_use_struct => true,
g_master_mode => CLASSIC,
g_master_granularity => WORD,
g_slave_use_struct => false,
g_slave_mode => g_interface_mode,
g_slave_granularity => g_address_granularity)
port map (
clk_sys_i => clk_sys_i,
rst_n_i => rst_n_i,
master_i => wb_out,
master_o => wb_in,
sl_adr_i => resized_addr,
sl_dat_i => wb_dat_i,
sl_sel_i => wb_sel_i,
sl_cyc_i => wb_cyc_i,
sl_stb_i => wb_stb_i,
sl_we_i => wb_we_i,
sl_dat_o => wb_dat_o,
sl_ack_o => wb_ack_o,
sl_stall_o => wb_stall_o);
sync_ffs_rst2 : gc_sync_ffs
generic map (
g_sync_edge => "positive")
port map (
clk_i => clk_dmtd_i,
rst_n_i => '1',
data_i => rst_n_i,
synced_o => rst_n_dmtdclk,
npulse_o => open,
ppulse_o => open);
--gen_with_single_dmtd : if(c_use_multi_dmtd = false) generate
gen_ref_dmtds : for i in 0 to g_num_ref_inputs-1 generate
DMTD_REF : dmtd_with_deglitcher
generic map (
g_counter_bits => g_tag_bits,
g_chipscope => false)
port map (
rst_n_dmtdclk_i => rst_n_dmtdclk,
rst_n_sysclk_i => rst_n_i,
clk_dmtd_i => clk_dmtd_i,
clk_dmtd_en_i => clk_dmtd_en_ref(i),
clk_sys_i => clk_sys_i,
clk_in_i => clk_ref_i(i),
tag_o => tags(i),
tag_stb_p1_o => tags_p(i),
shift_en_i => '0',
shift_dir_i => '0',
deglitch_threshold_i => deglitch_thr_slv,
dbg_dmtdout_o => open);
end generate gen_ref_dmtds;
gen_feedback_dmtds : for i in 0 to g_num_outputs-1 generate
DMTD_FB : dmtd_with_deglitcher
generic map (
g_counter_bits => g_tag_bits)
port map (
rst_n_dmtdclk_i => rst_n_dmtdclk,
rst_n_sysclk_i => rst_n_i,
clk_dmtd_i => clk_dmtd_i,
clk_dmtd_en_i => '1',
clk_sys_i => clk_sys_i,
clk_in_i => clk_fb_i(i),
tag_o => tags(i+g_num_ref_inputs),
tag_stb_p1_o => tags_p(i+g_num_ref_inputs),
shift_en_i => '0',
shift_dir_i => '0',
deglitch_threshold_i => deglitch_thr_slv,
dbg_dmtdout_o => open);
end generate gen_feedback_dmtds;
U_WB_SLAVE : spll_wb_slave
port map (
clk_sys_i => clk_sys_i,
rst_n_i => rst_n_i,
wb_adr_i => wb_in.adr(4 downto 0),
wb_dat_i => wb_in.dat,
wb_dat_o => wb_out.dat,
wb_cyc_i => wb_in.cyc,
wb_sel_i => wb_in.sel,
wb_stb_i => wb_in.stb,
wb_we_i => wb_in.we,
wb_ack_o => wb_out.ack,
wb_int_o => wb_irq_out,
wb_stall_o => open,
tag_hpll_rd_period_o => tag_hpll_rd_period_ack,
regs_o => regs_in,
regs_i => regs_out,
irq_tag_i => irq_tag);
per_clk_ref(g_num_ref_inputs-1 downto 0) <= clk_ref_i and g_period_detector_ref_mask(g_num_ref_inputs-1 downto 0);
per_clk_ref(g_num_ref_inputs) <= clk_fb_i(0);
-- Frequency/Period detector (to speed up locking)
U_Period_Detector : spll_period_detect
generic map (
g_num_ref_inputs => g_num_ref_inputs + 1)
port map (
clk_ref_i => per_clk_ref,
clk_dmtd_i => clk_dmtd_i,
clk_sys_i => clk_sys_i,
rst_n_dmtdclk_i => rst_n_dmtdclk,
rst_n_sysclk_i => rst_n_i,
freq_err_o => dmtd_freq_err,
freq_err_stb_p_o => dmtd_freq_err_stb_p,
in_sel_i => regs_in.csr_per_sel_o(4 downto 0));
wb_irq_o <= wb_irq_out;
dac_dmtd_load_o <= regs_in.dac_hpll_wr_o;
dac_dmtd_data_o <= regs_in.dac_hpll_o;
dac_out_data_o <= regs_in.dac_main_value_o;
dac_out_sel_o <= regs_in.dac_main_dac_sel_o;
dac_out_load_o <= regs_in.dac_main_value_wr_o;
p_collect_tags_hpll : process(clk_sys_i)
begin
if rising_edge(clk_sys_i) then
if(rst_n_i = '0') then
regs_out.per_hpll_valid_i <= '0';
regs_out.per_hpll_error_i <= (others => '0');
else
if(dmtd_freq_err_stb_p = '1')then
regs_out.per_hpll_error_i(11 downto 0) <= dmtd_freq_err;
regs_out.per_hpll_error_i(15 downto 12) <= (others => dmtd_freq_err(dmtd_freq_err'left));
end if;
if(dmtd_freq_err_stb_p = '1' and regs_in.csr_per_en_o = '1') then
regs_out.per_hpll_valid_i <= '1';
elsif(tag_hpll_rd_period_ack = '1' or regs_in.csr_per_en_o = '0') then
regs_out.per_hpll_valid_i <= '0';
end if;
end if;
end if;
end process;
p_ocer_rcer_regs : process(clk_sys_i)
begin
if rising_edge(clk_sys_i) then
if rst_n_i = '0' then
ocer_int <= (others => '0');
rcer_int <= (others => '0');
else
if(regs_in.ocer_load_o = '1') then
ocer_int <= regs_in.ocer_o(g_num_outputs -1 downto 0);
end if;
if(regs_in.rcer_load_o = '1') then
rcer_int <= regs_in.rcer_o(g_num_ref_inputs -1 downto 0);
end if;
end if;
end if;
end process;
-- Drive back the respective registers
regs_out.ocer_i(g_num_outputs-1 downto 0) <= ocer_int;
regs_out.rcer_i(g_num_ref_inputs-1 downto 0) <= rcer_int;
p_latch_tags_hpll : process(clk_sys_i)
begin
if rising_edge(clk_sys_i) then
if(rst_n_i = '0') then
tags_req <= (others => '0');
tags_grant <= (others => '0');
else
f_rr_arbitrate(tags_req, tags_grant, tags_grant);
for i in 0 to g_num_ref_inputs-1 loop
if(tags_p(i) = '1') then
tags_req(i) <= rcer_int(i);
elsif(tags_grant(i) = '1') then
tags_req(i) <= '0';
end if;
end loop; -- i
for i in 0 to g_num_outputs-1 loop
if(tags_p(i + g_num_ref_inputs) = '1') then
tags_req(i + g_num_ref_inputs) <= ocer_int(i);
elsif(tags_grant(i + g_num_ref_inputs) = '1') then
tags_req(i + g_num_ref_inputs) <= '0';
end if;
end loop; -- i
end if;
end if;
end process;
tags_grant_p <= tags_req and tags_grant;
p_mux_tags : process(clk_sys_i)
variable muxed : std_logic_vector(g_tag_bits-1 downto 0);
variable src_id : std_logic_vector(5 downto 0);
begin
if rising_edge(clk_sys_i) then
if rst_n_i = '0' then
tag_muxed <= (others => '0');
tag_src_pre <= (others => '0');
tag_src <= (others => '0');
tag_valid_pre <= '0';
tag_valid <= '0';
else
for i in 0 to g_num_ref_inputs+g_num_outputs-1 loop
if(tags_grant_p(i) = '1') then
tags_masked(i) <= tags(i);
else
tags_masked(i) <= (others => '0');
end if;
end loop; -- i
if(unsigned(tags_grant_p) /= 0) then
tag_valid_pre <= '1';
else
tag_valid_pre <= '0';
end if;
tag_valid <= tag_valid_pre;
tag_src_pre <= f_onehot_decode(tags_grant_p);
tag_src <= tag_src_pre;
muxed := (others => '0');
for i in 0 to g_num_ref_inputs+g_num_outputs-1 loop
muxed := muxed or tags_masked(i);
end loop;
tag_muxed <= muxed;
end if;
end if;
end process;
regs_out.trr_wr_req_i <= tag_valid and not regs_in.trr_wr_full_o;
regs_out.trr_value_i(g_tag_bits-1 downto 0) <= tag_muxed;
regs_out.trr_chan_id_i <= '0'&tag_src;
regs_out.occr_out_en_i(g_num_outputs-1 downto 0) <= out_enable_i;
regs_out.occr_out_en_i(7 downto g_num_outputs) <= (others => '0');
irq_tag <= '1' when regs_out.per_hpll_valid_i = '1' or regs_in.trr_wr_empty_o = '0' else '0';
deglitch_thr_slv <= regs_in.deglitch_thr_o;
-----------------------------------------------------------------------------
-- Debugging FIFO
-----------------------------------------------------------------------------
dbg_fifo_almostfull <= '1' when unsigned(regs_in.dfr_host_wr_usedw_o) > 8180 else '0';
p_request_counter : process(clk_sys_i)
begin
if rising_edge(clk_sys_i) then
if rst_n_i = '0' then
dbg_seq_id <= (others => '0');
else
if(regs_in.dfr_spll_eos_o = '1' and regs_in.dfr_spll_eos_wr_o = '1') then
dbg_seq_id <= dbg_seq_id + 1;
end if;
end if;
end if;
end process;
p_fifo_permit_write : process(clk_sys_i)
begin
if rising_edge(clk_sys_i) then
if rst_n_i = '0' then
dbg_fifo_permit_write <= '1';
else
if(dbg_fifo_almostfull = '0') then
dbg_fifo_permit_write <= '1';
elsif(regs_in.dfr_spll_eos_o = '1' and regs_in.dfr_spll_eos_wr_o = '1') then
dbg_fifo_permit_write <= '0';
end if;
end if;
end if;
end process;
p_coalesce_fifo_irq : process(clk_sys_i)
begin
if rising_edge(clk_sys_i) then
if rst_n_i = '0' then
dbg_fifo_irq_o <= '0';
else
if(unsigned(regs_in.dfr_host_wr_usedw_o) = 0) then
dbg_fifo_irq_o <= '0';
elsif(unsigned(regs_in.dfr_host_wr_usedw_o) = c_DBG_FIFO_COALESCE) then
dbg_fifo_irq_o <= '1';
end if;
end if;
end if;
end process;
regs_out.dfr_host_wr_req_i <= regs_in.dfr_spll_value_wr_o and dbg_fifo_permit_write;
regs_out.dfr_host_value_i <= regs_in.dfr_spll_eos_o & regs_in.dfr_spll_value_o;
regs_out.dfr_host_seq_id_i <= std_logic_vector(dbg_seq_id);
-----------------------------------------------------------------------------
-- CSR N_OUT/N_REF fields
-----------------------------------------------------------------------------
regs_out.csr_n_ref_i <= std_logic_vector(to_unsigned(g_num_ref_inputs, regs_out.csr_n_ref_i'length));
regs_out.csr_n_out_i <= std_logic_vector(to_unsigned(g_num_outputs, regs_out.csr_n_out_i'length));
end rtl;
xwr_softpll_ng.vhd 0 → 100644
View file @ a975b77b
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use work.gencores_pkg.all;
use work.wishbone_pkg.all;
entity xwr_softpll_ng is
generic(
g_tag_bits : integer;
g_interface_mode : t_wishbone_interface_mode := CLASSIC;
g_address_granularity : t_wishbone_address_granularity := WORD;
g_num_ref_inputs : integer;
g_num_outputs : integer;
g_period_detector_ref_mask : std_logic_vector(31 downto 0) := x"ffffffff"
);
port(
clk_sys_i : in std_logic;
rst_n_i : in std_logic;
-- Reference inputs (i.e. the RX clocks recovered by the PHYs)
clk_ref_i : in std_logic_vector(g_num_ref_inputs-1 downto 0);
-- Feedback clocks (i.e. the outputs of the main or aux oscillator)
clk_fb_i : in std_logic_vector(g_num_outputs-1 downto 0);
-- DMTD Offset clock
clk_dmtd_i : in std_logic;
-- DMTD oscillator drive
dac_dmtd_data_o : out std_logic_vector(15 downto 0);
dac_dmtd_load_o : out std_logic;
-- Output channel DAC value
dac_out_data_o : out std_logic_vector(15 downto 0);
-- Output channel select (0 = channel 0, etc. )
dac_out_sel_o : out std_logic_vector(3 downto 0);
dac_out_load_o : out std_logic;
out_enable_i : in std_logic_vector(g_num_outputs-1 downto 0);
out_locked_o : out std_logic_vector(g_num_outputs-1 downto 0);
slave_i : in t_wishbone_slave_in;
slave_o : out t_wishbone_slave_out;
debug_o : out std_logic_vector(3 downto 0)
);
end xwr_softpll_ng;
architecture wrapper of xwr_softpll_ng is
component wr_softpll_ng
generic (
g_tag_bits : integer;
g_interface_mode : t_wishbone_interface_mode;
g_address_granularity : t_wishbone_address_granularity;
g_num_ref_inputs : integer;
g_num_outputs : integer;
g_period_detector_ref_mask : std_logic_vector(31 downto 0) := x"ffffffff"
);
port (
clk_sys_i : in std_logic;
rst_n_i : in std_logic;
clk_ref_i : in std_logic_vector(g_num_ref_inputs-1 downto 0);
clk_fb_i : in std_logic_vector(g_num_outputs-1 downto 0);
clk_dmtd_i : in std_logic;
dac_dmtd_data_o : out std_logic_vector(15 downto 0);
dac_dmtd_load_o : out std_logic;
dac_out_data_o : out std_logic_vector(15 downto 0);
dac_out_sel_o : out std_logic_vector(3 downto 0);
dac_out_load_o : out std_logic;
out_enable_i : in std_logic_vector(g_num_outputs-1 downto 0);
out_locked_o : out std_logic_vector(g_num_outputs-1 downto 0);
wb_adr_i : in std_logic_vector(6 downto 0);
wb_dat_i : in std_logic_vector(31 downto 0);
wb_dat_o : out std_logic_vector(31 downto 0);
wb_cyc_i : in std_logic;
wb_sel_i : in std_logic_vector(3 downto 0);
wb_stb_i : in std_logic;
wb_we_i : in std_logic;
wb_ack_o : out std_logic;
wb_stall_o : out std_logic;
wb_irq_o : out std_logic;
debug_o : out std_logic_vector(3 downto 0));
end component;
begin -- behavioral
U_Wrapped_Softpll : wr_softpll_ng
generic map (
g_tag_bits => g_tag_bits,
g_interface_mode => g_interface_mode,
g_address_granularity => g_address_granularity,
g_num_ref_inputs => g_num_ref_inputs,
g_num_outputs => g_num_outputs,
g_period_detector_ref_mask => g_period_detector_ref_mask)
port map (
clk_sys_i => clk_sys_i,
rst_n_i => rst_n_i,
clk_ref_i => clk_ref_i,
clk_fb_i => clk_fb_i,
clk_dmtd_i => clk_dmtd_i,
dac_dmtd_data_o => dac_dmtd_data_o,
dac_dmtd_load_o => dac_dmtd_load_o,
dac_out_data_o => dac_out_data_o,
dac_out_sel_o => dac_out_sel_o,
dac_out_load_o => dac_out_load_o,
out_enable_i => out_enable_i,
out_locked_o => out_locked_o,
wb_adr_i => slave_i.adr(6 downto 0),
wb_dat_i => slave_i.dat,
wb_dat_o => slave_o.dat,
wb_cyc_i => slave_i.cyc,
wb_sel_i => slave_i.sel,
wb_stb_i => slave_i.stb,
wb_we_i => slave_i.we,
wb_ack_o => slave_o.ack,
wb_stall_o => slave_o.stall,
wb_irq_o => slave_o.int,
debug_o => debug_o);
end wrapper;
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