Skip to content
Projects
Groups
Snippets
Help
Loading...
Sign in
Toggle navigation
W
White Rabbit core collection
Project
Project
Details
Activity
Cycle Analytics
Repository
Repository
Files
Commits
Branches
Tags
Contributors
Graph
Compare
Charts
Issues
30
Issues
30
List
Board
Labels
Milestones
Merge Requests
1
Merge Requests
1
CI / CD
CI / CD
Pipelines
Schedules
Wiki
Wiki
image/svg+xml
Discourse
Discourse
Members
Members
Collapse sidebar
Close sidebar
Activity
Graph
Charts
Create a new issue
Commits
Issue Boards
Open sidebar
Projects
White Rabbit core collection
Commits
9fdb9f5b
Commit
9fdb9f5b
authored
Oct 29, 2015
by
Grzegorz Daniluk
Browse files
Options
Browse Files
Download
Email Patches
Plain Diff
modules/fabric: adding xwrf_loopback module for testing WRPC with network tester
parent
e61affca
Hide whitespace changes
Inline
Side-by-side
Showing
14 changed files
with
1324 additions
and
1 deletion
+1324
-1
Manifest.py
modules/fabric/Manifest.py
+3
-1
wr_fabric_pkg.vhd
modules/fabric/wr_fabric_pkg.vhd
+18
-0
build_wb.sh
modules/fabric/xwrf_loopback/build_wb.sh
+4
-0
lbk_pkg.vhd
modules/fabric/xwrf_loopback/lbk_pkg.vhd
+107
-0
lbk_wishbone.wb
modules/fabric/xwrf_loopback/lbk_wishbone.wb
+96
-0
lbk_wishbone_controller.vhd
modules/fabric/xwrf_loopback/lbk_wishbone_controller.vhd
+237
-0
wrf_loopback.vhd
modules/fabric/xwrf_loopback/wrf_loopback.vhd
+113
-0
xwrf_loopback.vhd
modules/fabric/xwrf_loopback/xwrf_loopback.vhd
+398
-0
lbk_regs.v
sim/lbk_regs.v
+12
-0
Manifest.py
testbench/xwrf_loopback/Manifest.py
+15
-0
functions.svh
testbench/xwrf_loopback/functions.svh
+110
-0
main.sv
testbench/xwrf_loopback/main.sv
+146
-0
run.do
testbench/xwrf_loopback/run.do
+12
-0
wave.do
testbench/xwrf_loopback/wave.do
+53
-0
No files found.
modules/fabric/Manifest.py
View file @
9fdb9f5b
files
=
[
"wr_fabric_pkg.vhd"
,
"xwb_fabric_sink.vhd"
,
"xwb_fabric_source.vhd"
,
"xwrf_mux.vhd"
,
"xwrf_reg.vhd"
]
files
=
[
"wr_fabric_pkg.vhd"
,
"xwb_fabric_sink.vhd"
,
"xwb_fabric_source.vhd"
,
"xwrf_mux.vhd"
,
"xwrf_reg.vhd"
,
"xwrf_loopback/lbk_pkg.vhd"
,
"xwrf_loopback/lbk_wishbone_controller.vhd"
,
"xwrf_loopback/xwrf_loopback.vhd"
,
"xwrf_loopback/wrf_loopback.vhd"
];
modules/fabric/wr_fabric_pkg.vhd
View file @
9fdb9f5b
library
ieee
;
use
ieee
.
std_logic_1164
.
all
;
use
work
.
wishbone_pkg
.
all
;
package
wr_fabric_pkg
is
...
...
@@ -104,6 +105,23 @@ package wr_fabric_pkg is
src_o
:
out
t_wrf_source_out
);
end
component
;
component
xwrf_loopback
generic
(
g_interface_mode
:
t_wishbone_interface_mode
:
=
CLASSIC
;
g_address_granularity
:
t_wishbone_address_granularity
:
=
WORD
);
port
(
clk_sys_i
:
in
std_logic
;
rst_n_i
:
in
std_logic
;
wrf_snk_i
:
in
t_wrf_sink_in
;
wrf_snk_o
:
out
t_wrf_sink_out
;
wrf_src_o
:
out
t_wrf_source_out
;
wrf_src_i
:
in
t_wrf_source_in
;
wb_i
:
in
t_wishbone_slave_in
;
wb_o
:
out
t_wishbone_slave_out
);
end
component
;
end
wr_fabric_pkg
;
package
body
wr_fabric_pkg
is
...
...
modules/fabric/xwrf_loopback/build_wb.sh
0 → 100755
View file @
9fdb9f5b
#!/bin/bash
mkdir
-p
doc
wbgen2
-D
./doc/xwrf_loopback.html
-C
lbk_regs.h
-p
lbk_pkg.vhd
-H
record
-V
lbk_wishbone_controller.vhd
--cstyle
struct
--lang
vhdl
-K
../../sim/lbk_regs.v lbk_wishbone.wb
modules/fabric/xwrf_loopback/lbk_pkg.vhd
0 → 100644
View file @
9fdb9f5b
---------------------------------------------------------------------------------------
-- Title : Wishbone slave core for WRF Loopback
---------------------------------------------------------------------------------------
-- File : lbk_pkg.vhd
-- Author : auto-generated by wbgen2 from lbk_wishbone.wb
-- Created : Wed Oct 28 15:10:33 2015
-- Standard : VHDL'87
---------------------------------------------------------------------------------------
-- THIS FILE WAS GENERATED BY wbgen2 FROM SOURCE FILE lbk_wishbone.wb
-- DO NOT HAND-EDIT UNLESS IT'S ABSOLUTELY NECESSARY!
---------------------------------------------------------------------------------------
library
ieee
;
use
ieee
.
std_logic_1164
.
all
;
use
ieee
.
numeric_std
.
all
;
package
lbk_wbgen2_pkg
is
-- Input registers (user design -> WB slave)
type
t_lbk_in_registers
is
record
dmac_l_i
:
std_logic_vector
(
31
downto
0
);
dmac_h_i
:
std_logic_vector
(
15
downto
0
);
rcv_cnt_i
:
std_logic_vector
(
31
downto
0
);
drp_cnt_i
:
std_logic_vector
(
31
downto
0
);
fwd_cnt_i
:
std_logic_vector
(
31
downto
0
);
end
record
;
constant
c_lbk_in_registers_init_value
:
t_lbk_in_registers
:
=
(
dmac_l_i
=>
(
others
=>
'0'
),
dmac_h_i
=>
(
others
=>
'0'
),
rcv_cnt_i
=>
(
others
=>
'0'
),
drp_cnt_i
=>
(
others
=>
'0'
),
fwd_cnt_i
=>
(
others
=>
'0'
)
);
-- Output registers (WB slave -> user design)
type
t_lbk_out_registers
is
record
mcr_ena_o
:
std_logic
;
mcr_clr_o
:
std_logic
;
mcr_fdmac_o
:
std_logic
;
dmac_l_o
:
std_logic_vector
(
31
downto
0
);
dmac_l_load_o
:
std_logic
;
dmac_h_o
:
std_logic_vector
(
15
downto
0
);
dmac_h_load_o
:
std_logic
;
rcv_cnt_o
:
std_logic_vector
(
31
downto
0
);
rcv_cnt_load_o
:
std_logic
;
drp_cnt_o
:
std_logic_vector
(
31
downto
0
);
drp_cnt_load_o
:
std_logic
;
fwd_cnt_o
:
std_logic_vector
(
31
downto
0
);
fwd_cnt_load_o
:
std_logic
;
end
record
;
constant
c_lbk_out_registers_init_value
:
t_lbk_out_registers
:
=
(
mcr_ena_o
=>
'0'
,
mcr_clr_o
=>
'0'
,
mcr_fdmac_o
=>
'0'
,
dmac_l_o
=>
(
others
=>
'0'
),
dmac_l_load_o
=>
'0'
,
dmac_h_o
=>
(
others
=>
'0'
),
dmac_h_load_o
=>
'0'
,
rcv_cnt_o
=>
(
others
=>
'0'
),
rcv_cnt_load_o
=>
'0'
,
drp_cnt_o
=>
(
others
=>
'0'
),
drp_cnt_load_o
=>
'0'
,
fwd_cnt_o
=>
(
others
=>
'0'
),
fwd_cnt_load_o
=>
'0'
);
function
"or"
(
left
,
right
:
t_lbk_in_registers
)
return
t_lbk_in_registers
;
function
f_x_to_zero
(
x
:
std_logic
)
return
std_logic
;
function
f_x_to_zero
(
x
:
std_logic_vector
)
return
std_logic_vector
;
end
package
;
package
body
lbk_wbgen2_pkg
is
function
f_x_to_zero
(
x
:
std_logic
)
return
std_logic
is
begin
if
x
=
'1'
then
return
'1'
;
else
return
'0'
;
end
if
;
end
function
;
function
f_x_to_zero
(
x
:
std_logic_vector
)
return
std_logic_vector
is
variable
tmp
:
std_logic_vector
(
x
'length
-1
downto
0
);
begin
for
i
in
0
to
x
'length
-1
loop
if
x
(
i
)
=
'1'
then
tmp
(
i
):
=
'1'
;
else
tmp
(
i
):
=
'0'
;
end
if
;
end
loop
;
return
tmp
;
end
function
;
function
"or"
(
left
,
right
:
t_lbk_in_registers
)
return
t_lbk_in_registers
is
variable
tmp
:
t_lbk_in_registers
;
begin
tmp
.
dmac_l_i
:
=
f_x_to_zero
(
left
.
dmac_l_i
)
or
f_x_to_zero
(
right
.
dmac_l_i
);
tmp
.
dmac_h_i
:
=
f_x_to_zero
(
left
.
dmac_h_i
)
or
f_x_to_zero
(
right
.
dmac_h_i
);
tmp
.
rcv_cnt_i
:
=
f_x_to_zero
(
left
.
rcv_cnt_i
)
or
f_x_to_zero
(
right
.
rcv_cnt_i
);
tmp
.
drp_cnt_i
:
=
f_x_to_zero
(
left
.
drp_cnt_i
)
or
f_x_to_zero
(
right
.
drp_cnt_i
);
tmp
.
fwd_cnt_i
:
=
f_x_to_zero
(
left
.
fwd_cnt_i
)
or
f_x_to_zero
(
right
.
fwd_cnt_i
);
return
tmp
;
end
function
;
end
package
body
;
modules/fabric/xwrf_loopback/lbk_wishbone.wb
0 → 100644
View file @
9fdb9f5b
peripheral {
name = "WRF Loopback";
hdl_entity = "lbk_wishbone_controller";
prefix = "lbk";
reg {
name = "Main Control Register";
prefix = "MCR";
field {
name = "Enable Loopback";
prefix = "ENA";
access_bus = READ_WRITE;
access_dev = READ_ONLY;
type = BIT;
};
field {
name = "Clear counters";
prefix = "CLR";
type = MONOSTABLE;
};
field {
name = "Force DMAC";
prefix = "FDMAC";
access_bus = READ_WRITE;
access_dev = READ_ONLY;
type = BIT;
};
};
reg {
name = "Forced Destination MAC [3:0]";
prefix = "DMAC_L";
field {
name = "MAC";
access_bus = READ_WRITE;
access_dev = READ_WRITE;
type = SLV;
load = LOAD_EXT;
size = 32;
};
};
reg {
name = "Forced Destination MAC [5:4]";
prefix = "DMAC_H";
field {
name = "MAC";
access_bus = READ_WRITE;
access_dev = READ_WRITE;
type = SLV;
load = LOAD_EXT;
size = 16;
};
};
reg {
name = "Received frames counter";
prefix = "RCV_CNT";
field {
name = "Value";
access_bus = READ_WRITE;
access_dev = READ_WRITE;
type = SLV;
load = LOAD_EXT;
size = 32;
};
};
reg {
name = "Dropped frames counter";
prefix = "DRP_CNT";
field {
name = "Value";
access_bus = READ_WRITE;
access_dev = READ_WRITE;
type = SLV;
load = LOAD_EXT;
size = 32;
};
};
reg {
name = "Forwarded frames counter";
prefix = "FWD_CNT";
field {
name = "Value";
access_bus = READ_WRITE;
access_dev = READ_WRITE;
type = SLV;
load = LOAD_EXT;
size = 32;
};
};
}
modules/fabric/xwrf_loopback/lbk_wishbone_controller.vhd
0 → 100644
View file @
9fdb9f5b
---------------------------------------------------------------------------------------
-- Title : Wishbone slave core for WRF Loopback
---------------------------------------------------------------------------------------
-- File : lbk_wishbone_controller.vhd
-- Author : auto-generated by wbgen2 from lbk_wishbone.wb
-- Created : Wed Oct 28 15:10:33 2015
-- Standard : VHDL'87
---------------------------------------------------------------------------------------
-- THIS FILE WAS GENERATED BY wbgen2 FROM SOURCE FILE lbk_wishbone.wb
-- DO NOT HAND-EDIT UNLESS IT'S ABSOLUTELY NECESSARY!
---------------------------------------------------------------------------------------
library
ieee
;
use
ieee
.
std_logic_1164
.
all
;
use
ieee
.
numeric_std
.
all
;
use
work
.
lbk_wbgen2_pkg
.
all
;
entity
lbk_wishbone_controller
is
port
(
rst_n_i
:
in
std_logic
;
clk_sys_i
:
in
std_logic
;
wb_adr_i
:
in
std_logic_vector
(
2
downto
0
);
wb_dat_i
:
in
std_logic_vector
(
31
downto
0
);
wb_dat_o
:
out
std_logic_vector
(
31
downto
0
);
wb_cyc_i
:
in
std_logic
;
wb_sel_i
:
in
std_logic_vector
(
3
downto
0
);
wb_stb_i
:
in
std_logic
;
wb_we_i
:
in
std_logic
;
wb_ack_o
:
out
std_logic
;
wb_stall_o
:
out
std_logic
;
regs_i
:
in
t_lbk_in_registers
;
regs_o
:
out
t_lbk_out_registers
);
end
lbk_wishbone_controller
;
architecture
syn
of
lbk_wishbone_controller
is
signal
lbk_mcr_ena_int
:
std_logic
;
signal
lbk_mcr_clr_dly0
:
std_logic
;
signal
lbk_mcr_clr_int
:
std_logic
;
signal
lbk_mcr_fdmac_int
:
std_logic
;
signal
ack_sreg
:
std_logic_vector
(
9
downto
0
);
signal
rddata_reg
:
std_logic_vector
(
31
downto
0
);
signal
wrdata_reg
:
std_logic_vector
(
31
downto
0
);
signal
bwsel_reg
:
std_logic_vector
(
3
downto
0
);
signal
rwaddr_reg
:
std_logic_vector
(
2
downto
0
);
signal
ack_in_progress
:
std_logic
;
signal
wr_int
:
std_logic
;
signal
rd_int
:
std_logic
;
signal
allones
:
std_logic_vector
(
31
downto
0
);
signal
allzeros
:
std_logic_vector
(
31
downto
0
);
begin
-- Some internal signals assignments. For (foreseen) compatibility with other bus standards.
wrdata_reg
<=
wb_dat_i
;
bwsel_reg
<=
wb_sel_i
;
rd_int
<=
wb_cyc_i
and
(
wb_stb_i
and
(
not
wb_we_i
));
wr_int
<=
wb_cyc_i
and
(
wb_stb_i
and
wb_we_i
);
allones
<=
(
others
=>
'1'
);
allzeros
<=
(
others
=>
'0'
);
--
-- Main register bank access process.
process
(
clk_sys_i
,
rst_n_i
)
begin
if
(
rst_n_i
=
'0'
)
then
ack_sreg
<=
"0000000000"
;
ack_in_progress
<=
'0'
;
rddata_reg
<=
"00000000000000000000000000000000"
;
lbk_mcr_ena_int
<=
'0'
;
lbk_mcr_clr_int
<=
'0'
;
lbk_mcr_fdmac_int
<=
'0'
;
regs_o
.
dmac_l_load_o
<=
'0'
;
regs_o
.
dmac_h_load_o
<=
'0'
;
regs_o
.
rcv_cnt_load_o
<=
'0'
;
regs_o
.
drp_cnt_load_o
<=
'0'
;
regs_o
.
fwd_cnt_load_o
<=
'0'
;
elsif
rising_edge
(
clk_sys_i
)
then
-- advance the ACK generator shift register
ack_sreg
(
8
downto
0
)
<=
ack_sreg
(
9
downto
1
);
ack_sreg
(
9
)
<=
'0'
;
if
(
ack_in_progress
=
'1'
)
then
if
(
ack_sreg
(
0
)
=
'1'
)
then
lbk_mcr_clr_int
<=
'0'
;
regs_o
.
dmac_l_load_o
<=
'0'
;
regs_o
.
dmac_h_load_o
<=
'0'
;
regs_o
.
rcv_cnt_load_o
<=
'0'
;
regs_o
.
drp_cnt_load_o
<=
'0'
;
regs_o
.
fwd_cnt_load_o
<=
'0'
;
ack_in_progress
<=
'0'
;
else
regs_o
.
dmac_l_load_o
<=
'0'
;
regs_o
.
dmac_h_load_o
<=
'0'
;
regs_o
.
rcv_cnt_load_o
<=
'0'
;
regs_o
.
drp_cnt_load_o
<=
'0'
;
regs_o
.
fwd_cnt_load_o
<=
'0'
;
end
if
;
else
if
((
wb_cyc_i
=
'1'
)
and
(
wb_stb_i
=
'1'
))
then
case
rwaddr_reg
(
2
downto
0
)
is
when
"000"
=>
if
(
wb_we_i
=
'1'
)
then
lbk_mcr_ena_int
<=
wrdata_reg
(
0
);
lbk_mcr_clr_int
<=
wrdata_reg
(
1
);
lbk_mcr_fdmac_int
<=
wrdata_reg
(
2
);
end
if
;
rddata_reg
(
0
)
<=
lbk_mcr_ena_int
;
rddata_reg
(
1
)
<=
'0'
;
rddata_reg
(
2
)
<=
lbk_mcr_fdmac_int
;
rddata_reg
(
3
)
<=
'X'
;
rddata_reg
(
4
)
<=
'X'
;
rddata_reg
(
5
)
<=
'X'
;
rddata_reg
(
6
)
<=
'X'
;
rddata_reg
(
7
)
<=
'X'
;
rddata_reg
(
8
)
<=
'X'
;
rddata_reg
(
9
)
<=
'X'
;
rddata_reg
(
10
)
<=
'X'
;
rddata_reg
(
11
)
<=
'X'
;
rddata_reg
(
12
)
<=
'X'
;
rddata_reg
(
13
)
<=
'X'
;
rddata_reg
(
14
)
<=
'X'
;
rddata_reg
(
15
)
<=
'X'
;
rddata_reg
(
16
)
<=
'X'
;
rddata_reg
(
17
)
<=
'X'
;
rddata_reg
(
18
)
<=
'X'
;
rddata_reg
(
19
)
<=
'X'
;
rddata_reg
(
20
)
<=
'X'
;
rddata_reg
(
21
)
<=
'X'
;
rddata_reg
(
22
)
<=
'X'
;
rddata_reg
(
23
)
<=
'X'
;
rddata_reg
(
24
)
<=
'X'
;
rddata_reg
(
25
)
<=
'X'
;
rddata_reg
(
26
)
<=
'X'
;
rddata_reg
(
27
)
<=
'X'
;
rddata_reg
(
28
)
<=
'X'
;
rddata_reg
(
29
)
<=
'X'
;
rddata_reg
(
30
)
<=
'X'
;
rddata_reg
(
31
)
<=
'X'
;
ack_sreg
(
2
)
<=
'1'
;
ack_in_progress
<=
'1'
;
when
"001"
=>
if
(
wb_we_i
=
'1'
)
then
regs_o
.
dmac_l_load_o
<=
'1'
;
end
if
;
rddata_reg
(
31
downto
0
)
<=
regs_i
.
dmac_l_i
;
ack_sreg
(
0
)
<=
'1'
;
ack_in_progress
<=
'1'
;
when
"010"
=>
if
(
wb_we_i
=
'1'
)
then
regs_o
.
dmac_h_load_o
<=
'1'
;
end
if
;
rddata_reg
(
15
downto
0
)
<=
regs_i
.
dmac_h_i
;
rddata_reg
(
16
)
<=
'X'
;
rddata_reg
(
17
)
<=
'X'
;
rddata_reg
(
18
)
<=
'X'
;
rddata_reg
(
19
)
<=
'X'
;
rddata_reg
(
20
)
<=
'X'
;
rddata_reg
(
21
)
<=
'X'
;
rddata_reg
(
22
)
<=
'X'
;
rddata_reg
(
23
)
<=
'X'
;
rddata_reg
(
24
)
<=
'X'
;
rddata_reg
(
25
)
<=
'X'
;
rddata_reg
(
26
)
<=
'X'
;
rddata_reg
(
27
)
<=
'X'
;
rddata_reg
(
28
)
<=
'X'
;
rddata_reg
(
29
)
<=
'X'
;
rddata_reg
(
30
)
<=
'X'
;
rddata_reg
(
31
)
<=
'X'
;
ack_sreg
(
0
)
<=
'1'
;
ack_in_progress
<=
'1'
;
when
"011"
=>
if
(
wb_we_i
=
'1'
)
then
regs_o
.
rcv_cnt_load_o
<=
'1'
;
end
if
;
rddata_reg
(
31
downto
0
)
<=
regs_i
.
rcv_cnt_i
;
ack_sreg
(
0
)
<=
'1'
;
ack_in_progress
<=
'1'
;
when
"100"
=>
if
(
wb_we_i
=
'1'
)
then
regs_o
.
drp_cnt_load_o
<=
'1'
;
end
if
;
rddata_reg
(
31
downto
0
)
<=
regs_i
.
drp_cnt_i
;
ack_sreg
(
0
)
<=
'1'
;
ack_in_progress
<=
'1'
;
when
"101"
=>
if
(
wb_we_i
=
'1'
)
then
regs_o
.
fwd_cnt_load_o
<=
'1'
;
end
if
;
rddata_reg
(
31
downto
0
)
<=
regs_i
.
fwd_cnt_i
;
ack_sreg
(
0
)
<=
'1'
;
ack_in_progress
<=
'1'
;
when
others
=>
-- prevent the slave from hanging the bus on invalid address
ack_in_progress
<=
'1'
;
ack_sreg
(
0
)
<=
'1'
;
end
case
;
end
if
;
end
if
;
end
if
;
end
process
;
-- Drive the data output bus
wb_dat_o
<=
rddata_reg
;
-- Enable Loopback
regs_o
.
mcr_ena_o
<=
lbk_mcr_ena_int
;
-- Clear counters
process
(
clk_sys_i
,
rst_n_i
)
begin
if
(
rst_n_i
=
'0'
)
then
lbk_mcr_clr_dly0
<=
'0'
;
regs_o
.
mcr_clr_o
<=
'0'
;
elsif
rising_edge
(
clk_sys_i
)
then
lbk_mcr_clr_dly0
<=
lbk_mcr_clr_int
;
regs_o
.
mcr_clr_o
<=
lbk_mcr_clr_int
and
(
not
lbk_mcr_clr_dly0
);
end
if
;
end
process
;
-- Force DMAC
regs_o
.
mcr_fdmac_o
<=
lbk_mcr_fdmac_int
;
-- MAC
regs_o
.
dmac_l_o
<=
wrdata_reg
(
31
downto
0
);
-- MAC
regs_o
.
dmac_h_o
<=
wrdata_reg
(
15
downto
0
);
-- Value
regs_o
.
rcv_cnt_o
<=
wrdata_reg
(
31
downto
0
);
-- Value
regs_o
.
drp_cnt_o
<=
wrdata_reg
(
31
downto
0
);
-- Value
regs_o
.
fwd_cnt_o
<=
wrdata_reg
(
31
downto
0
);
rwaddr_reg
<=
wb_adr_i
;
wb_stall_o
<=
(
not
ack_sreg
(
0
))
and
(
wb_stb_i
and
wb_cyc_i
);
-- ACK signal generation. Just pass the LSB of ACK counter.
wb_ack_o
<=
ack_sreg
(
0
);
end
syn
;
modules/fabric/xwrf_loopback/wrf_loopback.vhd
0 → 100644
View file @
9fdb9f5b
library
ieee
;
use
ieee
.
std_logic_1164
.
all
;
use
work
.
wishbone_pkg
.
all
;
use
work
.
wr_fabric_pkg
.
all
;
entity
wrf_loopback
is
generic
(
g_interface_mode
:
t_wishbone_interface_mode
:
=
CLASSIC
;
g_address_granularity
:
t_wishbone_address_granularity
:
=
WORD
);
port
(
clk_sys_i
:
in
std_logic
;
rst_n_i
:
in
std_logic
;
snk_cyc_i
:
in
std_logic
;
snk_stb_i
:
in
std_logic
;
snk_we_i
:
in
std_logic
;
snk_sel_i
:
in
std_logic_vector
(
1
downto
0
);
snk_adr_i
:
in
std_logic_vector
(
1
downto
0
);
snk_dat_i
:
in
std_logic_vector
(
15
downto
0
);
snk_ack_o
:
out
std_logic
;
snk_stall_o
:
out
std_logic
;
src_cyc_o
:
out
std_logic
;
src_stb_o
:
out
std_logic
;
src_we_o
:
out
std_logic
;
src_sel_o
:
out
std_logic_vector
(
1
downto
0
);
src_adr_o
:
out
std_logic_vector
(
1
downto
0
);
src_dat_o
:
out
std_logic_vector
(
15
downto
0
);
src_ack_i
:
in
std_logic
;
src_stall_i
:
in
std_logic
;
wb_cyc_i
:
in
std_logic
;
wb_stb_i
:
in
std_logic
;
wb_we_i
:
in
std_logic
;
wb_sel_i
:
in
std_logic_vector
(
3
downto
0
);
wb_adr_i
:
in
std_logic_vector
(
31
downto
0
);
wb_dat_i
:
in
std_logic_vector
(
31
downto
0
);
wb_dat_o
:
out
std_logic_vector
(
31
downto
0
);
wb_ack_o
:
out
std_logic
;
wb_stall_o
:
out
std_logic
);
end
wrf_loopback
;
architecture
behav
of
wrf_loopback
is
component
xwrf_loopback
generic
(
g_interface_mode
:
t_wishbone_interface_mode
:
=
CLASSIC
;
g_address_granularity
:
t_wishbone_address_granularity
:
=
WORD
);
port
(
clk_sys_i
:
in
std_logic
;
rst_n_i
:
in
std_logic
;
wrf_snk_i
:
in
t_wrf_sink_in
;
wrf_snk_o
:
out
t_wrf_sink_out
;
wrf_src_o
:
out
t_wrf_source_out
;
wrf_src_i
:
in
t_wrf_source_in
;
wb_i
:
in
t_wishbone_slave_in
;
wb_o
:
out
t_wishbone_slave_out
);
end
component
;
signal
snk_in
:
t_wrf_sink_in
;
signal
snk_out
:
t_wrf_sink_out
;
signal
src_in
:
t_wrf_source_in
;
signal
src_out
:
t_wrf_source_out
;
signal
wb_in
:
t_wishbone_slave_in
;
signal
wb_out
:
t_wishbone_slave_out
;
begin
X_LOOPBACK
:
xwrf_loopback
generic
map
(
g_interface_mode
=>
g_interface_mode
,
g_address_granularity
=>
g_address_granularity
)
port
map
(
clk_sys_i
=>
clk_sys_i
,
rst_n_i
=>
rst_n_i
,
wrf_snk_i
=>
snk_in
,
wrf_snk_o
=>
snk_out
,
wrf_src_o
=>
src_out
,
wrf_src_i
=>
src_in
,
wb_i
=>
wb_in
,
wb_o
=>
wb_out
);
snk_in
.
cyc
<=
snk_cyc_i
;
snk_in
.
stb
<=
snk_stb_i
;
snk_in
.
we
<=
snk_we_i
;
snk_in
.
sel
<=
snk_sel_i
;
snk_in
.
adr
<=
snk_adr_i
;
snk_in
.
dat
<=
snk_dat_i
;
snk_ack_o
<=
snk_out
.
ack
;
snk_stall_o
<=
snk_out
.
stall
;
src_cyc_o
<=
src_out
.
cyc
;
src_stb_o
<=
src_out
.
stb
;
src_we_o
<=
src_out
.
we
;
src_sel_o
<=
src_out
.
sel
;
src_adr_o
<=
src_out
.
adr
;
src_dat_o
<=
src_out
.
dat
;
src_in
.
ack
<=
src_ack_i
;
src_in
.
stall
<=
src_stall_i
;
src_in
.
err
<=
'0'
;
src_in
.
rty
<=
'0'
;
wb_in
.
cyc
<=
wb_cyc_i
;
wb_in
.
stb
<=
wb_stb_i
;
wb_in
.
we
<=
wb_we_i
;
wb_in
.
sel
<=
wb_sel_i
;
wb_in
.
adr
<=
wb_adr_i
;
wb_in
.
dat
<=
wb_dat_i
;
wb_dat_o
<=
wb_out
.
dat
;
wb_ack_o
<=
wb_out
.
ack
;
wb_stall_o
<=
wb_out
.
stall
;
end
behav
;
modules/fabric/xwrf_loopback/xwrf_loopback.vhd
0 → 100644
View file @
9fdb9f5b
library
ieee
;
use
ieee
.
std_logic_1164
.
all
;
use
ieee
.
numeric_std
.
all
;
use
work
.
wr_fabric_pkg
.
all
;
use
work
.
wishbone_pkg
.
all
;
use
work
.
genram_pkg
.
all
;
use
work
.
lbk_wbgen2_pkg
.
all
;
use
work
.
endpoint_pkg
.
all
;
use
work
.
endpoint_private_pkg
.
all
;
entity
xwrf_loopback
is
generic
(
g_interface_mode
:
t_wishbone_interface_mode
:
=
CLASSIC
;
g_address_granularity
:
t_wishbone_address_granularity
:
=
WORD
);
port
(
clk_sys_i
:
in
std_logic
;
rst_n_i
:
in
std_logic
;
wrf_snk_i
:
in
t_wrf_sink_in
;
wrf_snk_o
:
out
t_wrf_sink_out
;
wrf_src_o
:
out
t_wrf_source_out
;
wrf_src_i
:
in
t_wrf_source_in
;
wb_i
:
in
t_wishbone_slave_in
;
wb_o
:
out
t_wishbone_slave_out
);
end
xwrf_loopback
;
architecture
behav
of
xwrf_loopback
is
component
lbk_wishbone_controller
port
(
rst_n_i
:
in
std_logic
;
clk_sys_i
:
in
std_logic
;
wb_adr_i
:
in
std_logic_vector
(
2
downto
0
);
wb_dat_i
:
in
std_logic_vector
(
31
downto
0
);
wb_dat_o
:
out
std_logic_vector
(
31
downto
0
);
wb_cyc_i
:
in
std_logic
;
wb_sel_i
:
in
std_logic_vector
(
3
downto
0
);
wb_stb_i
:
in
std_logic
;
wb_we_i
:
in
std_logic
;
wb_ack_o
:
out
std_logic
;
wb_stall_o
:
out
std_logic
;
regs_i
:
in
t_lbk_in_registers
;
regs_o
:
out
t_lbk_out_registers
);
end
component
;
signal
regs_fromwb
:
t_lbk_out_registers
;
signal
regs_towb
:
t_lbk_in_registers
;
signal
wb_out
:
t_wishbone_slave_out
;
signal
wb_in
:
t_wishbone_slave_in
;
type
t_lbk_rxfsm
is
(
IDLE
,
PAYLOAD
,
DROP
,
FEND
);
signal
lbk_rxfsm
:
t_lbk_rxfsm
;
type
t_lbk_txfsm
is
(
IDLE
,
GET_SIZE
,
PAYLOAD
,
EOF
);
signal
lbk_txfsm
:
t_lbk_txfsm
;
signal
rcv_cnt
:
unsigned
(
31
downto
0
);
signal
drp_cnt
:
unsigned
(
31
downto
0
);
signal
fwd_cnt
:
unsigned
(
31
downto
0
);
signal
fsize
:
unsigned
(
15
downto
0
);
signal
txsize
:
unsigned
(
15
downto
0
);
signal
tx_cnt
:
unsigned
(
3
downto
0
);
signal
rcv_cnt_inc
:
std_logic
;
signal
drp_cnt_inc
:
std_logic
;
signal
fwd_cnt_inc
:
std_logic
;
signal
frame_in
:
std_logic_vector
(
15
downto
0
);
signal
frame_out
:
std_logic_vector
(
15
downto
0
);
signal
frame_wr
:
std_logic
;
signal
frame_rd
:
std_logic
;
signal
ffifo_full
:
std_logic
;
signal
sfifo_empty
:
std_logic
;
signal
sfifo_full
:
std_logic
;
signal
fsize_in
:
std_logic_vector
(
15
downto
0
);
signal
fsize_out
:
std_logic_vector
(
15
downto
0
);
signal
fsize_wr
:
std_logic
;
signal
fsize_rd
:
std_logic
;
signal
fword_valid
:
std_logic
;
type
t_mac_array
is
array
(
natural
range
<>
)
of
std_logic_vector
(
15
downto
0
);
signal
forced_dmac
:
t_mac_array
(
2
downto
0
);
signal
src_fab
:
t_ep_internal_fabric
;
signal
src_dreq
:
std_logic
;
begin
-------------------------------------------
-- Standard Wishbone stuff
-------------------------------------------
U_Slave_adapter
:
wb_slave_adapter
generic
map
(
g_master_use_struct
=>
true
,
g_master_mode
=>
CLASSIC
,
g_master_granularity
=>
WORD
,
g_slave_use_struct
=>
true
,
g_slave_mode
=>
g_interface_mode
,
g_slave_granularity
=>
g_address_granularity
)
port
map
(
clk_sys_i
=>
clk_sys_i
,
rst_n_i
=>
rst_n_i
,
slave_i
=>
wb_i
,
slave_o
=>
wb_o
,
master_i
=>
wb_out
,
master_o
=>
wb_in
);
U_WB_SLAVE
:
lbk_wishbone_controller
port
map
(
rst_n_i
=>
rst_n_i
,
clk_sys_i
=>
clk_sys_i
,
wb_adr_i
=>
wb_in
.
adr
(
2
downto
0
),
wb_dat_i
=>
wb_in
.
dat
,
wb_dat_o
=>
wb_out
.
dat
,
wb_cyc_i
=>
wb_in
.
cyc
,
wb_sel_i
=>
wb_in
.
sel
,
wb_stb_i
=>
wb_in
.
stb
,
wb_we_i
=>
wb_in
.
we
,
wb_ack_o
=>
wb_out
.
ack
,
wb_stall_o
=>
wb_out
.
stall
,
regs_i
=>
regs_towb
,
regs_o
=>
regs_fromwb
);
wb_out
.
rty
<=
'0'
;
wb_out
.
err
<=
'0'
;
wb_out
.
int
<=
'0'
;
-------------------------------------------
FRAME_FIFO
:
generic_sync_fifo
generic
map
(
g_data_width
=>
16
,
g_size
=>
2048
,
g_with_empty
=>
true
,
g_with_full
=>
true
,
g_with_almost_empty
=>
false
,
g_with_almost_full
=>
false
,
g_with_count
=>
true
)
port
map
(
rst_n_i
=>
rst_n_i
,
clk_i
=>
clk_sys_i
,
d_i
=>
frame_in
,
we_i
=>
frame_wr
,
q_o
=>
frame_out
,
rd_i
=>
frame_rd
,
empty_o
=>
open
,
full_o
=>
ffifo_full
);
SIZE_FIFO
:
generic_sync_fifo
generic
map
(
g_data_width
=>
16
,
g_size
=>
8
,
g_show_ahead
=>
true
,
g_with_empty
=>
true
,
g_with_full
=>
true
,
g_with_almost_empty
=>
false
,
g_with_almost_full
=>
false
,
g_with_count
=>
true
)
port
map
(
rst_n_i
=>
rst_n_i
,
clk_i
=>
clk_sys_i
,
d_i
=>
fsize_in
,
we_i
=>
fsize_wr
,
q_o
=>
fsize_out
,
rd_i
=>
fsize_rd
,
empty_o
=>
sfifo_empty
,
full_o
=>
sfifo_full
);
-------------------------------------------
-- Counters
-------------------------------------------
regs_towb
.
rcv_cnt_i
<=
std_logic_vector
(
rcv_cnt
);
regs_towb
.
drp_cnt_i
<=
std_logic_vector
(
drp_cnt
);
regs_towb
.
fwd_cnt_i
<=
std_logic_vector
(
fwd_cnt
);
process
(
clk_sys_i
)
begin
if
rising_edge
(
clk_sys_i
)
then
if
(
rst_n_i
=
'0'
or
regs_fromwb
.
rcv_cnt_load_o
=
'1'
or
regs_fromwb
.
mcr_clr_o
=
'1'
)
then
rcv_cnt
<=
(
others
=>
'0'
);
elsif
(
rcv_cnt_inc
=
'1'
)
then
rcv_cnt
<=
rcv_cnt
+
1
;
end
if
;
end
if
;
end
process
;
process
(
clk_sys_i
)
begin
if
rising_edge
(
clk_sys_i
)
then
if
(
rst_n_i
=
'0'
or
regs_fromwb
.
drp_cnt_load_o
=
'1'
or
regs_fromwb
.
mcr_clr_o
=
'1'
)
then
drp_cnt
<=
(
others
=>
'0'
);
elsif
(
drp_cnt_inc
=
'1'
)
then
drp_cnt
<=
drp_cnt
+
1
;
end
if
;
end
if
;
end
process
;
process
(
clk_sys_i
)
begin
if
rising_edge
(
clk_sys_i
)
then
if
(
rst_n_i
=
'0'
or
regs_fromwb
.
fwd_cnt_load_o
=
'1'
or
regs_fromwb
.
mcr_clr_o
=
'1'
)
then
fwd_cnt
<=
(
others
=>
'0'
);
elsif
(
fwd_cnt_inc
=
'1'
)
then
fwd_cnt
<=
fwd_cnt
+
1
;
end
if
;
end
if
;
end
process
;
process
(
clk_sys_i
)
begin
if
rising_edge
(
clk_sys_i
)
then
if
(
rst_n_i
=
'0'
)
then
forced_dmac
(
0
)
<=
(
others
=>
'0'
);
forced_dmac
(
1
)
<=
(
others
=>
'0'
);
forced_dmac
(
2
)
<=
(
others
=>
'0'
);
else
if
(
regs_fromwb
.
dmac_h_load_o
=
'1'
)
then
forced_dmac
(
0
)
<=
regs_fromwb
.
dmac_h_o
;
end
if
;
if
(
regs_fromwb
.
dmac_l_load_o
=
'1'
)
then
forced_dmac
(
1
)
<=
regs_fromwb
.
dmac_l_o
(
31
downto
16
);
forced_dmac
(
2
)
<=
regs_fromwb
.
dmac_l_o
(
15
downto
0
);
end
if
;
end
if
;
end
if
;
end
process
;
regs_towb
.
dmac_h_i
<=
forced_dmac
(
0
);
regs_towb
.
dmac_l_i
<=
forced_dmac
(
1
)
&
forced_dmac
(
2
);
-------------------------------------------
-- RX FSM
-------------------------------------------
fword_valid
<=
'1'
when
(
wrf_snk_i
.
cyc
=
'1'
and
wrf_snk_i
.
stb
=
'1'
and
wrf_snk_i
.
adr
=
c_WRF_DATA
)
else
'0'
;
process
(
clk_sys_i
)
begin
if
rising_edge
(
clk_sys_i
)
then
if
(
rst_n_i
=
'0'
)
then
fsize
<=
(
others
=>
'0'
);
lbk_rxfsm
<=
IDLE
;
else
frame_wr
<=
'0'
;
fsize_wr
<=
'0'
;
drp_cnt_inc
<=
'0'
;
rcv_cnt_inc
<=
'0'
;
if
(
fword_valid
=
'1'
)
then
wrf_snk_o
.
ack
<=
'1'
;
else
wrf_snk_o
.
ack
<=
'0'
;
end
if
;
case
lbk_rxfsm
is
when
IDLE
=>
if
(
regs_fromwb
.
mcr_ena_o
=
'1'
and
wrf_snk_i
.
cyc
=
'1'
and
ffifo_full
=
'0'
and
sfifo_full
=
'0'
)
then
lbk_rxfsm
<=
PAYLOAD
;
elsif
(
regs_fromwb
.
mcr_ena_o
=
'1'
and
wrf_snk_i
.
cyc
=
'1'
)
then
drp_cnt_inc
<=
'1'
;
lbk_rxfsm
<=
DROP
;
end
if
;
when
PAYLOAD
=>
if
(
fword_valid
=
'1'
and
wrf_snk_i
.
sel
=
"11"
and
ffifo_full
=
'0'
)
then
fsize
<=
fsize
+
2
;
elsif
(
fword_valid
=
'1'
and
wrf_snk_i
.
sel
=
"10"
and
ffifo_full
=
'0'
)
then
fsize
<=
fsize
+
1
;
end
if
;
if
(
fsize
>
4
and
fword_valid
=
'1'
and
ffifo_full
=
'0'
)
then
-- because we don't store DMAC
frame_wr
<=
'1'
;
frame_in
<=
wrf_snk_i
.
dat
;
elsif
(
fsize
>
4
and
fword_valid
=
'1'
and
ffifo_full
=
'1'
)
then
fsize
<=
fsize
-2
;
--last write was already unsuccesfull lbk_rxfsm <= DROP; end if;
lbk_rxfsm
<=
DROP
;
end
if
;
if
(
wrf_snk_i
.
cyc
=
'0'
)
then
lbk_rxfsm
<=
FEND
;
end
if
;
when
DROP
=>
if
(
wrf_snk_i
.
cyc
=
'0'
)
then
--fsize <= (others=>'0');
lbk_rxfsm
<=
FEND
;
end
if
;
when
FEND
=>
if
(
fsize
>
4
)
then
fsize_wr
<=
'1'
;
fsize_in
<=
std_logic_vector
(
fsize
);
rcv_cnt_inc
<=
'1'
;
fsize
<=
(
others
=>
'0'
);
end
if
;
lbk_rxfsm
<=
IDLE
;
end
case
;
end
if
;
end
if
;
end
process
;
wrf_snk_o
.
stall
<=
'0'
;
wrf_snk_o
.
rty
<=
'0'
;
wrf_snk_o
.
err
<=
'0'
;
-------------------------------------------
-- TX FSM
-------------------------------------------
WRF_SRC
:
ep_rx_wb_master
generic
map
(
g_ignore_ack
=>
false
,
g_cyc_on_stall
=>
true
)
port
map
(
clk_sys_i
=>
clk_sys_i
,
rst_n_i
=>
rst_n_i
,
snk_fab_i
=>
src_fab
,
snk_dreq_o
=>
src_dreq
,
src_wb_i
=>
wrf_src_i
,
src_wb_o
=>
wrf_src_o
);
src_fab
.
has_rx_timestamp
<=
'0'
;
src_fab
.
rx_timestamp_valid
<=
'0'
;
src_fab
.
error
<=
'0'
;
src_fab
.
data
<=
forced_dmac
(
0
)
when
(
regs_fromwb
.
mcr_fdmac_o
=
'1'
and
tx_cnt
=
1
)
else
forced_dmac
(
1
)
when
(
regs_fromwb
.
mcr_fdmac_o
=
'1'
and
tx_cnt
=
2
)
else
forced_dmac
(
2
)
when
(
regs_fromwb
.
mcr_fdmac_o
=
'1'
and
tx_cnt
=
3
)
else
frame_out
;
src_fab
.
addr
<=
c_WRF_DATA
;
process
(
clk_sys_i
)
begin
if
rising_edge
(
clk_sys_i
)
then
if
(
rst_n_i
=
'0'
)
then
lbk_txfsm
<=
IDLE
;
txsize
<=
(
others
=>
'0'
);
fsize_rd
<=
'0'
;
frame_rd
<=
'0'
;
fwd_cnt_inc
<=
'0'
;
else
fsize_rd
<=
'0'
;
frame_rd
<=
'0'
;
fwd_cnt_inc
<=
'0'
;
src_fab
.
sof
<=
'0'
;
src_fab
.
eof
<=
'0'
;
src_fab
.
dvalid
<=
'0'
;
case
lbk_txfsm
is
when
IDLE
=>
txsize
<=
(
others
=>
'0'
);
tx_cnt
<=
(
others
=>
'0'
);
src_fab
.
bytesel
<=
'0'
;
if
(
sfifo_empty
=
'0'
and
src_dreq
=
'1'
)
then
lbk_txfsm
<=
GET_SIZE
;
fsize_rd
<=
'1'
;
end
if
;
when
GET_SIZE
=>
txsize
<=
unsigned
(
fsize_out
);
tx_cnt
<=
(
others
=>
'0'
);
if
(
src_dreq
=
'1'
)
then
src_fab
.
sof
<=
'1'
;
frame_rd
<=
'1'
;
lbk_txfsm
<=
PAYLOAD
;
end
if
;
when
PAYLOAD
=>
if
(
src_dreq
=
'1'
and
txsize
>
1
)
then
txsize
<=
txsize
-
2
;
src_fab
.
bytesel
<=
'0'
;
elsif
(
src_dreq
=
'1'
and
txsize
=
1
)
then
txsize
<=
txsize
-
1
;
src_fab
.
bytesel
<=
'1'
;
end
if
;
--tx_cnt used only for ETH header counting words
if
(
src_dreq
=
'1'
and
tx_cnt
<
15
)
then
tx_cnt
<=
tx_cnt
+
1
;
end
if
;
if
(
src_dreq
=
'1'
and
(
tx_cnt
<
3
or
tx_cnt
>
5
)
and
txsize
>
2
)
then
frame_rd
<=
'1'
;
src_fab
.
dvalid
<=
'1'
;
elsif
(
(
src_dreq
=
'1'
and
tx_cnt
>=
3
and
tx_cnt
<=
5
)
or
(
src_dreq
=
'1'
and
tx_cnt
>
5
and
txsize
<=
2
)
)
then
src_fab
.
dvalid
<=
'1'
;
end
if
;
if
(
txsize
<=
2
and
src_dreq
=
'1'
)
then
lbk_txfsm
<=
EOF
;
end
if
;
when
EOF
=>
if
(
src_dreq
=
'1'
)
then
src_fab
.
eof
<=
'1'
;
fwd_cnt_inc
<=
'1'
;
lbk_txfsm
<=
IDLE
;
end
if
;
end
case
;
end
if
;
end
if
;
end
process
;
end
behav
;
sim/lbk_regs.v
0 → 100644
View file @
9fdb9f5b
`define
ADDR_LBK_MCR
5'h0
`define
LBK_MCR_ENA_OFFSET 0
`define
LBK_MCR_ENA 32
'
h00000001
`define
LBK_MCR_CLR_OFFSET 1
`define
LBK_MCR_CLR 32
'
h00000002
`define
LBK_MCR_FDMAC_OFFSET 2
`define
LBK_MCR_FDMAC 32
'
h00000004
`define
ADDR_LBK_DMAC_L 5
'
h4
`define
ADDR_LBK_DMAC_H 5
'
h8
`define
ADDR_LBK_RCV_CNT 5
'
hc
`define
ADDR_LBK_DRP_CNT 5
'
h10
`define
ADDR_LBK_FWD_CNT 5
'
h14
testbench/xwrf_loopback/Manifest.py
0 → 100644
View file @
9fdb9f5b
action
=
"simulation"
target
=
"xilinx"
fetchto
=
"../../ip_cores"
vlog_opt
=
"+incdir+../../sim"
files
=
[
"main.sv"
]
modules
=
{
"local"
:
[
"../.."
,
"../../modules/fabric"
,
"../../ip_cores/general-cores"
,
"../../ip_cores/etherbone-core"
,
"../../ip_cores/gn4124-core"
]}
testbench/xwrf_loopback/functions.svh
0 → 100644
View file @
9fdb9f5b
`define
WIRE_VHD_SV_WRFSRC
(
vhd_dst
,
sv_src
)
\
assign
vhd_dst
`
`_i
.
cyc
=
sv_src
.
cyc
;
\
assign
vhd_dst
`
`_i
.
stb
=
sv_src
.
stb
;
\
assign
vhd_dst
`
`_i
.
adr
=
sv_src
.
adr
;
\
assign
vhd_dst
`
`_i
.
dat
=
sv_src
.
dat_o
;
\
assign
vhd_dst
`
`_i
.
sel
=
sv_src
.
sel
;
\
assign
vhd_dst
`
`_i
.
we
=
sv_src
.
we
;
\
assign
sv_src
.
ack
=
vhd_dst
`
`_o
.
ack
;
\
assign
sv_src
.
err
=
vhd_dst
`
`_o
.
err
;
\
assign
sv_src
.
stall
=
vhd_dst
`
`_o
.
stall
;
`define
WIRE_VHD_SV_WRFSNK
(
sv_dst
,
vhd_src
)
\
assign sv_dst
.
cyc
=
vhd_src
``
_o
.
cyc
;
\
assign sv_dst
.
stb
=
vhd_src
``
_o
.
stb
;
\
assign sv_dst
.
adr
=
vhd_src
``
_o
.
adr
;
\
assign sv_dst
.
dat_o
=
vhd_src
``
_o
.
dat
;
\
assign sv_dst
.
sel
=
vhd_src
``
_o
.
sel
;
\
assign sv_dst
.
we
=
vhd_src
``
_o
.
we
;
\
assign vhd_src
``
_i
.
ack
=
sv_dst
.
ack
;
\
assign vhd_src
``
_i
.
err
=
sv_dst
.
err
;
\
assign vhd_src
``
_i
.
stall
=
sv_dst
.
stall
;
`define
WIRE_VHD_SV_WBM
(
vhd_dst
,
sv_src
)
\
assign vhd_dst
``
_o
.
cyc
=
sv_src
.
cyc
;
\
assign vhd_dst
``
_o
.
stb
=
sv_src
.
stb
;
\
assign vhd_dst
``
_o
.
adr
=
sv_src
.
adr
;
\
assign vhd_dst
``
_o
.
dat
=
sv_src
.
dat_o
;
\
assign vhd_dst
``
_o
.
sel
=
sv_src
.
sel
;
\
assign vhd_dst
``
_o
.
we
=
sv_src
.
we
;
\
assign sv_src
.
ack
=
vhd_dst
``
_i
.
ack
;
\
assign sv_src
.
err
=
vhd_dst
``
_i
.
err
;
\
assign sv_src
.
dat_i
=
vhd_dst
``
_i
.
dat
;
\
assign sv_src
.
stall
=
vhd_dst
``
_i
.
stall
;
int
tx_sizes
[$]
,
tx_padded
[$]
;
//////////////////////////////////////////////////////////
task
send_frames
(
WBPacketSource
src
,
int
n_packets
)
;
int
i
,
seed
=
0
,
n1
=
0
,
n2
=
0
;
int
cur_size
,
dir
;
EthPacket
pkt
,
tmpl
;
EthPacket
to_ext
[$]
,
to_minic
[$]
;
EthPacketGenerator
gen
=
new
;
tmpl
=
new
;
tmpl
.
src
=
'
{
22
,
33
,
44
,
44
,
55
,
66
};
tmpl
.
dst
=
'
{
'hff
,
'hff
,
'hff
,
'hff
,
'hff
,
'hff
};
//tmpl.dst = '{'h01,'h1b,'h19,'h00,'h00,'h00}; // PTP dst MAC
tmpl
.
has_smac
=
1
;
tmpl
.
is_q
=
0
;
tmpl
.
ethertype
=
{
'h0800
};
//tmpl.ethertype = {'hdbff};
//tmpl.ethertype = {'h88f7};
//gen.set_randomization(EthPacketGenerator::SEQ_PAYLOAD | EthPacketGenerator::ETHERTYPE /*| EthPacketGenerator::RX_OOB*/) ;
gen
.
set_randomization
(
EthPacketGenerator
::
SEQ_PAYLOAD
)
;
gen
.
set_template
(
tmpl
)
;
gen
.
set_size
(
1
,
1500
)
;
cur_size
=
9
;
//cur_size = 1056;
dir
=
1
;
for
(
i
=
0
;
i
<
n_packets
;
i
++
)
begin
/* switch between incrementing/decrementing */
if
(
cur_size
==
1495
)
dir
=
0
;
if
(
cur_size
==
1
)
dir
=
1
;
/* increment/decrement frame size, based on dir */
if
(
dir
==
1
)
cur_size
+=
1
;
else
cur_size
-=
1
;
pkt
=
gen
.
gen
(
cur_size
)
;
//pkt = gen.gen();
tx_sizes
=
{
tx_sizes
,
pkt
.
size
};
tx_padded
=
{
tx_padded
,
padded_size
(
pkt
)
};
src
.
send
(
pkt
)
;
//#2us;
end
endtask
function
int
nopad_size
(
EthPacket
pkt
)
;
int
i
;
if
(
pkt
.
size
>
64
)
nopad_size
=
pkt
.
size
;
else
begin
nopad_size
=
1
;
for
(
i
=
1
;
i
<
pkt
.
size
;
i
++
)
begin
if
(
pkt
.
payload
[
i
]
==
0
)
break
;
nopad_size
=
nopad_size
+
1
;
end
nopad_size
=
nopad_size
+
14
;
//+header
end
endfunction
;
function
int
padded_size
(
EthPacket
pkt
)
;
if
(
pkt
.
size
<
60
)
padded_size
=
60
;
else
padded_size
=
pkt
.
size
;
endfunction
;
function
int
find_pkt_size
(
EthPacket
pkt
,
int
start
,
int
limit
)
;
int
i
;
for
(
i
=
start
;
i
<
start
+
limit
;
i
++
)
begin
if
(
pkt
.
size
==
tx_sizes
[
i
])
return
i
;
end
return
-
1
;
endfunction
;
testbench/xwrf_loopback/main.sv
0 → 100644
View file @
9fdb9f5b
`timescale
1
ns
/
1
ps
`include
"tbi_utils.sv"
`include
"simdrv_defs.svh"
`include
"if_wb_master.svh"
`include
"if_wb_slave.svh"
`include
"wb_packet_source.svh"
`include
"wb_packet_sink.svh"
`include
"if_wb_link.svh"
`include
"functions.svh"
`include
"lbk_regs.v"
module
main
;
wire
clk_ref
;
wire
clk_sys
;
wire
rst_n
;
/* WB masters */
IWishboneMaster
WB_lbk
(
clk_sys
,
rst_n
)
;
/* WB accessors */
CWishboneAccessor
acc_lbk
;
/* Fabrics */
IWishboneMaster
#(
2
,
16
)
WB_lbk_src
(
clk_sys
,
rst_n
)
;
IWishboneSlave
#(
2
,
16
)
WB_lbk_snk
(
clk_sys
,
rst_n
)
;
/* Fabrics accessors */
WBPacketSource
lbk_src
;
WBPacketSink
lbk_snk
;
tbi_clock_rst_gen
#(
.
g_rbclk_period
(
8000
))
clkgen
(
.
clk_ref_o
(
clk_ref
)
,
.
clk_sys_o
(
clk_sys
)
,
.
phy_rbclk_o
(
phy_rbclk
)
,
.
rst_n_o
(
rst_n
)
)
;
wrf_loopback
#(
.
g_interface_mode
(
PIPELINED
)
,
.
g_address_granularity
(
BYTE
))
WRF_LBK
(
.
clk_sys_i
(
clk_sys
)
,
.
rst_n_i
(
rst_n
)
,
.
snk_cyc_i
(
WB_lbk_src
.
master
.
cyc
)
,
.
snk_stb_i
(
WB_lbk_src
.
master
.
stb
)
,
.
snk_we_i
(
WB_lbk_src
.
master
.
we
)
,
.
snk_sel_i
(
WB_lbk_src
.
master
.
sel
)
,
.
snk_adr_i
(
WB_lbk_src
.
master
.
adr
)
,
.
snk_dat_i
(
WB_lbk_src
.
master
.
dat_o
)
,
.
snk_ack_o
(
WB_lbk_src
.
master
.
ack
)
,
.
snk_stall_o
(
WB_lbk_src
.
master
.
stall
)
,
.
src_cyc_o
(
WB_lbk_snk
.
slave
.
cyc
)
,
.
src_stb_o
(
WB_lbk_snk
.
slave
.
stb
)
,
.
src_we_o
(
WB_lbk_snk
.
slave
.
we
)
,
.
src_sel_o
(
WB_lbk_snk
.
slave
.
sel
)
,
.
src_adr_o
(
WB_lbk_snk
.
slave
.
adr
)
,
.
src_dat_o
(
WB_lbk_snk
.
slave
.
dat_i
)
,
.
src_ack_i
(
WB_lbk_snk
.
slave
.
ack
)
,
.
src_stall_i
(
WB_lbk_snk
.
slave
.
stall
)
,
.
wb_cyc_i
(
WB_lbk
.
master
.
cyc
)
,
.
wb_stb_i
(
WB_lbk
.
master
.
stb
)
,
.
wb_we_i
(
WB_lbk
.
master
.
we
)
,
.
wb_sel_i
(
4'b1111
)
,
.
wb_adr_i
(
WB_lbk
.
master
.
adr
)
,
.
wb_dat_i
(
WB_lbk
.
master
.
dat_o
)
,
.
wb_dat_o
(
WB_lbk
.
master
.
dat_i
)
,
.
wb_ack_o
(
WB_lbk
.
master
.
ack
)
,
.
wb_stall_o
(
WB_lbk
.
master
.
stall
))
;
initial
begin
@
(
posedge
rst_n
)
;
repeat
(
3
)
@
(
posedge
clk_sys
)
;
#
1u
s
;
acc_lbk
=
WB_lbk
.
get_accessor
()
;
acc_lbk
.
set_mode
(
PIPELINED
)
;
WB_lbk
.
settings
.
cyc_on_stall
=
1
;
lbk_src
=
new
(
WB_lbk_src
.
get_accessor
())
;
WB_lbk_src
.
settings
.
cyc_on_stall
=
1
;
#
1u
s
;
acc_lbk
.
write
(
`ADDR_LBK_DMAC_H
,
32'h00001122
)
;
#
1u
s
;
acc_lbk
.
write
(
`ADDR_LBK_DMAC_L
,
32'h33445566
)
;
#
1u
s
;
acc_lbk
.
write
(
`ADDR_LBK_MCR
,
`LBK_MCR_ENA
|
`LBK_MCR_FDMAC
)
;
//acc_lbk.write(`ADDR_LBK_MCR, `LBK_MCR_ENA);
#
1500
ns
;
tx_sizes
=
{};
//NOW LET'S SEND SOME FRAMES
send_frames
(
lbk_src
,
1500
)
;
end
initial
begin
EthPacket
pkt
;
int
prev_size
=
0
;
uint64_t
val64
;
WB_lbk_snk
.
settings
.
gen_random_stalls
=
1
;
lbk_snk
=
new
(
WB_lbk_snk
.
get_accessor
())
;
#
5u
s
;
while
(
1
)
begin
#
1u
s
;
lbk_snk
.
recv
(
pkt
)
;
//if(pkt.size-prev_size!=1)
// $warning("--> recv: size=%4d, %4d", pkt.size, pkt.size-prev_size);
if
(
pkt
.
dst
[
0
]
!=
8'h11
||
pkt
.
dst
[
1
]
!=
8'h22
||
pkt
.
dst
[
2
]
!=
8'h33
||
pkt
.
dst
[
3
]
!=
8'h44
||
pkt
.
dst
[
4
]
!=
8'h55
||
pkt
.
dst
[
5
]
!=
8'h66
)
//if(pkt.dst[0]!=8'h16 || pkt.dst[1]!=8'h21 || pkt.dst[2]!=8'h2c ||
// pkt.dst[3]!=8'h2c || pkt.dst[4]!=8'h37 || pkt.dst[5]!=8'h42)
begin
$
write
(
"%02X:"
,
pkt
.
dst
[
0
])
;
$
write
(
"%02X:"
,
pkt
.
dst
[
1
])
;
$
write
(
"%02X:"
,
pkt
.
dst
[
2
])
;
$
write
(
"%02X:"
,
pkt
.
dst
[
3
])
;
$
write
(
"%02X:"
,
pkt
.
dst
[
4
])
;
$
write
(
"%02X"
,
pkt
.
dst
[
5
])
;
$
warning
(
"--> recv: size=%4d, %4d"
,
pkt
.
size
,
pkt
.
size
-
prev_size
)
;
end
;
prev_size
=
pkt
.
size
;
//acc_lbk.read(`ADDR_LBK_RCV_CNT, val64);
//$display("rcv_cnt: %d", val64);
//acc_lbk.read(`ADDR_LBK_DRP_CNT, val64);
//$display("drp_cnt: %d", val64);
//acc_lbk.read(`ADDR_LBK_FWD_CNT, val64);
//$display("fwd_cnt: %d", val64);
//acc_lbk.write(`ADDR_LBK_MCR, `LBK_MCR_CLR);
//acc_lbk.write(`ADDR_LBK_MCR, 0);
end
end
endmodule
// main
testbench/xwrf_loopback/run.do
0 → 100644
View file @
9fdb9f5b
#vlog -dpiheader dpi/minic_dpi.h -sv main.sv +incdir+"." +incdir+../../sim
vlog -sv main.sv +incdir+"." +incdir+../../sim
make -f Makefile
#vsim -sv_lib dpi/minic -L unisim -t 10fs work.main -voptargs="+acc"
vsim -L unisim -t 10fs work.main -voptargs="+acc"
set StdArithNoWarnings 1
set NumericStdNoWarnings 1
do wave.do
radix -hexadecimal
run 20ms
wave zoomfull
radix -hexadecimal
testbench/xwrf_loopback/wave.do
0 → 100644
View file @
9fdb9f5b
onerror {resume}
quietly WaveActivateNextPane {} 0
add wave -noupdate /main/clk_sys
add wave -noupdate -expand /main/WRF_LBK/X_LOOPBACK/wrf_snk_i
add wave -noupdate /main/WRF_LBK/X_LOOPBACK/wrf_snk_o
add wave -noupdate -expand /main/WRF_LBK/X_LOOPBACK/wrf_src_o
add wave -noupdate -expand /main/WRF_LBK/X_LOOPBACK/wrf_src_i
add wave -noupdate -height 16 /main/WRF_LBK/X_LOOPBACK/WRF_SRC/state
add wave -noupdate -expand /main/WRF_LBK/X_LOOPBACK/src_fab
add wave -noupdate /main/WRF_LBK/X_LOOPBACK/src_dreq
add wave -noupdate /main/WRF_LBK/X_LOOPBACK/wb_i
add wave -noupdate /main/WRF_LBK/X_LOOPBACK/wb_o
add wave -noupdate -height 16 /main/WRF_LBK/X_LOOPBACK/lbk_rxfsm
add wave -noupdate -height 16 /main/WRF_LBK/X_LOOPBACK/lbk_txfsm
add wave -noupdate /main/WRF_LBK/X_LOOPBACK/fword_valid
add wave -noupdate -radix unsigned /main/WRF_LBK/X_LOOPBACK/fsize
add wave -noupdate -radix unsigned /main/WRF_LBK/X_LOOPBACK/txsize
add wave -noupdate -radix unsigned /main/WRF_LBK/X_LOOPBACK/tx_cnt
add wave -noupdate /main/WRF_LBK/X_LOOPBACK/ack_cnt
add wave -noupdate -expand -group FFIFO /main/WRF_LBK/X_LOOPBACK/ffifo_empty
add wave -noupdate -expand -group FFIFO /main/WRF_LBK/X_LOOPBACK/ffifo_full
add wave -noupdate -expand -group FFIFO -radix unsigned /main/WRF_LBK/X_LOOPBACK/FRAME_FIFO/count_o
add wave -noupdate -expand -group FFIFO /main/WRF_LBK/X_LOOPBACK/frame_wr
add wave -noupdate -expand -group FFIFO /main/WRF_LBK/X_LOOPBACK/frame_in
add wave -noupdate -expand -group FFIFO /main/WRF_LBK/X_LOOPBACK/frame_rd
add wave -noupdate -expand -group FFIFO /main/WRF_LBK/X_LOOPBACK/frame_out
add wave -noupdate -expand -group SFIFO /main/WRF_LBK/X_LOOPBACK/sfifo_empty
add wave -noupdate -expand -group SFIFO /main/WRF_LBK/X_LOOPBACK/sfifo_full
add wave -noupdate -expand -group SFIFO -radix unsigned /main/WRF_LBK/X_LOOPBACK/SIZE_FIFO/count_o
add wave -noupdate -expand -group SFIFO -radix unsigned /main/WRF_LBK/X_LOOPBACK/fsize_in
add wave -noupdate -expand -group SFIFO -radix unsigned /main/WRF_LBK/X_LOOPBACK/fsize_out
add wave -noupdate -expand -group SFIFO /main/WRF_LBK/X_LOOPBACK/fsize_wr
add wave -noupdate -expand -group SFIFO /main/WRF_LBK/X_LOOPBACK/fsize_rd
add wave -noupdate -expand -group CNTRS -radix unsigned /main/WRF_LBK/X_LOOPBACK/rcv_cnt
add wave -noupdate -expand -group CNTRS -radix unsigned /main/WRF_LBK/X_LOOPBACK/drp_cnt
add wave -noupdate -expand -group CNTRS -radix unsigned /main/WRF_LBK/X_LOOPBACK/fwd_cnt
TreeUpdate [SetDefaultTree]
WaveRestoreCursors {{Cursor 1} {1493558550000 fs} 1} {{Cursor 2} {1489058481240 fs} 1} {{Cursor 4} {1488913558440 fs} 0}
configure wave -namecolwidth 150
configure wave -valuecolwidth 100
configure wave -justifyvalue left
configure wave -signalnamewidth 1
configure wave -snapdistance 10
configure wave -datasetprefix 0
configure wave -rowmargin 4
configure wave -childrowmargin 2
configure wave -gridoffset 0
configure wave -gridperiod 1
configure wave -griddelta 40
configure wave -timeline 0
configure wave -timelineunits ns
update
WaveRestoreZoom {1488841281420 fs} {1489276418580 fs}
Write
Preview
Markdown
is supported
0%
Try again
or
attach a new file
Attach a file
Cancel
You are about to add
0
people
to the discussion. Proceed with caution.
Finish editing this message first!
Cancel
Please
register
or
sign in
to comment