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White Rabbit core collection
Commits
9876e112
Commit
9876e112
authored
Oct 27, 2011
by
Tomasz Wlostowski
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Plain Diff
simulation models: bugfixes
parent
9d8b618f
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6 changed files
with
33 additions
and
12 deletions
+33
-12
simdrv_minic.svh
sim/drivers/simdrv_minic.svh
+15
-6
eth_packet.svh
sim/eth_packet.svh
+1
-0
if_wb_master.svh
sim/if_wb_master.svh
+2
-1
if_wb_slave.svh
sim/if_wb_slave.svh
+10
-4
wb_packet_sink.svh
sim/wb_packet_sink.svh
+2
-0
wb_packet_source.svh
sim/wb_packet_source.svh
+3
-1
No files found.
sim/drivers/simdrv_minic.svh
View file @
9876e112
...
...
@@ -13,7 +13,7 @@ class CSimDrv_Minic;
`define
RX_DESC_VALID
(
d
)
((
d
)
&
(
1
<<
31
)
?
1
:
0
)
`define
RX_DESC_ERROR
(
d
)
((
d
)
&
(
1
<<
30
)
?
1
:
0
)
`define
RX_DESC_HAS_OOB
(
d
)
((
d
)
&
(
1
<<
29
)
?
1
:
0
)
`define
RX_DESC_SIZE
(
d
)
(((
d
)
&
(
1
<<
0
)
?
-
1
:
0
)
+
(
d
&
'
hff
f
e
))
`define
RX_DESC_SIZE
(
d
)
(((
d
)
&
(
1
<<
0
)
?
-
1
:
0
)
+
(
d
&
'
hffe
))
protected
CBusAccessor
acc_regs
,
acc_pmem
;
protected
uint32_t
base_regs
,
base_pmem
;
...
...
@@ -126,6 +126,8 @@ class CSimDrv_Minic;
minic_readl
(
`ADDR_MINIC_EIC_ISR
,
isr
)
;
// $display("RXFrame");
if
(
!
(
isr
&
`MINIC_EIC_ISR_RX
))
return
;
...
...
@@ -144,6 +146,13 @@ class CSimDrv_Minic;
num_words
=
(
payload_size
+
3
)
>>
2
;
pbuff
=
new
[
num_words
]
;
// $display("NWords %d hdr %x", num_words, desc_hdr);
if
(
`RX_DESC_HAS_OOB
(
desc_hdr
))
payload_size
=
payload_size
-
6
;
if
(
!
`RX_DESC_ERROR
(
desc_hdr
))
begin
...
...
sim/eth_packet.svh
View file @
9876e112
...
...
@@ -43,6 +43,7 @@ class EthPacket;
bit
error
;
bit
[
15
:
0
]
ethertype
;
bit
[
7
:
0
]
pclass
;
vid_t
vid
;
pcp_t
pcp
;
...
...
sim/if_wb_master.svh
View file @
9876e112
...
...
@@ -18,8 +18,8 @@ interface IWishboneMaster
input
rst_n_i
)
;
parameter
g_data_width
=
32
;
parameter
g_addr_width
=
32
;
parameter
g_data_width
=
32
;
logic
[
g_addr_width
-
1
:
0
]
adr
;
logic
[
g_data_width
-
1
:
0
]
dat_o
;
...
...
@@ -256,6 +256,7 @@ interface IWishboneMaster
begin
stb
<=
1'b1
;
we
<=
1'b1
;
while
(
stall
)
begin
count_ack
(
ack_count
)
;
...
...
sim/if_wb_slave.svh
View file @
9876e112
...
...
@@ -152,11 +152,17 @@ interface IWishboneSlave
task
pipelined_fsm
()
;
if
(
cyc
)
begin
if
(
settings
.
gen_random_stalls
)
gen_random_stalls
()
;
else
stall
<=
0
;
/* -----\/----- EXCLUDED -----\/-----
if(cyc) begin
end else
stall <= 0;
-----/\----- EXCLUDED -----/\----- */
if
(
cyc_start
)
begin
current_cycle
.
data
=
{};
...
...
sim/wb_packet_sink.svh
View file @
9876e112
...
...
@@ -35,6 +35,8 @@ class WBPacketSink extends EthPacketSink;
else
begin
pkt
.
has_smac
=
(
stat
&
'h4
?
1'b1
:
1'b0
)
;
pkt
.
has_crc
=
(
stat
&
'h8
?
1'b1
:
1'b0
)
;
pkt
.
pclass
=
(
stat
>>
8
)
&
'hff
;
end
endtask
// decode_status
...
...
sim/wb_packet_source.svh
View file @
9876e112
...
...
@@ -27,7 +27,9 @@ class WBPacketSource extends EthPacketSource;
st
[
1
]
=
1'b0
;
st
[
2
]
=
(
pkt
.
has_smac
?
1'b1
:
1'b0
)
;
st
[
3
]
=
error
;
st
[
15
:
3
]
=
0
;
// FIXME: add packet classes
st
[
15
:
8
]
=
pkt
.
pclass
;
// FIXME: add packet classes
st
[
7
:
4
]
=
0
;
return
st
;
endfunction
// pack_status
...
...
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