Skip to content
Projects
Groups
Snippets
Help
Loading...
Sign in
Toggle navigation
W
White Rabbit core collection
Project
Project
Details
Activity
Cycle Analytics
Repository
Repository
Files
Commits
Branches
Tags
Contributors
Graph
Compare
Charts
Issues
30
Issues
30
List
Board
Labels
Milestones
Merge Requests
1
Merge Requests
1
CI / CD
CI / CD
Pipelines
Schedules
Wiki
Wiki
image/svg+xml
Discourse
Discourse
Members
Members
Collapse sidebar
Close sidebar
Activity
Graph
Charts
Create a new issue
Commits
Issue Boards
Open sidebar
Projects
White Rabbit core collection
Commits
97ecba2b
Commit
97ecba2b
authored
Jul 03, 2020
by
Tomasz Wlostowski
Committed by
Grzegorz Daniluk
Sep 15, 2020
Browse files
Options
Browse Files
Download
Email Patches
Plain Diff
wr_gthe3_phy_family7: reset RX PCS after link loss to ensure reset of the bitslide counter
parent
6d55fbc4
Show whitespace changes
Inline
Side-by-side
Showing
2 changed files
with
8 additions
and
4 deletions
+8
-4
wr_gthe3_phy_family7.vhd
.../xilinx/wr_gtp_phy/family7-gthe3/wr_gthe3_phy_family7.vhd
+5
-3
wr_gthe3_wrapper.vhd
...form/xilinx/wr_gtp_phy/family7-gthe3/wr_gthe3_wrapper.vhd
+3
-1
No files found.
platform/xilinx/wr_gtp_phy/family7-gthe3/wr_gthe3_phy_family7.vhd
View file @
97ecba2b
...
...
@@ -191,6 +191,7 @@ architecture rtl of wr_gthe3_phy_family7 is
attribute
mark_debug
of
RXPMARESETDONE
:
signal
is
"TRUE"
;
attribute
mark_debug
of
serdes_ready
:
signal
is
"TRUE"
;
signal
rx_pcs_reset
:
std_logic
;
begin
...
...
@@ -212,7 +213,7 @@ begin
U_Bitslide
:
entity
work
.
gtp_bitslide
generic
map
(
g_simulation
=>
g_simulation
,
g_target
=>
"
virtex6
"
)
g_target
=>
"
ultrascale
"
)
port
map
(
gtp_rst_i
=>
rst_i
,
gtp_rx_clk_i
=>
RXUSRCLK2
,
...
...
@@ -220,7 +221,7 @@ begin
gtp_rx_byte_is_aligned_i
=>
RXBYTEISALIGNED
,
serdes_ready_i
=>
serdes_ready_rxusrclk
,
gtp_rx_slide_o
=>
RXSLIDE
,
gtp_rx_cdr_rst_o
=>
open
,
gtp_rx_cdr_rst_o
=>
rx_pcs_reset
,
bitslide_o
=>
rx_bitslide_o
,
synced_o
=>
rx_synced
);
...
...
@@ -367,6 +368,7 @@ begin
RXBYTEISALIGNED
=>
RXBYTEISALIGNED
,
RXCOMMADET
=>
RXCOMMADET
,
RXCTRL0
=>
RXCTRL0
,
RXPCSRESET
=>
rx_pcs_reset
,
rxctrl3
=>
rxctrl3
,
RXDATA
=>
RXDATA
,
RXOUTCLK
=>
RXOUTCLK
,
...
...
platform/xilinx/wr_gtp_phy/family7-gthe3/wr_gthe3_wrapper.vhd
View file @
97ecba2b
...
...
@@ -15,6 +15,8 @@ entity wr_gthe3_wrapper is
TXRESETDONE
:
out
std_logic
;
TXPROGDIVRESET
:
in
std_logic
;
RXPCSRESET
:
in
std_logic
;
GTHTXN
:
out
std_logic
;
GTHTXP
:
out
std_logic
;
...
...
@@ -1404,7 +1406,7 @@ begin
RXOSOVRDEN
=>
'0'
,
RXOUTCLKSEL
=>
"010"
,
RXPCOMMAALIGNEN
=>
'0'
,
RXPCSRESET
=>
'0'
,
RXPCSRESET
=>
RXPCSRESET
,
RXPD
=>
"00"
,
RXPHALIGN
=>
'0'
,
RXPHALIGNEN
=>
'0'
,
...
...
Write
Preview
Markdown
is supported
0%
Try again
or
attach a new file
Attach a file
Cancel
You are about to add
0
people
to the discussion. Proceed with caution.
Finish editing this message first!
Cancel
Please
register
or
sign in
to comment