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White Rabbit core collection
Commit 958bb360 authored by Tristan Gingold's avatar Tristan Gingold
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Generated files for wrpc-v5.0-pre1

parent 38ab214f
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    bin/wrpc/wrc_phy8.bram
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    bin/wrpc/wrc_phy8.mif
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    syn/cute_ref_design/Makefile
    View file @ 958bb360
    ......@@ -3,423 +3,352 @@
    # http://ohwr.org/projects/hdl-make/ #
    ########################################
    PROJECT := cute_wr_ref.xise
    ISE_CRAP := *.b cute_wr_ref_top_summary.html *.tcl cute_wr_ref_top.bld cute_wr_ref_top.cmd_log *.drc cute_wr_ref_top.lso *.ncd cute_wr_ref_top.ngc cute_wr_ref_top.ngd cute_wr_ref_top.ngr cute_wr_ref_top.pad cute_wr_ref_top.par cute_wr_ref_top.pcf cute_wr_ref_top.prj cute_wr_ref_top.ptwx cute_wr_ref_top.stx cute_wr_ref_top.syr cute_wr_ref_top.twr cute_wr_ref_top.twx cute_wr_ref_top.gise $(PROJECT).gise cute_wr_ref_top.bgn cute_wr_ref_top.unroutes cute_wr_ref_top.ut cute_wr_ref_top.xpi cute_wr_ref_top.xst cute_wr_ref_top_bitgen.xwbt cute_wr_ref_top_envsettings.html cute_wr_ref_top_guide.ncd cute_wr_ref_top_map.map cute_wr_ref_top_map.mrp cute_wr_ref_top_map.ncd cute_wr_ref_top_map.ngm cute_wr_ref_top_map.xrpt cute_wr_ref_top_ngdbuild.xrpt cute_wr_ref_top_pad.csv cute_wr_ref_top_pad.txt cute_wr_ref_top_par.xrpt cute_wr_ref_top_summary.xml cute_wr_ref_top_usage.xml cute_wr_ref_top_xst.xrpt usage_statistics_webtalk.html par_usage_statistics.html webtalk.log webtalk_pn.xml run.tcl
    TOP_MODULE := cute_wr_ref_top
    PROJECT := cute_wr_ref
    PROJECT_FILE := $(PROJECT).xise
    TOOL_PATH := /opt/Xilinx/14.7/ISE_DS/ISE/bin/lin64
    TCL_INTERPRETER := xtclsh
    ifneq ($(strip $(TOOL_PATH)),)
    TCL_INTERPRETER := $(TOOL_PATH)/$(TCL_INTERPRETER)
    endif
    SYN_FAMILY := Spartan6
    SYN_DEVICE := xc6slx45t
    SYN_PACKAGE := csg324
    SYN_GRADE := -3
    TCL_CREATE := project new $(PROJECT_FILE)
    TCL_OPEN := project open $(PROJECT_FILE)
    TCL_SAVE := project save
    TCL_CLOSE := project close
    #target for performing local synthesis
    local: syn_pre_cmd check_tool generate_tcl synthesis syn_post_cmd
    all: bitstream
    generate_tcl:
    echo "project open $(PROJECT)" > run.tcl
    echo "process run {Synthesize - XST}" >> run.tcl
    echo "process run {Translate}" >> run.tcl
    echo "process run {Map}" >> run.tcl
    echo "process run {Place & Route}" >> run.tcl
    echo "process run {Generate Programming File}" >> run.tcl
    files.tcl:
    echo 'xfile add ../../board/common/wr_board_pkg.vhd' >> $@
    echo 'xfile add ../../board/common/xwrc_board_common.vhd' >> $@
    echo 'xfile add ../../board/cute/oserdes_4_to_1.vhd' >> $@
    echo 'xfile add ../../board/cute/wr_cute_pkg.vhd' >> $@
    echo 'xfile add ../../board/cute/xwrc_board_cute.vhd' >> $@
    echo 'xfile add ../../ip_cores/etherbone-core/hdl/eb_slave_core/eb_cfg_fifo.vhd' >> $@
    echo 'xfile add ../../ip_cores/etherbone-core/hdl/eb_slave_core/eb_checksum.vhd' >> $@
    echo 'xfile add ../../ip_cores/etherbone-core/hdl/eb_slave_core/eb_commit_fifo.vhd' >> $@
    echo 'xfile add ../../ip_cores/etherbone-core/hdl/eb_slave_core/eb_eth_rx.vhd' >> $@
    echo 'xfile add ../../ip_cores/etherbone-core/hdl/eb_slave_core/eb_eth_tx.vhd' >> $@
    echo 'xfile add ../../ip_cores/etherbone-core/hdl/eb_slave_core/eb_ethernet_slave.vhd' >> $@
    echo 'xfile add ../../ip_cores/etherbone-core/hdl/eb_slave_core/eb_fifo.vhd' >> $@
    echo 'xfile add ../../ip_cores/etherbone-core/hdl/eb_slave_core/eb_hdr_pkg.vhd' >> $@
    echo 'xfile add ../../ip_cores/etherbone-core/hdl/eb_slave_core/eb_internals_pkg.vhd' >> $@
    echo 'xfile add ../../ip_cores/etherbone-core/hdl/eb_slave_core/eb_pass_fifo.vhd' >> $@
    echo 'xfile add ../../ip_cores/etherbone-core/hdl/eb_slave_core/eb_slave_fsm.vhd' >> $@
    echo 'xfile add ../../ip_cores/etherbone-core/hdl/eb_slave_core/eb_slave_top.vhd' >> $@
    echo 'xfile add ../../ip_cores/etherbone-core/hdl/eb_slave_core/eb_stream_narrow.vhd' >> $@
    echo 'xfile add ../../ip_cores/etherbone-core/hdl/eb_slave_core/eb_stream_widen.vhd' >> $@
    echo 'xfile add ../../ip_cores/etherbone-core/hdl/eb_slave_core/eb_tag_fifo.vhd' >> $@
    echo 'xfile add ../../ip_cores/etherbone-core/hdl/eb_slave_core/eb_tx_mux.vhd' >> $@
    echo 'xfile add ../../ip_cores/etherbone-core/hdl/eb_slave_core/eb_wbm_fifo.vhd' >> $@
    echo 'xfile add ../../ip_cores/etherbone-core/hdl/eb_slave_core/etherbone_pkg.vhd' >> $@
    echo 'xfile add ../../ip_cores/general-cores/modules/common/gc_async_counter_diff.vhd' >> $@
    echo 'xfile add ../../ip_cores/general-cores/modules/common/gc_crc_gen.vhd' >> $@
    echo 'xfile add ../../ip_cores/general-cores/modules/common/gc_edge_detect.vhd' >> $@
    echo 'xfile add ../../ip_cores/general-cores/modules/common/gc_extend_pulse.vhd' >> $@
    echo 'xfile add ../../ip_cores/general-cores/modules/common/gc_frequency_meter.vhd' >> $@
    echo 'xfile add ../../ip_cores/general-cores/modules/common/gc_fsm_watchdog.vhd' >> $@
    echo 'xfile add ../../ip_cores/general-cores/modules/common/gc_pulse_synchronizer.vhd' >> $@
    echo 'xfile add ../../ip_cores/general-cores/modules/common/gc_pulse_synchronizer2.vhd' >> $@
    echo 'xfile add ../../ip_cores/general-cores/modules/common/gc_reset.vhd' >> $@
    echo 'xfile add ../../ip_cores/general-cores/modules/common/gc_sync.vhd' >> $@
    echo 'xfile add ../../ip_cores/general-cores/modules/common/gc_sync_ffs.vhd' >> $@
    echo 'xfile add ../../ip_cores/general-cores/modules/common/gc_sync_register.vhd' >> $@
    echo 'xfile add ../../ip_cores/general-cores/modules/common/gc_sync_word_wr.vhd' >> $@
    echo 'xfile add ../../ip_cores/general-cores/modules/common/gencores_pkg.vhd' >> $@
    echo 'xfile add ../../ip_cores/general-cores/modules/genrams/common/generic_shiftreg_fifo.vhd' >> $@
    echo 'xfile add ../../ip_cores/general-cores/modules/genrams/common/inferred_async_fifo.vhd' >> $@
    echo 'xfile add ../../ip_cores/general-cores/modules/genrams/common/inferred_async_fifo_dual_rst.vhd' >> $@
    echo 'xfile add ../../ip_cores/general-cores/modules/genrams/common/inferred_sync_fifo.vhd' >> $@
    echo 'xfile add ../../ip_cores/general-cores/modules/genrams/generic/generic_async_fifo.vhd' >> $@
    echo 'xfile add ../../ip_cores/general-cores/modules/genrams/generic/generic_async_fifo_dual_rst.vhd' >> $@
    echo 'xfile add ../../ip_cores/general-cores/modules/genrams/generic/generic_sync_fifo.vhd' >> $@
    echo 'xfile add ../../ip_cores/general-cores/modules/genrams/genram_pkg.vhd' >> $@
    echo 'xfile add ../../ip_cores/general-cores/modules/genrams/memory_loader_pkg.vhd' >> $@
    echo 'xfile add ../../ip_cores/general-cores/modules/genrams/xilinx/gc_shiftreg.vhd' >> $@
    echo 'xfile add ../../ip_cores/general-cores/modules/genrams/xilinx/generic_dpram.vhd' >> $@
    echo 'xfile add ../../ip_cores/general-cores/modules/genrams/xilinx/generic_dpram_dualclock.vhd' >> $@
    echo 'xfile add ../../ip_cores/general-cores/modules/genrams/xilinx/generic_dpram_sameclock.vhd' >> $@
    echo 'xfile add ../../ip_cores/general-cores/modules/genrams/xilinx/generic_dpram_split.vhd' >> $@
    echo 'xfile add ../../ip_cores/general-cores/modules/genrams/xilinx/generic_simple_dpram.vhd' >> $@
    echo 'xfile add ../../ip_cores/general-cores/modules/wishbone/wb_clock_crossing/xwb_clock_crossing.vhd' >> $@
    echo 'xfile add ../../ip_cores/general-cores/modules/wishbone/wb_crossbar/sdb_rom.vhd' >> $@
    echo 'xfile add ../../ip_cores/general-cores/modules/wishbone/wb_crossbar/xwb_crossbar.vhd' >> $@
    echo 'xfile add ../../ip_cores/general-cores/modules/wishbone/wb_crossbar/xwb_sdb_crossbar.vhd' >> $@
    echo 'xfile add ../../ip_cores/general-cores/modules/wishbone/wb_onewire_master/sockit_owm.v' >> $@
    echo 'xfile add ../../ip_cores/general-cores/modules/wishbone/wb_onewire_master/wb_onewire_master.vhd' >> $@
    echo 'xfile add ../../ip_cores/general-cores/modules/wishbone/wb_onewire_master/xwb_onewire_master.vhd' >> $@
    echo 'xfile add ../../ip_cores/general-cores/modules/wishbone/wb_slave_adapter/wb_slave_adapter.vhd' >> $@
    echo 'xfile add ../../ip_cores/general-cores/modules/wishbone/wb_uart/simple_uart_pkg.vhd' >> $@
    echo 'xfile add ../../ip_cores/general-cores/modules/wishbone/wb_uart/simple_uart_wb.vhd' >> $@
    echo 'xfile add ../../ip_cores/general-cores/modules/wishbone/wb_uart/uart_async_rx.vhd' >> $@
    echo 'xfile add ../../ip_cores/general-cores/modules/wishbone/wb_uart/uart_async_tx.vhd' >> $@
    echo 'xfile add ../../ip_cores/general-cores/modules/wishbone/wb_uart/uart_baud_gen.vhd' >> $@
    echo 'xfile add ../../ip_cores/general-cores/modules/wishbone/wb_uart/wb_simple_uart.vhd' >> $@
    echo 'xfile add ../../ip_cores/general-cores/modules/wishbone/wb_uart/xwb_simple_uart.vhd' >> $@
    echo 'xfile add ../../ip_cores/general-cores/modules/wishbone/wbgen2/wbgen2_eic.vhd' >> $@
    echo 'xfile add ../../ip_cores/general-cores/modules/wishbone/wbgen2/wbgen2_fifo_sync.vhd' >> $@
    echo 'xfile add ../../ip_cores/general-cores/modules/wishbone/wbgen2/wbgen2_pkg.vhd' >> $@
    echo 'xfile add ../../ip_cores/general-cores/modules/wishbone/wishbone_pkg.vhd' >> $@
    echo 'xfile add ../../ip_cores/general-cores/platform/xilinx/wb_xil_multiboot/multiboot_fsm.vhd' >> $@
    echo 'xfile add ../../ip_cores/general-cores/platform/xilinx/wb_xil_multiboot/multiboot_regs.vhd' >> $@
    echo 'xfile add ../../ip_cores/general-cores/platform/xilinx/wb_xil_multiboot/spi_master.vhd' >> $@
    echo 'xfile add ../../ip_cores/general-cores/platform/xilinx/wb_xil_multiboot/xwb_xil_multiboot.vhd' >> $@
    echo 'xfile add ../../ip_cores/urv-core/rtl/urv_cpu.v' >> $@
    echo 'xfile add ../../ip_cores/urv-core/rtl/urv_csr.v' >> $@
    echo 'xfile add ../../ip_cores/urv-core/rtl/urv_decode.v' >> $@
    echo 'xfile add ../../ip_cores/urv-core/rtl/urv_divide.v' >> $@
    echo 'xfile add ../../ip_cores/urv-core/rtl/urv_exceptions.v' >> $@
    echo 'xfile add ../../ip_cores/urv-core/rtl/urv_exec.v' >> $@
    echo 'xfile add ../../ip_cores/urv-core/rtl/urv_fetch.v' >> $@
    echo 'xfile add ../../ip_cores/urv-core/rtl/urv_multiply.v' >> $@
    echo 'xfile add ../../ip_cores/urv-core/rtl/urv_regfile.v' >> $@
    echo 'xfile add ../../ip_cores/urv-core/rtl/urv_shifter.v' >> $@
    echo 'xfile add ../../ip_cores/urv-core/rtl/urv_timer.v' >> $@
    echo 'xfile add ../../ip_cores/urv-core/rtl/urv_writeback.v' >> $@
    echo 'xfile add ../../modules/fabric/wr_fabric_pkg.vhd' >> $@
    echo 'xfile add ../../modules/fabric/xwb_fabric_sink.vhd' >> $@
    echo 'xfile add ../../modules/fabric/xwb_fabric_source.vhd' >> $@
    echo 'xfile add ../../modules/fabric/xwrf_loopback/lbk_pkg.vhd' >> $@
    echo 'xfile add ../../modules/fabric/xwrf_loopback/lbk_wishbone_controller.vhd' >> $@
    echo 'xfile add ../../modules/fabric/xwrf_loopback/xwrf_loopback.vhd' >> $@
    echo 'xfile add ../../modules/fabric/xwrf_mux.vhd' >> $@
    echo 'xfile add ../../modules/timing/dmtd_phase_meas.vhd' >> $@
    echo 'xfile add ../../modules/timing/dmtd_sampler.vhd' >> $@
    echo 'xfile add ../../modules/timing/dmtd_with_deglitcher.vhd' >> $@
    echo 'xfile add ../../modules/timing/pulse_stamper.vhd' >> $@
    echo 'xfile add ../../modules/timing/pulse_stamper_sync.vhd' >> $@
    echo 'xfile add ../../modules/wr_dacs/cute_serial_dac.vhd' >> $@
    echo 'xfile add ../../modules/wr_dacs/cute_serial_dac_arb.vhd' >> $@
    echo 'xfile add ../../modules/wr_endpoint/endpoint_pkg.vhd' >> $@
    echo 'xfile add ../../modules/wr_endpoint/endpoint_private_pkg.vhd' >> $@
    echo 'xfile add ../../modules/wr_endpoint/ep_1000basex_pcs.vhd' >> $@
    echo 'xfile add ../../modules/wr_endpoint/ep_autonegotiation.vhd' >> $@
    echo 'xfile add ../../modules/wr_endpoint/ep_clock_alignment_fifo.vhd' >> $@
    echo 'xfile add ../../modules/wr_endpoint/ep_crc32_pkg.vhd' >> $@
    echo 'xfile add ../../modules/wr_endpoint/ep_leds_controller.vhd' >> $@
    echo 'xfile add ../../modules/wr_endpoint/ep_packet_filter.vhd' >> $@
    echo 'xfile add ../../modules/wr_endpoint/ep_pcs_tbi_mdio_wb.vhd' >> $@
    echo 'xfile add ../../modules/wr_endpoint/ep_registers_pkg.vhd' >> $@
    echo 'xfile add ../../modules/wr_endpoint/ep_rtu_header_extract.vhd' >> $@
    echo 'xfile add ../../modules/wr_endpoint/ep_rx_buffer.vhd' >> $@
    echo 'xfile add ../../modules/wr_endpoint/ep_rx_crc_size_check.vhd' >> $@
    echo 'xfile add ../../modules/wr_endpoint/ep_rx_early_address_match.vhd' >> $@
    echo 'xfile add ../../modules/wr_endpoint/ep_rx_oob_insert.vhd' >> $@
    echo 'xfile add ../../modules/wr_endpoint/ep_rx_path.vhd' >> $@
    echo 'xfile add ../../modules/wr_endpoint/ep_rx_pcs_16bit.vhd' >> $@
    echo 'xfile add ../../modules/wr_endpoint/ep_rx_pcs_8bit.vhd' >> $@
    echo 'xfile add ../../modules/wr_endpoint/ep_rx_status_reg_insert.vhd' >> $@
    echo 'xfile add ../../modules/wr_endpoint/ep_rx_vlan_unit.vhd' >> $@
    echo 'xfile add ../../modules/wr_endpoint/ep_rx_wb_master.vhd' >> $@
    echo 'xfile add ../../modules/wr_endpoint/ep_sync_detect.vhd' >> $@
    echo 'xfile add ../../modules/wr_endpoint/ep_sync_detect_16bit.vhd' >> $@
    echo 'xfile add ../../modules/wr_endpoint/ep_timestamping_unit.vhd' >> $@
    echo 'xfile add ../../modules/wr_endpoint/ep_ts_counter.vhd' >> $@
    echo 'xfile add ../../modules/wr_endpoint/ep_tx_crc_inserter.vhd' >> $@
    echo 'xfile add ../../modules/wr_endpoint/ep_tx_header_processor.vhd' >> $@
    echo 'xfile add ../../modules/wr_endpoint/ep_tx_inject_ctrl.vhd' >> $@
    echo 'xfile add ../../modules/wr_endpoint/ep_tx_packet_injection.vhd' >> $@
    echo 'xfile add ../../modules/wr_endpoint/ep_tx_path.vhd' >> $@
    echo 'xfile add ../../modules/wr_endpoint/ep_tx_pcs_16bit.vhd' >> $@
    echo 'xfile add ../../modules/wr_endpoint/ep_tx_pcs_8bit.vhd' >> $@
    echo 'xfile add ../../modules/wr_endpoint/ep_tx_vlan_unit.vhd' >> $@
    echo 'xfile add ../../modules/wr_endpoint/ep_wishbone_controller.vhd' >> $@
    echo 'xfile add ../../modules/wr_endpoint/prbs/lfsr.v' >> $@
    echo 'xfile add ../../modules/wr_endpoint/prbs/lfsr_prbs_check.v' >> $@
    echo 'xfile add ../../modules/wr_endpoint/prbs/lfsr_prbs_gen.v' >> $@
    echo 'xfile add ../../modules/wr_endpoint/wr_endpoint.vhd' >> $@
    echo 'xfile add ../../modules/wr_endpoint/xwr_endpoint.vhd' >> $@
    echo 'xfile add ../../modules/wr_mini_nic/minic_wb_slave.vhd' >> $@
    echo 'xfile add ../../modules/wr_mini_nic/minic_wbgen2_pkg.vhd' >> $@
    echo 'xfile add ../../modules/wr_mini_nic/wr_mini_nic.vhd' >> $@
    echo 'xfile add ../../modules/wr_mini_nic/xwr_mini_nic.vhd' >> $@
    echo 'xfile add ../../modules/wr_pps_gen/pps_gen_wb.vhd' >> $@
    echo 'xfile add ../../modules/wr_pps_gen/wr_pps_gen.vhd' >> $@
    echo 'xfile add ../../modules/wr_pps_gen/xwr_pps_gen.vhd' >> $@
    echo 'xfile add ../../modules/wr_softpll_ng/softpll_pkg.vhd' >> $@
    echo 'xfile add ../../modules/wr_softpll_ng/spll_aligner.vhd' >> $@
    echo 'xfile add ../../modules/wr_softpll_ng/spll_wb_slave.vhd' >> $@
    echo 'xfile add ../../modules/wr_softpll_ng/spll_wbgen2_pkg.vhd' >> $@
    echo 'xfile add ../../modules/wr_softpll_ng/wr_softpll_ng.vhd' >> $@
    echo 'xfile add ../../modules/wr_softpll_ng/xwr_softpll_ng.vhd' >> $@
    echo 'xfile add ../../modules/wr_streamers/dropping_buffer.vhd' >> $@
    echo 'xfile add ../../modules/wr_streamers/escape_detector.vhd' >> $@
    echo 'xfile add ../../modules/wr_streamers/escape_inserter.vhd' >> $@
    echo 'xfile add ../../modules/wr_streamers/fifo_showahead_adapter.vhd' >> $@
    echo 'xfile add ../../modules/wr_streamers/fixed_latency_delay.vhd' >> $@
    echo 'xfile add ../../modules/wr_streamers/fixed_latency_ts_match.vhd' >> $@
    echo 'xfile add ../../modules/wr_streamers/streamers_pkg.vhd' >> $@
    echo 'xfile add ../../modules/wr_streamers/streamers_priv_pkg.vhd' >> $@
    echo 'xfile add ../../modules/wr_streamers/ts_restore_tai.vhd' >> $@
    echo 'xfile add ../../modules/wr_streamers/wr_streamers_wb.vhd' >> $@
    echo 'xfile add ../../modules/wr_streamers/wr_streamers_wbgen2_pkg.vhd' >> $@
    echo 'xfile add ../../modules/wr_streamers/xrtx_streamers_stats.vhd' >> $@
    echo 'xfile add ../../modules/wr_streamers/xrx_streamer.vhd' >> $@
    echo 'xfile add ../../modules/wr_streamers/xrx_streamers_stats.vhd' >> $@
    echo 'xfile add ../../modules/wr_streamers/xtx_streamer.vhd' >> $@
    echo 'xfile add ../../modules/wr_streamers/xtx_streamers_stats.vhd' >> $@
    echo 'xfile add ../../modules/wr_streamers/xwr_streamers.vhd' >> $@
    echo 'xfile add ../../modules/wr_tbi_phy/disparity_gen_pkg.vhd' >> $@
    echo 'xfile add ../../modules/wrc_core/wr_core.vhd' >> $@
    echo 'xfile add ../../modules/wrc_core/wrc_cpu_csr_wb.vhd' >> $@
    echo 'xfile add ../../modules/wrc_core/wrc_cpu_csr_wbgen2_pkg.vhd' >> $@
    echo 'xfile add ../../modules/wrc_core/wrc_diags_dpram.vhd' >> $@
    echo 'xfile add ../../modules/wrc_core/wrc_periph.vhd' >> $@
    echo 'xfile add ../../modules/wrc_core/wrc_syscon_pkg.vhd' >> $@
    echo 'xfile add ../../modules/wrc_core/wrc_syscon_wb.vhd' >> $@
    echo 'xfile add ../../modules/wrc_core/wrc_urv_wrapper.vhd' >> $@
    echo 'xfile add ../../modules/wrc_core/wrcore_pkg.vhd' >> $@
    echo 'xfile add ../../modules/wrc_core/xwr_core.vhd' >> $@
    echo 'xfile add ../../platform/xilinx/wr_gtp_phy/gtp_bitslide.vhd' >> $@
    echo 'xfile add ../../platform/xilinx/wr_gtp_phy/spartan6/gtp_phase_align.vhd' >> $@
    echo 'xfile add ../../platform/xilinx/wr_gtp_phy/spartan6/whiterabbitgtp_wrapper_tile_spartan6.vhd' >> $@
    echo 'xfile add ../../platform/xilinx/wr_gtp_phy/spartan6/wr_gtp_phy_spartan6.vhd' >> $@
    echo 'xfile add ../../platform/xilinx/wr_xilinx_pkg.vhd' >> $@
    echo 'xfile add ../../platform/xilinx/xwrc_platform_xilinx.vhd' >> $@
    echo 'xfile add ../../top/cute_ref_design/cute_wr_ref_top.ucf' >> $@
    echo 'xfile add ../../top/cute_ref_design/cute_wr_ref_top.vhd' >> $@
    synthesis:
    /home/greg/opt/Xilinx/14.7/ISE_DS/ISE/bin/lin64/xtclsh run.tcl
    SYN_PRE_PROJECT_CMD :=
    SYN_POST_PROJECT_CMD :=
    check_tool:
    SYN_PRE_SYNTHESIZE_CMD :=
    SYN_POST_SYNTHESIZE_CMD :=
    syn_post_cmd:
    SYN_PRE_TRANSLATE_CMD :=
    SYN_POST_TRANSLATE_CMD :=
    syn_pre_cmd:
    SYN_PRE_MAP_CMD :=
    SYN_POST_MAP_CMD :=
    #target for cleaning all intermediate stuff
    clean:
    rm -f $(ISE_CRAP)
    rm -rf xst xlnx_auto_*_xdb iseconfig _xmsgs _ngo
    SYN_PRE_PAR_CMD :=
    SYN_POST_PAR_CMD :=
    #target for cleaning final files
    mrproper:
    rm -f *.bit *.bin *.mcs
    SYN_PRE_BITSTREAM_CMD :=
    SYN_POST_BITSTREAM_CMD :=
    .PHONY: mrproper clean syn_pre_cmd syn_post_cmd synthesis local check_tool
    project.tcl:
    echo file delete $(PROJECT_FILE) >> $@
    echo $(TCL_CREATE) >> $@
    echo xfile remove [search \* -type file] >> $@
    echo source files.tcl >> $@
    echo project set '"family"' \"$(SYN_FAMILY)\" >> $@
    echo project set '"device"' \"$(SYN_DEVICE)\" >> $@
    echo project set '"package"' \"$(SYN_PACKAGE)\" >> $@
    echo project set '"speed"' \"$(SYN_GRADE)\" >> $@
    echo project set '"Manual Implementation Compile Order"' \"false\" >> $@
    echo project set '"Auto Implementation Top"' \"false\" >> $@
    echo project set '"Create Binary Configuration File"' \"true\" >> $@
    echo set compile_directory . >> $@
    echo project set top $(TOP_MODULE) >> $@
    echo $(TCL_SAVE) >> $@
    echo $(TCL_CLOSE) >> $@
    USER:=$(HDLMAKE_RSYNTH_USER)# take the value from the environment
    SERVER:=$(HDLMAKE_RSYNTH_SERVER)# take the value from the environment
    ISE_PATH:=$(HDLMAKE_RSYNTH_ISE_PATH)
    R_NAME:=greg/cute_wr_ref
    PORT:=22
    project: files.tcl project.tcl
    $(SYN_PRE_PROJECT_CMD)
    $(TCL_INTERPRETER) $@.tcl
    $(SYN_POST_PROJECT_CMD)
    touch $@
    __test_for_remote_synthesis_variables:
    ifeq (x$(USER),x)
    @echo "Remote synthesis user is not set. You can set it by editing variable USER in the makefile or setting env. variable HDLMAKE_RSYNTH_USER." && false
    endif
    ifeq (x$(SERVER),x)
    @echo "Remote synthesis server is not set. You can set it by editing variable SERVER in the makefile or setting env. variable HDLMAKE_RSYNTH_SERVER." && false
    endif
    ifeq (x$(ISE_PATH),x)
    @echo "Remote synthesis server is not set. You can set it by editing variable ISE_PATH in the makefile or setting env. variable HDLMAKE_RSYNTH_ISE_PATH." && false
    endif
    synthesize.tcl:
    echo $(TCL_OPEN) >> $@
    echo set process {Synthesize - XST} >> $@
    echo process run '$$'process >> $@
    echo set result [process get '$$'process status] >> $@
    echo if { '$$'result == \"errors\" } { >> $@
    echo exit 1 >> $@
    echo } >> $@
    echo $(TCL_SAVE) >> $@
    echo $(TCL_CLOSE) >> $@
    CWD := $(shell pwd)
    synthesize: project synthesize.tcl ../../board/common/wr_board_pkg.vhd ../../board/common/xwrc_board_common.vhd ../../board/cute/oserdes_4_to_1.vhd ../../board/cute/wr_cute_pkg.vhd ../../board/cute/xwrc_board_cute.vhd ../../ip_cores/etherbone-core/hdl/eb_slave_core/eb_cfg_fifo.vhd ../../ip_cores/etherbone-core/hdl/eb_slave_core/eb_checksum.vhd ../../ip_cores/etherbone-core/hdl/eb_slave_core/eb_commit_fifo.vhd ../../ip_cores/etherbone-core/hdl/eb_slave_core/eb_eth_rx.vhd ../../ip_cores/etherbone-core/hdl/eb_slave_core/eb_eth_tx.vhd ../../ip_cores/etherbone-core/hdl/eb_slave_core/eb_ethernet_slave.vhd ../../ip_cores/etherbone-core/hdl/eb_slave_core/eb_fifo.vhd ../../ip_cores/etherbone-core/hdl/eb_slave_core/eb_hdr_pkg.vhd ../../ip_cores/etherbone-core/hdl/eb_slave_core/eb_internals_pkg.vhd ../../ip_cores/etherbone-core/hdl/eb_slave_core/eb_pass_fifo.vhd ../../ip_cores/etherbone-core/hdl/eb_slave_core/eb_slave_fsm.vhd ../../ip_cores/etherbone-core/hdl/eb_slave_core/eb_slave_top.vhd ../../ip_cores/etherbone-core/hdl/eb_slave_core/eb_stream_narrow.vhd ../../ip_cores/etherbone-core/hdl/eb_slave_core/eb_stream_widen.vhd ../../ip_cores/etherbone-core/hdl/eb_slave_core/eb_tag_fifo.vhd ../../ip_cores/etherbone-core/hdl/eb_slave_core/eb_tx_mux.vhd ../../ip_cores/etherbone-core/hdl/eb_slave_core/eb_wbm_fifo.vhd ../../ip_cores/etherbone-core/hdl/eb_slave_core/etherbone_pkg.vhd ../../ip_cores/general-cores/modules/common/gc_async_counter_diff.vhd ../../ip_cores/general-cores/modules/common/gc_crc_gen.vhd ../../ip_cores/general-cores/modules/common/gc_edge_detect.vhd ../../ip_cores/general-cores/modules/common/gc_extend_pulse.vhd ../../ip_cores/general-cores/modules/common/gc_frequency_meter.vhd ../../ip_cores/general-cores/modules/common/gc_fsm_watchdog.vhd ../../ip_cores/general-cores/modules/common/gc_pulse_synchronizer.vhd ../../ip_cores/general-cores/modules/common/gc_pulse_synchronizer2.vhd ../../ip_cores/general-cores/modules/common/gc_reset.vhd ../../ip_cores/general-cores/modules/common/gc_sync.vhd ../../ip_cores/general-cores/modules/common/gc_sync_ffs.vhd ../../ip_cores/general-cores/modules/common/gc_sync_register.vhd ../../ip_cores/general-cores/modules/common/gc_sync_word_wr.vhd ../../ip_cores/general-cores/modules/common/gencores_pkg.vhd ../../ip_cores/general-cores/modules/genrams/common/generic_shiftreg_fifo.vhd ../../ip_cores/general-cores/modules/genrams/common/inferred_async_fifo.vhd ../../ip_cores/general-cores/modules/genrams/common/inferred_async_fifo_dual_rst.vhd ../../ip_cores/general-cores/modules/genrams/common/inferred_sync_fifo.vhd ../../ip_cores/general-cores/modules/genrams/generic/generic_async_fifo.vhd ../../ip_cores/general-cores/modules/genrams/generic/generic_async_fifo_dual_rst.vhd ../../ip_cores/general-cores/modules/genrams/generic/generic_sync_fifo.vhd ../../ip_cores/general-cores/modules/genrams/genram_pkg.vhd ../../ip_cores/general-cores/modules/genrams/memory_loader_pkg.vhd ../../ip_cores/general-cores/modules/genrams/xilinx/gc_shiftreg.vhd ../../ip_cores/general-cores/modules/genrams/xilinx/generic_dpram.vhd ../../ip_cores/general-cores/modules/genrams/xilinx/generic_dpram_dualclock.vhd ../../ip_cores/general-cores/modules/genrams/xilinx/generic_dpram_sameclock.vhd ../../ip_cores/general-cores/modules/genrams/xilinx/generic_dpram_split.vhd ../../ip_cores/general-cores/modules/genrams/xilinx/generic_simple_dpram.vhd ../../ip_cores/general-cores/modules/wishbone/wb_clock_crossing/xwb_clock_crossing.vhd ../../ip_cores/general-cores/modules/wishbone/wb_crossbar/sdb_rom.vhd ../../ip_cores/general-cores/modules/wishbone/wb_crossbar/xwb_crossbar.vhd ../../ip_cores/general-cores/modules/wishbone/wb_crossbar/xwb_sdb_crossbar.vhd ../../ip_cores/general-cores/modules/wishbone/wb_onewire_master/sockit_owm.v ../../ip_cores/general-cores/modules/wishbone/wb_onewire_master/wb_onewire_master.vhd ../../ip_cores/general-cores/modules/wishbone/wb_onewire_master/xwb_onewire_master.vhd ../../ip_cores/general-cores/modules/wishbone/wb_slave_adapter/wb_slave_adapter.vhd ../../ip_cores/general-cores/modules/wishbone/wb_uart/simple_uart_pkg.vhd ../../ip_cores/general-cores/modules/wishbone/wb_uart/simple_uart_wb.vhd ../../ip_cores/general-cores/modules/wishbone/wb_uart/uart_async_rx.vhd ../../ip_cores/general-cores/modules/wishbone/wb_uart/uart_async_tx.vhd ../../ip_cores/general-cores/modules/wishbone/wb_uart/uart_baud_gen.vhd ../../ip_cores/general-cores/modules/wishbone/wb_uart/wb_simple_uart.vhd ../../ip_cores/general-cores/modules/wishbone/wb_uart/xwb_simple_uart.vhd ../../ip_cores/general-cores/modules/wishbone/wbgen2/wbgen2_eic.vhd ../../ip_cores/general-cores/modules/wishbone/wbgen2/wbgen2_fifo_sync.vhd ../../ip_cores/general-cores/modules/wishbone/wbgen2/wbgen2_pkg.vhd ../../ip_cores/general-cores/modules/wishbone/wishbone_pkg.vhd ../../ip_cores/general-cores/platform/xilinx/wb_xil_multiboot/multiboot_fsm.vhd ../../ip_cores/general-cores/platform/xilinx/wb_xil_multiboot/multiboot_regs.vhd ../../ip_cores/general-cores/platform/xilinx/wb_xil_multiboot/spi_master.vhd ../../ip_cores/general-cores/platform/xilinx/wb_xil_multiboot/xwb_xil_multiboot.vhd ../../ip_cores/urv-core/rtl/urv_cpu.v ../../ip_cores/urv-core/rtl/urv_csr.v ../../ip_cores/urv-core/rtl/urv_decode.v ../../ip_cores/urv-core/rtl/urv_divide.v ../../ip_cores/urv-core/rtl/urv_exceptions.v ../../ip_cores/urv-core/rtl/urv_exec.v ../../ip_cores/urv-core/rtl/urv_fetch.v ../../ip_cores/urv-core/rtl/urv_multiply.v ../../ip_cores/urv-core/rtl/urv_regfile.v ../../ip_cores/urv-core/rtl/urv_shifter.v ../../ip_cores/urv-core/rtl/urv_timer.v ../../ip_cores/urv-core/rtl/urv_writeback.v ../../modules/fabric/wr_fabric_pkg.vhd ../../modules/fabric/xwb_fabric_sink.vhd ../../modules/fabric/xwb_fabric_source.vhd ../../modules/fabric/xwrf_loopback/lbk_pkg.vhd ../../modules/fabric/xwrf_loopback/lbk_wishbone_controller.vhd ../../modules/fabric/xwrf_loopback/xwrf_loopback.vhd ../../modules/fabric/xwrf_mux.vhd ../../modules/timing/dmtd_phase_meas.vhd ../../modules/timing/dmtd_sampler.vhd ../../modules/timing/dmtd_with_deglitcher.vhd ../../modules/timing/pulse_stamper.vhd ../../modules/timing/pulse_stamper_sync.vhd ../../modules/wr_dacs/cute_serial_dac.vhd ../../modules/wr_dacs/cute_serial_dac_arb.vhd ../../modules/wr_endpoint/endpoint_pkg.vhd ../../modules/wr_endpoint/endpoint_private_pkg.vhd ../../modules/wr_endpoint/ep_1000basex_pcs.vhd ../../modules/wr_endpoint/ep_autonegotiation.vhd ../../modules/wr_endpoint/ep_clock_alignment_fifo.vhd ../../modules/wr_endpoint/ep_crc32_pkg.vhd ../../modules/wr_endpoint/ep_leds_controller.vhd ../../modules/wr_endpoint/ep_packet_filter.vhd ../../modules/wr_endpoint/ep_pcs_tbi_mdio_wb.vhd ../../modules/wr_endpoint/ep_registers_pkg.vhd ../../modules/wr_endpoint/ep_rtu_header_extract.vhd ../../modules/wr_endpoint/ep_rx_buffer.vhd ../../modules/wr_endpoint/ep_rx_crc_size_check.vhd ../../modules/wr_endpoint/ep_rx_early_address_match.vhd ../../modules/wr_endpoint/ep_rx_oob_insert.vhd ../../modules/wr_endpoint/ep_rx_path.vhd ../../modules/wr_endpoint/ep_rx_pcs_16bit.vhd ../../modules/wr_endpoint/ep_rx_pcs_8bit.vhd ../../modules/wr_endpoint/ep_rx_status_reg_insert.vhd ../../modules/wr_endpoint/ep_rx_vlan_unit.vhd ../../modules/wr_endpoint/ep_rx_wb_master.vhd ../../modules/wr_endpoint/ep_sync_detect.vhd ../../modules/wr_endpoint/ep_sync_detect_16bit.vhd ../../modules/wr_endpoint/ep_timestamping_unit.vhd ../../modules/wr_endpoint/ep_ts_counter.vhd ../../modules/wr_endpoint/ep_tx_crc_inserter.vhd ../../modules/wr_endpoint/ep_tx_header_processor.vhd ../../modules/wr_endpoint/ep_tx_inject_ctrl.vhd ../../modules/wr_endpoint/ep_tx_packet_injection.vhd ../../modules/wr_endpoint/ep_tx_path.vhd ../../modules/wr_endpoint/ep_tx_pcs_16bit.vhd ../../modules/wr_endpoint/ep_tx_pcs_8bit.vhd ../../modules/wr_endpoint/ep_tx_vlan_unit.vhd ../../modules/wr_endpoint/ep_wishbone_controller.vhd ../../modules/wr_endpoint/prbs/lfsr.v ../../modules/wr_endpoint/prbs/lfsr_prbs_check.v ../../modules/wr_endpoint/prbs/lfsr_prbs_gen.v ../../modules/wr_endpoint/wr_endpoint.vhd ../../modules/wr_endpoint/xwr_endpoint.vhd ../../modules/wr_mini_nic/minic_wb_slave.vhd ../../modules/wr_mini_nic/minic_wbgen2_pkg.vhd ../../modules/wr_mini_nic/wr_mini_nic.vhd ../../modules/wr_mini_nic/xwr_mini_nic.vhd ../../modules/wr_pps_gen/pps_gen_wb.vhd ../../modules/wr_pps_gen/wr_pps_gen.vhd ../../modules/wr_pps_gen/xwr_pps_gen.vhd ../../modules/wr_softpll_ng/softpll_pkg.vhd ../../modules/wr_softpll_ng/spll_aligner.vhd ../../modules/wr_softpll_ng/spll_wb_slave.vhd ../../modules/wr_softpll_ng/spll_wbgen2_pkg.vhd ../../modules/wr_softpll_ng/wr_softpll_ng.vhd ../../modules/wr_softpll_ng/xwr_softpll_ng.vhd ../../modules/wr_streamers/dropping_buffer.vhd ../../modules/wr_streamers/escape_detector.vhd ../../modules/wr_streamers/escape_inserter.vhd ../../modules/wr_streamers/fifo_showahead_adapter.vhd ../../modules/wr_streamers/fixed_latency_delay.vhd ../../modules/wr_streamers/fixed_latency_ts_match.vhd ../../modules/wr_streamers/streamers_pkg.vhd ../../modules/wr_streamers/streamers_priv_pkg.vhd ../../modules/wr_streamers/ts_restore_tai.vhd ../../modules/wr_streamers/wr_streamers_wb.vhd ../../modules/wr_streamers/wr_streamers_wbgen2_pkg.vhd ../../modules/wr_streamers/xrtx_streamers_stats.vhd ../../modules/wr_streamers/xrx_streamer.vhd ../../modules/wr_streamers/xrx_streamers_stats.vhd ../../modules/wr_streamers/xtx_streamer.vhd ../../modules/wr_streamers/xtx_streamers_stats.vhd ../../modules/wr_streamers/xwr_streamers.vhd ../../modules/wr_tbi_phy/disparity_gen_pkg.vhd ../../modules/wrc_core/wr_core.vhd ../../modules/wrc_core/wrc_cpu_csr_wb.vhd ../../modules/wrc_core/wrc_cpu_csr_wbgen2_pkg.vhd ../../modules/wrc_core/wrc_diags_dpram.vhd ../../modules/wrc_core/wrc_periph.vhd ../../modules/wrc_core/wrc_syscon_pkg.vhd ../../modules/wrc_core/wrc_syscon_wb.vhd ../../modules/wrc_core/wrc_urv_wrapper.vhd ../../modules/wrc_core/wrcore_pkg.vhd ../../modules/wrc_core/xwr_core.vhd ../../platform/xilinx/wr_gtp_phy/gtp_bitslide.vhd ../../platform/xilinx/wr_gtp_phy/spartan6/gtp_phase_align.vhd ../../platform/xilinx/wr_gtp_phy/spartan6/whiterabbitgtp_wrapper_tile_spartan6.vhd ../../platform/xilinx/wr_gtp_phy/spartan6/wr_gtp_phy_spartan6.vhd ../../platform/xilinx/wr_xilinx_pkg.vhd ../../platform/xilinx/xwrc_platform_xilinx.vhd ../../top/cute_ref_design/cute_wr_ref_top.ucf ../../top/cute_ref_design/cute_wr_ref_top.vhd
    $(SYN_PRE_SYNTHESIZE_CMD)
    $(TCL_INTERPRETER) $@.tcl
    $(SYN_POST_SYNTHESIZE_CMD)
    touch $@
    FILES := ../../ip_cores/etherbone-core/hdl/eb_slave_core/eb_commit_fifo.vhd \
    ../../top/cute_ref_design/cute_wr_ref_top.ucf \
    ../../modules/wr_si57x_interface/xwr_si57x_interface.vhd \
    ../../ip_cores/etherbone-core/hdl/eb_slave_core/eb_wbm_fifo.vhd \
    ../../ip_cores/etherbone-core/hdl/eb_slave_core/eb_stream_widen.vhd \
    ../../ip_cores/vme64x-core/hdl/rtl/vme_user_csr.vhd \
    ../../modules/wr_endpoint/ep_sync_detect.vhd \
    ../../modules/wr_pps_gen/wr_pps_gen.vhd \
    ../../ip_cores/general-cores/platform/xilinx/wb_xil_multiboot/multiboot_fsm.vhd \
    ../../ip_cores/etherbone-core/hdl/eb_slave_core/eb_slave_top.vhd \
    ../../ip_cores/etherbone-core/hdl/eb_master_core/eb_master_slave_wrapper.vhd \
    ../../ip_cores/general-cores/modules/genrams/generic/generic_sync_fifo.vhd \
    ../../modules/fabric/xwrf_loopback/wrf_loopback.vhd \
    ../../modules/wr_endpoint/ep_tx_inject_ctrl.vhd \
    ../../modules/wr_endpoint/ep_wishbone_controller.vhd \
    ../../modules/wr_endpoint/endpoint_pkg.vhd \
    ../../modules/wr_tbi_phy/enc_8b10b.vhd \
    ../../modules/wrc_core/wrc_syscon_pkg.vhd \
    ../../modules/wr_eca/eca_tlu_fsm.vhd \
    ../../ip_cores/general-cores/modules/wishbone/wb_axi4lite_bridge/xwb_axi4lite_bridge.vhd \
    ../../ip_cores/etherbone-core/hdl/eb_master_core/eb_record_gen.vhd \
    ../../ip_cores/etherbone-core/hdl/eb_master_core/eb_master_wb_if.vhd \
    ../../ip_cores/general-cores/modules/genrams/xilinx/generic_dpram_split.vhd \
    ../../platform/xilinx/chipscope/chipscope_icon.ngc \
    ../../platform/xilinx/wr_gtp_phy/spartan6/whiterabbitgtp_wrapper_tile_spartan6.vhd \
    ../../modules/wr_eca/eca_free.vhd \
    ../../ip_cores/general-cores/modules/wishbone/wb_i2c_master/i2c_master_top.vhd \
    ../../modules/wr_endpoint/ep_rtu_header_extract.vhd \
    ../../ip_cores/general-cores/modules/genrams/common/inferred_sync_fifo.vhd \
    ../../modules/wr_endpoint/ep_tx_path.vhd \
    ../../modules/wr_endpoint/ep_pcs_tbi_mdio_wb.vhd \
    ../../ip_cores/general-cores/modules/wishbone/wb_axi4lite_bridge/wb_axi4lite_bridge.vhd \
    ../../ip_cores/gn4124-core/hdl/gn4124core/rtl/spartan6/gn4124_core_pkg.vhd \
    ../../modules/wr_endpoint/ep_tx_pcs_16bit.vhd \
    ../../modules/wrc_core/wrc_periph.vhd \
    ../../modules/wr_eca/eca_pkg.vhd \
    ../../ip_cores/vme64x-core/hdl/rtl/vme_irq_controller.vhd \
    ../../ip_cores/general-cores/modules/wishbone/wb_spi/xwb_spi.vhd \
    ../../ip_cores/general-cores/modules/wishbone/wb_simple_timer/wb_tics.vhd \
    ../../modules/wr_softpll_ng/spll_aligner.vhd \
    ../../ip_cores/general-cores/modules/wishbone/wb_gpio_port/xwb_gpio_port.vhd \
    ../../modules/wr_endpoint/ep_rx_oob_insert.vhd \
    ../../ip_cores/general-cores/modules/common/gc_pulse_synchronizer2.vhd \
    ../../ip_cores/general-cores/modules/common/gc_moving_average.vhd \
    ../../ip_cores/general-cores/modules/common/gc_prio_encoder.vhd \
    ../../modules/wr_eca/eca_msi.vhd \
    ../../modules/wrc_core/wr_core.vhd \
    ../../ip_cores/general-cores/modules/common/gc_reset.vhd \
    ../../modules/timing/multi_dmtd_with_deglitcher.vhd \
    ../../ip_cores/general-cores/modules/wishbone/wb_lm32/src/lm32_logic_op.v \
    ../../modules/wr_mini_nic/xwr_mini_nic.vhd \
    ../../ip_cores/general-cores/modules/wishbone/wb_dma/xwb_streamer.vhd \
    ../../modules/wr_endpoint/ep_tx_header_processor.vhd \
    ../../ip_cores/general-cores/modules/common/gencores_pkg.vhd \
    ../../ip_cores/etherbone-core/hdl/eb_usb_core/ez_usb.vhd \
    ../../ip_cores/etherbone-core/hdl/eb_master_core/eb_master_eth_tx.vhd \
    ../../ip_cores/general-cores/modules/wishbone/wb_i2c_master/i2c_master_bit_ctrl.vhd \
    ../../modules/wr_eca/eca_channel.vhd \
    ../../modules/wr_eca/wr_eca.vhd \
    ../../ip_cores/general-cores/modules/wishbone/wb_gpio_port/wb_gpio_port.vhd \
    ../../modules/wr_eca/eca_offset.vhd \
    ../../ip_cores/gn4124-core/hdl/gn4124core/rtl/spartan6/l2p_ser.vhd \
    ../../ip_cores/general-cores/platform/xilinx/wb_xilinx_fpga_loader/wb_xilinx_fpga_loader.vhd \
    ../../modules/wr_endpoint/ep_crc32_pkg.vhd \
    ../../modules/wr_endpoint/ep_rx_pcs_8bit.vhd \
    ../../modules/wr_softpll_ng/spll_wbgen2_pkg.vhd \
    ../../ip_cores/general-cores/modules/wishbone/wb_lm32/generated/xwb_lm32.vhd \
    ../../modules/wr_eca/eca_wb_event.vhd \
    ../../modules/wr_tlu/tlu_fsm.vhd \
    ../../ip_cores/vme64x-core/hdl/rtl/vme64x_pkg.vhd \
    ../../modules/fabric/xwrf_loopback/lbk_pkg.vhd \
    ../../ip_cores/general-cores/modules/genrams/common/inferred_async_fifo.vhd \
    ../../ip_cores/general-cores/modules/common/gc_dyn_extend_pulse.vhd \
    ../../ip_cores/general-cores/modules/wishbone/wb_dma/xwb_dma.vhd \
    ../../modules/wr_dacs/spec_serial_dac_arb.vhd \
    ../../modules/wr_streamers/xrx_streamers_stats.vhd \
    ../../ip_cores/general-cores/modules/common/gc_dyn_glitch_filt.vhd \
    ../../modules/wr_eca/eca_auto.vhd \
    ../../ip_cores/general-cores/modules/wishbone/wishbone_pkg.vhd \
    ../../modules/wr_endpoint/ep_rx_crc_size_check.vhd \
    ../../platform/xilinx/wr_gtp_phy/spartan6/wr_gtp_phy_spartan6.vhd \
    ../../ip_cores/general-cores/modules/wishbone/wb_uart/uart_async_rx.vhd \
    ../../modules/wr_tlu/tlu_pkg.vhd \
    ../../board/cute/wr_cute_pkg.vhd \
    ../../modules/wr_dacs/cute_serial_dac.vhd \
    ../../modules/wr_eca/eca_ac_wbm_auto.vhd \
    ../../ip_cores/etherbone-core/hdl/eb_slave_core/eb_eth_rx.vhd \
    ../../modules/wr_softpll_ng/xwr_softpll_ng.vhd \
    ../../modules/wr_eca/eca_tlu.vhd \
    cute_wr_ref.xise \
    ../../ip_cores/etherbone-core/hdl/eb_usb_core/ez_usb_pkg.vhd \
    ../../ip_cores/etherbone-core/hdl/eb_usb_core/ez_usb_fifos.vhd \
    ../../modules/wr_mini_nic/minic_wb_slave.vhd \
    ../../ip_cores/general-cores/modules/wishbone/wbgen2/wbgen2_fifo_sync.vhd \
    ../../platform/xilinx/wr_xilinx_pkg.vhd \
    ../../ip_cores/general-cores/modules/genrams/xilinx/generic_simple_dpram.vhd \
    ../../modules/fabric/wr_fabric_pkg.vhd \
    ../../modules/wr_eca/eca_sdp.vhd \
    ../../modules/wr_eca/eca_scan.vhd \
    ../../modules/wr_streamers/xrtx_streamers_stats.vhd \
    ../../ip_cores/general-cores/modules/common/gc_sync_ffs.vhd \
    ../../modules/wr_endpoint/ep_rx_path.vhd \
    ../../modules/wr_streamers/dropping_buffer.vhd \
    ../../ip_cores/general-cores/modules/wishbone/wb_spi/spi_clgen.v \
    ../../modules/fabric/xwrf_reg.vhd \
    ../../ip_cores/general-cores/modules/wishbone/wb_lm32/src/lm32_addsub.v \
    ../../ip_cores/general-cores/modules/wishbone/wb_irq/wb_irq_timer.vhd \
    ../../modules/wr_eca/eca_ac_wbm_auto_pkg.vhd \
    ../../modules/timing/dmtd_phase_meas.vhd \
    ../../ip_cores/gn4124-core/hdl/gn4124core/rtl/spartan6/pulse_sync_rtl.vhd \
    ../../modules/wr_endpoint/ep_rx_pcs_16bit.vhd \
    run.tcl \
    ../../ip_cores/general-cores/modules/genrams/genram_pkg.vhd \
    ../../modules/wr_eca/eca_scubus_channel.vhd \
    ../../ip_cores/etherbone-core/hdl/eb_slave_core/eb_checksum.vhd \
    ../../board/cute/xwrc_board_cute.vhd \
    ../../modules/timing/pulse_stamper.vhd \
    ../../ip_cores/general-cores/modules/genrams/generic/generic_async_fifo.vhd \
    ../../modules/wr_streamers/streamers_pkg.vhd \
    ../../ip_cores/general-cores/modules/wishbone/wb_spi/spi_top.v \
    ../../modules/wr_si57x_interface/si570_if_wbgen2_pkg.vhd \
    ../../modules/wr_streamers/rx_streamer.vhd \
    ../../ip_cores/general-cores/modules/genrams/memory_loader_pkg.vhd \
    ../../modules/timing/dmtd_with_deglitcher.vhd \
    ../../ip_cores/general-cores/modules/wishbone/wb_simple_pwm/simple_pwm_wb.vhd \
    ../../ip_cores/general-cores/modules/wishbone/wb_irq/wb_irq_lm32.vhd \
    ../../platform/xilinx/xwrc_platform_xilinx.vhd \
    ../../modules/wr_endpoint/ep_timestamping_unit.vhd \
    ../../modules/fabric/xwb_fabric_sink.vhd \
    ../../modules/wrc_core/wrc_diags_pkg.vhd \
    ../../ip_cores/general-cores/modules/wishbone/wb_uart/uart_baud_gen.vhd \
    ../../modules/wr_si57x_interface/si570_if_wb.vhd \
    ../../ip_cores/general-cores/modules/wishbone/wb_irq/irqm_core.vhd \
    ../../modules/wr_endpoint/ep_rx_wb_master.vhd \
    ../../ip_cores/vme64x-core/hdl/rtl/vme_bus.vhd \
    ../../modules/wrc_core/wrcore_pkg.vhd \
    ../../modules/wr_endpoint/ep_sync_detect_16bit.vhd \
    ../../modules/wr_eca/eca_adder.vhd \
    ../../ip_cores/general-cores/modules/wishbone/wb_irq/wb_irq_pkg.vhd \
    ../../modules/fabric/xwrf_mux.vhd \
    ../../ip_cores/general-cores/modules/wishbone/wb_onewire_master/wb_onewire_master.vhd \
    ../../modules/wrc_core/xwrc_diags_wb.vhd \
    ../../ip_cores/general-cores/modules/common/gc_single_reset_gen.vhd \
    ../../modules/wr_tlu/tlu.vhd \
    ../../ip_cores/general-cores/modules/wishbone/wb_clock_crossing/xwb_clock_crossing.vhd \
    ../../top/cute_ref_design/cute_wr_ref_top.vhd \
    ../../ip_cores/general-cores/modules/wishbone/wb_vic/wb_vic.vhd \
    ../../modules/wr_eca/eca_piso_fifo.vhd \
    ../../ip_cores/etherbone-core/hdl/eb_master_core/eb_master_top.vhd \
    ../../modules/wrc_core/wrc_syscon_wb.vhd \
    ../../modules/wrc_core/xwr_core.vhd \
    ../../ip_cores/general-cores/platform/xilinx/wb_xilinx_fpga_loader/xloader_registers_pkg.vhd \
    ../../ip_cores/etherbone-core/hdl/eb_slave_core/eb_cfg_fifo.vhd \
    ../../ip_cores/general-cores/modules/common/gc_word_packer.vhd \
    ../../modules/wr_eca/eca_rmw.vhd \
    ../../modules/wr_endpoint/ep_tx_pcs_8bit.vhd \
    ../../ip_cores/vme64x-core/hdl/rtl/vme64x_core.vhd \
    ../../ip_cores/general-cores/modules/wishbone/wb_crossbar/wb_skidpad.vhd \
    ../../ip_cores/general-cores/modules/wishbone/wb_simple_pwm/simple_pwm_wbgen2_pkg.vhd \
    ../../ip_cores/general-cores/platform/xilinx/wb_xil_multiboot/multiboot_regs.vhd \
    ../../platform/xilinx/wr_gtp_phy/spartan6/gtp_phase_align.vhd \
    ../../modules/wr_endpoint/ep_tx_vlan_unit.vhd \
    ../../ip_cores/general-cores/modules/wishbone/wb_irq/wb_irq_master.vhd \
    ../../ip_cores/general-cores/modules/wishbone/wb_dpram/xwb_dpram.vhd \
    ../../ip_cores/general-cores/modules/common/gc_arbitrated_mux.vhd \
    ../../ip_cores/etherbone-core/hdl/eb_slave_core/eb_raw_slave.vhd \
    ../../ip_cores/general-cores/modules/wishbone/wb_vic/xwb_vic.vhd \
    ../../ip_cores/general-cores/modules/wishbone/wb_simple_pwm/xwb_simple_pwm.vhd \
    ../../modules/wr_dacs/spec_serial_dac.vhd \
    ../../modules/wrc_core/wrc_diags_wb.vhd \
    ../../ip_cores/general-cores/modules/wishbone/wb_i2c_master/wb_i2c_master.vhd \
    ../../modules/wr_pps_gen/xwr_pps_gen.vhd \
    ../../board/common/xwrc_board_common.vhd \
    ../../ip_cores/gn4124-core/hdl/spec/ip_cores/l2p_fifo.ngc \
    ../../ip_cores/general-cores/modules/common/gc_async_signals_input_stage.vhd \
    ../../ip_cores/general-cores/modules/wishbone/wb_lm32/src/lm32_ram.vhd \
    ../../ip_cores/general-cores/modules/wishbone/wbgen2/wbgen2_dpssram.vhd \
    ../../modules/fabric/xwb_fabric_source.vhd \
    ../../modules/wr_eca/eca_tlu_auto.vhd \
    ../../ip_cores/general-cores/modules/wishbone/wb_uart/uart_async_tx.vhd \
    ../../modules/wr_eca/eca_tlu_auto_pkg.vhd \
    ../../modules/wr_tbi_phy/wr_tbi_phy.vhd \
    ../../platform/xilinx/chipscope/chipscope_ila.ngc \
    ../../ip_cores/general-cores/modules/wishbone/wb_lm32/generated/lm32_allprofiles.v \
    ../../ip_cores/general-cores/modules/wishbone/wbgen2/wbgen2_fifo_async.vhd \
    ../../modules/wr_streamers/xwr_streamers.vhd \
    ../../modules/wr_softpll_ng/spll_wb_slave.vhd \
    ../../modules/timing/hpll_period_detect.vhd \
    ../../ip_cores/general-cores/modules/wishbone/wb_simple_pwm/wb_simple_pwm.vhd \
    ../../modules/wr_tbi_phy/disparity_gen_pkg.vhd \
    ../../ip_cores/general-cores/modules/genrams/xilinx/generic_spram.vhd \
    ../../ip_cores/general-cores/modules/common/gc_glitch_filt.vhd \
    ../../modules/wr_pps_gen/pps_gen_wb.vhd \
    ../../modules/wr_endpoint/ep_rx_status_reg_insert.vhd \
    ../../ip_cores/gn4124-core/hdl/gn4124core/rtl/l2p_dma_master.vhd \
    ../../modules/wr_streamers/xtx_streamers_stats.vhd \
    ../../ip_cores/gn4124-core/hdl/gn4124core/rtl/spartan6/serdes_n_to_1_s2_se.vhd \
    ../../modules/wr_endpoint/xwr_endpoint.vhd \
    ../../ip_cores/general-cores/modules/common/gc_dec_8b10b.vhd \
    ../../modules/wr_streamers/streamers_priv_pkg.vhd \
    ../../ip_cores/general-cores/modules/common/gc_fsm_watchdog.vhd \
    ../../ip_cores/general-cores/modules/wishbone/wbgen2/wbgen2_pkg.vhd \
    ../../ip_cores/general-cores/modules/wishbone/wb_i2c_bridge/wb_i2c_bridge.vhd \
    ../../modules/wr_endpoint/ep_registers_pkg.vhd \
    ../../modules/wr_endpoint/ep_autonegotiation.vhd \
    ../../ip_cores/general-cores/modules/wishbone/wb_spi/wb_spi.vhd \
    ../../ip_cores/general-cores/modules/wishbone/wb_vic/vic_prio_enc.vhd \
    ../../modules/wr_endpoint/ep_tx_packet_injection.vhd \
    ../../ip_cores/general-cores/modules/wishbone/wb_axi4lite_bridge/axi4_pkg.vhd \
    ../../ip_cores/general-cores/modules/wishbone/wb_spi_flash/wb_spi_flash.vhd \
    ../../modules/wr_endpoint/endpoint_private_pkg.vhd \
    ../../ip_cores/general-cores/modules/wishbone/wb_bus_fanout/xwb_bus_fanout.vhd \
    ../../ip_cores/general-cores/modules/wishbone/wb_lm32/platform/spartan6/jtag_tap.v \
    ../../ip_cores/general-cores/modules/wishbone/wb_i2c_master/i2c_master_byte_ctrl.vhd \
    ../../ip_cores/gn4124-core/hdl/gn4124core/rtl/l2p_arbiter.vhd \
    ../../ip_cores/general-cores/modules/common/gc_i2c_slave.vhd \
    ../../ip_cores/general-cores/modules/wishbone/wb_async_bridge/wb_async_bridge.vhd \
    ../../ip_cores/general-cores/modules/wishbone/wb_crossbar/sdb_rom.vhd \
    ../../ip_cores/general-cores/modules/common/gc_rr_arbiter.vhd \
    ../../ip_cores/general-cores/modules/wishbone/wb_lm32/src/lm32_shifter.v \
    ../../modules/wr_endpoint/ep_clock_alignment_fifo.vhd \
    ../../ip_cores/gn4124-core/hdl/gn4124core/rtl/dma_controller.vhd \
    ../../modules/wr_endpoint/ep_tx_crc_inserter.vhd \
    ../../modules/wr_eca/eca.vhd \
    ../../ip_cores/etherbone-core/hdl/eb_slave_core/eb_eth_tx.vhd \
    ../../ip_cores/general-cores/modules/wishbone/wb_vic/wb_slave_vic.vhd \
    ../../ip_cores/general-cores/modules/common/gc_dual_pi_controller.vhd \
    ../../board/common/wr_board_pkg.vhd \
    ../../ip_cores/general-cores/modules/wishbone/wb_spi/spi_shift.v \
    ../../ip_cores/general-cores/modules/genrams/xilinx/generic_dpram_dualclock.vhd \
    ../../ip_cores/general-cores/modules/wishbone/wb_lm32/src/jtag_cores.v \
    ../../modules/wr_endpoint/ep_rx_early_address_match.vhd \
    ../../modules/wr_si57x_interface/wr_si57x_interface.vhd \
    ../../ip_cores/gn4124-core/hdl/gn4124core/rtl/wbmaster32.vhd \
    ../../ip_cores/general-cores/modules/wishbone/wb_async_bridge/xwb_async_bridge.vhd \
    ../../ip_cores/vme64x-core/hdl/rtl/vme_funct_match.vhd \
    ../../ip_cores/general-cores/platform/xilinx/wb_xilinx_fpga_loader/xloader_wb.vhd \
    ../../modules/wr_endpoint/wr_endpoint.vhd \
    ../../modules/wr_streamers/escape_detector.vhd \
    ../../modules/wr_softpll_ng/spll_period_detect.vhd \
    ../../ip_cores/general-cores/modules/wishbone/wb_uart/simple_uart_wb.vhd \
    ../../ip_cores/etherbone-core/hdl/eb_slave_core/eb_internals_pkg.vhd \
    ../../ip_cores/general-cores/modules/common/gc_extend_pulse.vhd \
    ../../modules/wr_endpoint/ep_ts_counter.vhd \
    ../../ip_cores/general-cores/modules/wishbone/wb_lm32/src/lm32_adder.v \
    ../../ip_cores/general-cores/modules/wishbone/wb_i2c_master/xwb_i2c_master.vhd \
    ../../modules/wr_eca/eca_ac_wbm.vhd \
    ../../ip_cores/general-cores/modules/wishbone/wb_lm32/platform/spartan6/lm32_multiplier.v \
    ../../modules/wr_eca/eca_data.vhd \
    ../../ip_cores/general-cores/modules/common/gc_delay_gen.vhd \
    ../../modules/wr_eca/eca_queue.vhd \
    ../../modules/wr_mini_nic/minic_wbgen2_pkg.vhd \
    ../../modules/wr_eca/eca_auto_pkg.vhd \
    ../../ip_cores/general-cores/modules/wishbone/wbgen2/wbgen2_eic.vhd \
    ../../ip_cores/general-cores/modules/genrams/xilinx/generic_dpram.vhd \
    ../../ip_cores/general-cores/modules/genrams/common/generic_shiftreg_fifo.vhd \
    ../../ip_cores/general-cores/modules/wishbone/wb_crossbar/xwb_crossbar.vhd \
    ../../modules/fabric/xwrf_loopback/xwrf_loopback.vhd \
    ../../ip_cores/general-cores/modules/wishbone/wb_irq/wb_irq_slave.vhd \
    ../../modules/wr_endpoint/ep_rx_buffer.vhd \
    ../../modules/wr_mini_nic/minic_packet_buffer.vhd \
    ../../ip_cores/general-cores/modules/wishbone/wb_onewire_master/sockit_owm.v \
    ../../modules/wr_eca/eca_internals_pkg.vhd \
    ../../modules/wr_streamers/xtx_streamer.vhd \
    ../../ip_cores/gn4124-core/hdl/gn4124core/rtl/p2l_dma_master.vhd \
    ../../ip_cores/general-cores/modules/wishbone/wb_lm32/src/lm32_mc_arithmetic.v \
    ../../ip_cores/gn4124-core/hdl/gn4124core/rtl/spartan6/serdes_1_to_n_clk_pll_s2_diff.vhd \
    ../../modules/wr_dacs/cute_serial_dac_arb.vhd \
    ../../ip_cores/general-cores/modules/common/gc_comparator.vhd \
    ../../ip_cores/general-cores/modules/wishbone/wb_lm32/src/lm32_dp_ram.vhd \
    ../../modules/wr_mini_nic/wr_mini_nic.vhd \
    ../../ip_cores/etherbone-core/hdl/eb_slave_core/eb_pass_fifo.vhd \
    ../../modules/fabric/xwrf_loopback/lbk_wishbone_controller.vhd \
    ../../ip_cores/etherbone-core/hdl/eb_master_core/eb_commit_len_fifo.vhd \
    ../../ip_cores/gn4124-core/hdl/gn4124core/rtl/spartan6/serdes_n_to_1_s2_diff.vhd \
    ../../platform/xilinx/wr_gtp_phy/gtp_bitslide.vhd \
    ../../ip_cores/general-cores/modules/wishbone/wb_uart/wb_simple_uart.vhd \
    ../../ip_cores/general-cores/modules/wishbone/wb_serial_lcd/wb_serial_lcd.vhd \
    ../../ip_cores/vme64x-core/hdl/rtl/xvme64x_core.vhd \
    ../../ip_cores/etherbone-core/hdl/eb_master_core/eb_framer.vhd \
    ../../ip_cores/etherbone-core/hdl/eb_slave_core/eb_tx_mux.vhd \
    ../../ip_cores/etherbone-core/hdl/eb_slave_core/etherbone_pkg.vhd \
    ../../ip_cores/etherbone-core/hdl/eb_slave_core/eb_slave_core.vhd \
    ../../ip_cores/etherbone-core/hdl/eb_slave_core/eb_stream_narrow.vhd \
    ../../ip_cores/general-cores/modules/common/gc_sync_register.vhd \
    ../../ip_cores/general-cores/modules/wishbone/wb_crossbar/xwb_register_link.vhd \
    ../../ip_cores/general-cores/platform/xilinx/wb_xilinx_fpga_loader/xwb_xilinx_fpga_loader.vhd \
    ../../ip_cores/general-cores/modules/common/gc_ds182x_interface.vhd \
    ../../ip_cores/general-cores/modules/wishbone/wb_crossbar/xwb_sdb_crossbar.vhd \
    ../../modules/timing/pulse_gen.vhd \
    ../../modules/wr_endpoint/ep_rx_vlan_unit.vhd \
    ../../ip_cores/general-cores/modules/common/gc_big_adder.vhd \
    ../../board/cute/cute_reset_gen.vhd \
    ../../modules/wr_softpll_ng/wr_softpll_ng.vhd \
    ../../ip_cores/etherbone-core/hdl/eb_slave_core/eb_ethernet_slave.vhd \
    ../../ip_cores/gn4124-core/hdl/gn4124core/rtl/spartan6/gn4124_core.vhd \
    ../../ip_cores/general-cores/platform/xilinx/wb_xil_multiboot/xwb_xil_multiboot.vhd \
    ../../modules/wr_endpoint/ep_1000basex_pcs.vhd \
    ../../ip_cores/gn4124-core/hdl/gn4124core/rtl/spartan6/serdes_1_to_n_data_s2_se.vhd \
    ../../modules/wr_streamers/wr_streamers_wb.vhd \
    ../../modules/wr_streamers/wr_streamers_wbgen2_pkg.vhd \
    ../../ip_cores/general-cores/modules/common/gc_delay_line.vhd \
    ../../ip_cores/general-cores/platform/xilinx/wb_xil_multiboot/spi_master.vhd \
    ../../ip_cores/general-cores/modules/common/gc_pulse_synchronizer.vhd \
    ../../modules/wr_eca/eca_tag_channel.vhd \
    ../../ip_cores/general-cores/modules/common/gc_crc_gen.vhd \
    ../../modules/wr_eca/eca_tdp.vhd \
    ../../ip_cores/general-cores/modules/common/gc_bicolor_led_ctrl.vhd \
    ../../ip_cores/etherbone-core/hdl/eb_slave_core/eb_slave_fsm.vhd \
    ../../ip_cores/general-cores/modules/genrams/xilinx/generic_dpram_sameclock.vhd \
    ../../modules/wr_eca/eca_search.vhd \
    ../../modules/wr_eca/eca_queue_auto_pkg.vhd \
    ../../ip_cores/general-cores/modules/common/gc_serial_dac.vhd \
    ../../ip_cores/vme64x-core/hdl/rtl/vme_cr_csr_space.vhd \
    ../../ip_cores/general-cores/modules/genrams/xilinx/gc_shiftreg.vhd \
    ../../ip_cores/gn4124-core/hdl/gn4124core/rtl/p2l_decode32.vhd \
    ../../modules/wr_eca/eca_queue_auto.vhd \
    ../../modules/wr_streamers/tx_streamer.vhd \
    ../../ip_cores/gn4124-core/hdl/gn4124core/rtl/dma_controller_wb_slave.vhd \
    ../../modules/wr_eca/eca_wr_time.vhd \
    ../../modules/wr_streamers/xrx_streamer.vhd \
    ../../modules/wr_endpoint/ep_rx_bypass_queue.vhd \
    ../../ip_cores/gn4124-core/hdl/gn4124core/rtl/spartan6/p2l_des.vhd \
    ../../ip_cores/general-cores/modules/wishbone/wb_onewire_master/xwb_onewire_master.vhd \
    ../../modules/wr_streamers/escape_inserter.vhd \
    ../../ip_cores/general-cores/modules/wishbone/wb_uart/simple_uart_pkg.vhd \
    ../../ip_cores/general-cores/modules/wishbone/wb_simple_timer/xwb_tics.vhd \
    ../../ip_cores/general-cores/modules/wishbone/wb_uart/xwb_simple_uart.vhd \
    ../../ip_cores/etherbone-core/hdl/eb_slave_core/eb_tag_fifo.vhd \
    ../../ip_cores/general-cores/modules/wishbone/wb_slave_adapter/wb_slave_adapter.vhd \
    ../../modules/wr_endpoint/ep_leds_controller.vhd \
    ../../ip_cores/etherbone-core/hdl/eb_slave_core/eb_hdr_pkg.vhd \
    ../../modules/wr_eca/eca_walker.vhd \
    ../../ip_cores/general-cores/modules/common/gc_frequency_meter.vhd \
    ../../modules/wr_softpll_ng/softpll_pkg.vhd \
    ../../ip_cores/general-cores/modules/wishbone/wbgenplus/wbgenplus_pkg.vhd \
    ../../modules/wr_endpoint/ep_packet_filter.vhd \
    ../../ip_cores/etherbone-core/hdl/eb_slave_core/eb_fifo.vhd
    translate.tcl:
    echo $(TCL_OPEN) >> $@
    echo set process {Translate} >> $@
    echo process run '$$'process >> $@
    echo set result [process get '$$'process status] >> $@
    echo if { '$$'result == \"errors\" } { >> $@
    echo exit 1 >> $@
    echo } >> $@
    echo $(TCL_SAVE) >> $@
    echo $(TCL_CLOSE) >> $@
    #target for running synthesis in the remote location
    remote: __test_for_remote_synthesis_variables generate_tcl __send __do_synthesis
    __send_back: __do_synthesis
    __do_synthesis: __send
    __send: __test_for_remote_synthesis_variables
    translate: synthesize translate.tcl
    $(SYN_PRE_TRANSLATE_CMD)
    $(TCL_INTERPRETER) $@.tcl
    $(SYN_POST_TRANSLATE_CMD)
    touch $@
    __send:
    ssh $(USER)@$(SERVER) 'mkdir -p $(R_NAME)'
    rsync -e 'ssh -p $(PORT)' -Ravl $(foreach file, $(FILES), $(shell readlink -f $(file))) $(USER)@$(SERVER):$(R_NAME)
    map.tcl:
    echo $(TCL_OPEN) >> $@
    echo set process {Map} >> $@
    echo process run '$$'process >> $@
    echo set result [process get '$$'process status] >> $@
    echo if { '$$'result == \"errors\" } { >> $@
    echo exit 1 >> $@
    echo } >> $@
    echo $(TCL_SAVE) >> $@
    echo $(TCL_CLOSE) >> $@
    __do_synthesis:
    ifeq (x$(HDLMAKE_RSYNTH_USE_SCREEN), x1)
    ssh -t $(USER)@$(SERVER) 'screen bash -c "cd $(R_NAME)$(CWD) && $(HDLMAKE_RSYNTH_ISE_PATH)/xtclsh run.tcl"'
    else
    ssh $(USER)@$(SERVER) 'cd $(R_NAME)$(CWD) && $(HDLMAKE_RSYNTH_ISE_PATH)/xtclsh run.tcl'
    endif
    map: translate map.tcl
    $(SYN_PRE_MAP_CMD)
    $(TCL_INTERPRETER) $@.tcl
    $(SYN_POST_MAP_CMD)
    touch $@
    par.tcl:
    echo $(TCL_OPEN) >> $@
    echo set process {Place '&' Route} >> $@
    echo process run '$$'process >> $@
    echo set result [process get '$$'process status] >> $@
    echo if { '$$'result == \"errors\" } { >> $@
    echo exit 1 >> $@
    echo } >> $@
    echo $(TCL_SAVE) >> $@
    echo $(TCL_CLOSE) >> $@
    par: map par.tcl
    $(SYN_PRE_PAR_CMD)
    $(TCL_INTERPRETER) $@.tcl
    $(SYN_POST_PAR_CMD)
    touch $@
    bitstream.tcl:
    echo $(TCL_OPEN) >> $@
    echo set process {Generate Programming File} >> $@
    echo process run '$$'process >> $@
    echo set result [process get '$$'process status] >> $@
    echo if { '$$'result == \"errors\" } { >> $@
    echo exit 1 >> $@
    echo } >> $@
    echo $(TCL_SAVE) >> $@
    echo $(TCL_CLOSE) >> $@
    sync:
    cd .. && rsync -av $(USER)@$(SERVER):$(R_NAME)/$(CWD) . && cd $(CWD)
    bitstream: par bitstream.tcl
    $(SYN_PRE_BITSTREAM_CMD)
    $(TCL_INTERPRETER) $@.tcl
    $(SYN_POST_BITSTREAM_CMD)
    touch $@
    CLEAN_TARGETS := $(LIBS) xst xlnx_auto_0_xdb iseconfig _xmsgs _ngo *.b *_summary.html *.bld *.cmd_log *.drc *.lso *.ncd *.ngc *.ngd *.ngr *.pad *.par *.pcf *.prj *.ptwx *.stx *.syr *.twr *.twx *.gise *.gise *.bgn *.unroutes *.ut *.xpi *.xst *.xise *.xwbt *_envsettings.html *_guide.ncd *_map.map *_map.mrp *_map.ncd *_map.ngm *_map.xrpt *_ngdbuild.xrpt *_pad.csv *_pad.txt *_par.xrpt *_summary.xml *_usage.xml *_xst.xrpt usage_statistics_webtalk.html webtalk.log par_usage_statistics.html webtalk_pn.xml
    clean:
    rm -rf $(CLEAN_TARGETS)
    rm -rf project synthesize translate map par bitstream
    rm -rf project.tcl synthesize.tcl translate.tcl map.tcl par.tcl bitstream.tcl files.tcl
    #target for removing stuff from the remote location
    cleanremote:
    ssh $(USER)@$(SERVER) 'rm -rf $(R_NAME)'
    mrproper: clean
    rm -rf *.bit *.bin *.mcs
    .PHONY: mrproper clean all
    syn/cute_ref_design/cute_wr_ref.xise
    View file @ 958bb360
    This source diff could not be displayed because it is too large. You can view the blob instead.
    syn/spec_ref_design/spec_wr_ref.xise
    View file @ 958bb360
    ......@@ -17,804 +17,798 @@
    <files>
    <file xil_pn:name="../../board/common/wr_board_pkg.vhd" xil_pn:type="FILE_VHDL">
    <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="1"/>
    <association xil_pn:name="Implementation" xil_pn:seqID="189"/>
    <association xil_pn:name="Implementation" xil_pn:seqID="1"/>
    </file>
    <file xil_pn:name="../../board/common/xwrc_board_common.vhd" xil_pn:type="FILE_VHDL">
    <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="2"/>
    <association xil_pn:name="Implementation" xil_pn:seqID="194"/>
    <association xil_pn:name="Implementation" xil_pn:seqID="2"/>
    </file>
    <file xil_pn:name="../../board/spec/wr_spec_pkg.vhd" xil_pn:type="FILE_VHDL">
    <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="3"/>
    <association xil_pn:name="Implementation" xil_pn:seqID="193"/>
    <association xil_pn:name="Implementation" xil_pn:seqID="3"/>
    </file>
    <file xil_pn:name="../../board/spec/xwrc_board_spec.vhd" xil_pn:type="FILE_VHDL">
    <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="4"/>
    <association xil_pn:name="Implementation" xil_pn:seqID="197"/>
    <association xil_pn:name="Implementation" xil_pn:seqID="4"/>
    </file>
    <file xil_pn:name="../../ip_cores/etherbone-core/hdl/eb_slave_core/eb_cfg_fifo.vhd" xil_pn:type="FILE_VHDL">
    <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="5"/>
    <association xil_pn:name="Implementation" xil_pn:seqID="149"/>
    <association xil_pn:name="Implementation" xil_pn:seqID="5"/>
    </file>
    <file xil_pn:name="../../ip_cores/etherbone-core/hdl/eb_slave_core/eb_checksum.vhd" xil_pn:type="FILE_VHDL">
    <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="6"/>
    <association xil_pn:name="Implementation" xil_pn:seqID="148"/>
    <association xil_pn:name="Implementation" xil_pn:seqID="6"/>
    </file>
    <file xil_pn:name="../../ip_cores/etherbone-core/hdl/eb_slave_core/eb_commit_fifo.vhd" xil_pn:type="FILE_VHDL">
    <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="7"/>
    <association xil_pn:name="Implementation" xil_pn:seqID="147"/>
    <association xil_pn:name="Implementation" xil_pn:seqID="7"/>
    </file>
    <file xil_pn:name="../../ip_cores/etherbone-core/hdl/eb_slave_core/eb_eth_rx.vhd" xil_pn:type="FILE_VHDL">
    <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="8"/>
    <association xil_pn:name="Implementation" xil_pn:seqID="171"/>
    <association xil_pn:name="Implementation" xil_pn:seqID="8"/>
    </file>
    <file xil_pn:name="../../ip_cores/etherbone-core/hdl/eb_slave_core/eb_eth_tx.vhd" xil_pn:type="FILE_VHDL">
    <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="9"/>
    <association xil_pn:name="Implementation" xil_pn:seqID="170"/>
    <association xil_pn:name="Implementation" xil_pn:seqID="9"/>
    </file>
    <file xil_pn:name="../../ip_cores/etherbone-core/hdl/eb_slave_core/eb_ethernet_slave.vhd" xil_pn:type="FILE_VHDL">
    <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="10"/>
    <association xil_pn:name="Implementation" xil_pn:seqID="188"/>
    <association xil_pn:name="Implementation" xil_pn:seqID="10"/>
    </file>
    <file xil_pn:name="../../ip_cores/etherbone-core/hdl/eb_slave_core/eb_fifo.vhd" xil_pn:type="FILE_VHDL">
    <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="11"/>
    <association xil_pn:name="Implementation" xil_pn:seqID="120"/>
    <association xil_pn:name="Implementation" xil_pn:seqID="11"/>
    </file>
    <file xil_pn:name="../../ip_cores/etherbone-core/hdl/eb_slave_core/eb_hdr_pkg.vhd" xil_pn:type="FILE_VHDL">
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    <property xil_pn:name="Target Board for Hardware Co-Simulation" xil_pn:value="SP601 (JTAG)" xil_pn:valueState="default"/>
    <property xil_pn:name="Target Board for Hardware Co-Simulation" xil_pn:value="N/A" xil_pn:valueState="default"/>
    <property xil_pn:name="Target Simulator" xil_pn:value="Please Specify" xil_pn:valueState="default"/>
    <property xil_pn:name="Test Bench Module/Entity Name" xil_pn:value="testbench" xil_pn:valueState="default"/>
    <property xil_pn:name="Test Bench Target Language Xps" xil_pn:value="Verilog" xil_pn:valueState="default"/>
    ......@@ -1271,8 +1265,8 @@
    <property xil_pn:name="PROP_PostSynthSimTop" xil_pn:value="" xil_pn:valueState="default"/>
    <property xil_pn:name="PROP_PostXlateSimTop" xil_pn:value="" xil_pn:valueState="default"/>
    <property xil_pn:name="PROP_PreSynthesis" xil_pn:value="PreSynthesis" xil_pn:valueState="default"/>
    <property xil_pn:name="PROP_intProjectCreationTimestamp" xil_pn:value="2021-02-26T14:07:05" xil_pn:valueState="non-default"/>
    <property xil_pn:name="PROP_intWbtProjectID" xil_pn:value="254C4D00FF0E5140DE1B741E24DF3391" xil_pn:valueState="non-default"/>
    <property xil_pn:name="PROP_intProjectCreationTimestamp" xil_pn:value="2022-10-31T16:17:42" xil_pn:valueState="non-default"/>
    <property xil_pn:name="PROP_intWbtProjectID" xil_pn:value="C546E2A1C30C92EFFD0B7F5D6F4CD2BB" xil_pn:valueState="non-default"/>
    <property xil_pn:name="PROP_intWorkingDirLocWRTProjDir" xil_pn:value="Same" xil_pn:valueState="non-default"/>
    <property xil_pn:name="PROP_intWorkingDirUsed" xil_pn:value="No" xil_pn:valueState="non-default"/>
    </properties>
    ......
    syn/svec_ref_design/svec_wr_ref.xise
    View file @ 958bb360
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    syn/vxs_ref_design/vxs_wr_ref.xise
    View file @ 958bb360
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