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White Rabbit core collection
Commits
74e929a1
Commit
74e929a1
authored
Nov 08, 2018
by
Tomasz Wlostowski
Committed by
Grzegorz Daniluk
Aug 30, 2019
Browse files
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Plain Diff
platform: added low phase drift GTX PHY for Virtex6
parent
f0f79db0
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Showing
7 changed files
with
2643 additions
and
1 deletion
+2643
-1
Manifest.py
platform/xilinx/wr_gtp_phy/Manifest.py
+6
-1
gtx_comma_detect_lp.vhd
...r_gtp_phy/virtex6-low-phase-drift/gtx_comma_detect_lp.vhd
+199
-0
gtx_tx_reset_lp.vhd
...nx/wr_gtp_phy/virtex6-low-phase-drift/gtx_tx_reset_lp.vhd
+119
-0
whiterabbitgtx_wrapper_gtx_lp.vhd
...virtex6-low-phase-drift/whiterabbitgtx_wrapper_gtx_lp.vhd
+633
-0
wr_gtx_phy_virtex6_lp.vhd
...gtp_phy/virtex6-low-phase-drift/wr_gtx_phy_virtex6_lp.vhd
+567
-0
whiterabbitgtx_wrapper_gtx_old.vhd
...form/xilinx/wr_gtp_phy/whiterabbitgtx_wrapper_gtx_old.vhd
+631
-0
wr_gtx_phy_virtex6_old.vhd
platform/xilinx/wr_gtp_phy/wr_gtx_phy_virtex6_old.vhd
+488
-0
No files found.
platform/xilinx/wr_gtp_phy/Manifest.py
View file @
74e929a1
...
...
@@ -10,7 +10,12 @@ elif (syn_device[0:4].upper()=="XC6V"): # Virtex6
files
.
extend
([
"virtex6/wr_gtx_phy_virtex6.vhd"
,
"virtex6/whiterabbitgtx_wrapper_gtx.vhd"
,
"virtex6/gtp_phase_align_virtex6.vhd"
,
"virtex6/gtx_reset.vhd"
])
"virtex6/gtx_reset.vhd"
,
"virtex6-low-phase-drift/gtx_comma_detect_lp.vhd"
,
"virtex6-low-phase-drift/gtx_tx_reset_lp.vhd"
,
"virtex6-low-phase-drift/whiterabbitgtx_wrapper_gtx_lp.vhd"
,
"virtex6-low-phase-drift/wr_gtx_phy_virtex6_lp.vhd"
])
elif
(
syn_device
[
0
:
4
]
.
upper
()
==
"XC5V"
):
# Virtex5
files
.
extend
([
"virtex5/wr_gtp_phy_virtex5.vhd"
,
"virtex5/whiterabbit_gtp_wrapper_tile_virtex5.vhd"
,
...
...
platform/xilinx/wr_gtp_phy/virtex6-low-phase-drift/gtx_comma_detect_lp.vhd
0 → 100644
View file @
74e929a1
library
ieee
;
use
ieee
.
std_logic_1164
.
all
;
use
ieee
.
numeric_std
.
all
;
entity
gtx_comma_detect_lp
is
generic
(
g_ID
:
integer
);
port
(
clk_rx_i
:
in
std_logic
;
rst_i
:
in
std_logic
;
rx_data_raw_i
:
in
std_logic_vector
(
19
downto
0
);
link_up_o
:
out
std_logic
;
aligned_o
:
out
std_logic
;
rx_data_i
:
in
std_logic_vector
(
15
downto
0
);
rx_k_i
:
in
std_logic_vector
(
1
downto
0
);
rx_error_i
:
in
std_logic
);
end
gtx_comma_detect_lp
;
architecture
rtl
of
gtx_comma_detect_lp
is
type
t_state
is
(
SYNC_LOST
,
SYNC_CHECK
,
SYNC_ACQUIRED
);
constant
c_IDLE_LENGTH_UP
:
integer
:
=
40
;
constant
c_IDLE_LENGTH_LOSS
:
integer
:
=
1000
;
constant
c_COMMA_SHIFT_WE_WANT
:
std_logic_vector
(
6
downto
0
)
:
=
"0110000"
;
-- fixme
signal
rx_data_d0
:
std_logic_vector
(
19
downto
0
);
signal
rx_data_merged
:
std_logic_vector
(
49
downto
0
);
signal
first_comma
:
std_logic_vector
(
4
downto
0
);
signal
cnt
:
unsigned
(
15
downto
0
);
signal
state
:
t_state
;
signal
comma_found
:
std_logic_vector
(
19
downto
0
);
component
chipscope_icon
port
(
CONTROL0
:
inout
std_logic_vector
(
35
downto
0
));
end
component
;
component
chipscope_ila
port
(
CONTROL
:
inout
std_logic_vector
(
35
downto
0
);
CLK
:
in
std_logic
;
TRIG0
:
in
std_logic_vector
(
31
downto
0
);
TRIG1
:
in
std_logic_vector
(
31
downto
0
);
TRIG2
:
in
std_logic_vector
(
31
downto
0
);
TRIG3
:
in
std_logic_vector
(
31
downto
0
));
end
component
;
signal
CONTROL
:
std_logic_vector
(
35
downto
0
);
signal
TRIG0
:
std_logic_vector
(
31
downto
0
);
signal
TRIG1
:
std_logic_vector
(
31
downto
0
);
signal
TRIG2
:
std_logic_vector
(
31
downto
0
);
signal
TRIG3
:
std_logic_vector
(
31
downto
0
);
function
f_onehot_encode
(
x
:
std_logic_vector
;
output_bits
:
integer
)
return
std_logic_vector
is
variable
rv
:
std_logic_vector
(
output_bits
-1
downto
0
);
begin
for
i
in
0
to
x
'length
-1
loop
if
x
(
i
)
=
'1'
then
rv
:
=
std_logic_vector
(
to_unsigned
(
i
,
output_bits
));
return
rv
;
end
if
;
end
loop
;
return
std_logic_vector
(
to_unsigned
(
0
,
output_bits
));
end
f_onehot_encode
;
constant
c_K28_5_PLUS
:
std_logic_vector
(
9
downto
0
)
:
=
"1010000011"
;
signal
comma_pos
:
std_logic_vector
(
4
downto
0
);
signal
prev_comma_pos
:
std_logic_vector
(
4
downto
0
);
signal
prev_comma_pos_valid
:
std_logic
;
signal
comma_pos_valid
:
std_logic
;
signal
link_up
:
std_logic
;
signal
link_aligned
:
std_logic
;
begin
gen1
:
if
g_id
=
0
generate
--chipscope_icon_1 : chipscope_icon
-- port map (
-- CONTROL0 => CONTROL);
--chipscope_ila_1 : chipscope_ila
-- port map (
-- CONTROL => CONTROL,
-- CLK => clk_rx_i,
-- TRIG0 => TRIG0,
-- TRIG1 => TRIG1,
-- TRIG2 => TRIG2,
-- TRIG3 => TRIG3);
--trig0 (19 downto 0) <= rx_data_raw_i;
--trig1 (19 downto 0) <= comma_found;
--trig0(20) <= comma_pos_valid;
--trig0(21) <= link_up;
--trig0(22) <= link_aligned;
--trig2(15 downto 0) <= rx_data_i;
--trig2(17 downto 16) <= rx_k_i;
--trig2(18) <= rx_error_i;
end
generate
gen1
;
process
(
clk_rx_i
)
begin
if
rising_edge
(
clk_rx_i
)
then
if
rst_i
=
'1'
then
comma_found
<=
(
others
=>
'0'
);
else
rx_data_d0
<=
rx_data_raw_i
;
rx_data_merged
(
39
downto
0
)
<=
rx_data_d0
&
rx_data_raw_i
;
for
i
in
0
to
19
loop
if
rx_data_merged
(
i
+
9
downto
i
)
=
c_K28_5_PLUS
or
rx_data_merged
(
i
+
9
downto
i
)
=
(
not
c_K28_5_PLUS
)
then
comma_found
(
i
)
<=
'1'
;
else
comma_found
(
i
)
<=
'0'
;
end
if
;
end
loop
;
comma_pos
<=
f_onehot_encode
(
comma_found
,
comma_pos
'length
);
if
unsigned
(
comma_found
)
/=
0
then
comma_pos_valid
<=
'1'
;
else
comma_pos_valid
<=
'0'
;
end
if
;
end
if
;
end
if
;
end
process
;
process
(
clk_rx_i
)
begin
if
rising_edge
(
clk_rx_i
)
then
if
rst_i
=
'1'
then
state
<=
SYNC_LOST
;
else
case
state
is
when
SYNC_LOST
=>
link_up
<=
'0'
;
link_aligned
<=
'0'
;
if
comma_pos_valid
=
'1'
then
first_comma
<=
comma_pos
;
state
<=
SYNC_CHECK
;
cnt
<=
(
others
=>
'0'
);
end
if
;
when
SYNC_CHECK
=>
if
comma_pos
=
first_comma
and
comma_pos_valid
=
'1'
then
if
cnt
<
2
*
c_IDLE_LENGTH_UP
then
cnt
<=
cnt
+
4
;
end
if
;
elsif
cnt
>
0
then
cnt
<=
cnt
-
1
;
end
if
;
if
cnt
>=
c_IDLE_LENGTH_UP
then
state
<=
SYNC_ACQUIRED
;
cnt
<=
(
others
=>
'0'
);
end
if
;
when
SYNC_ACQUIRED
=>
link_up
<=
'1'
;
if
(
comma_pos_valid
=
'1'
and
comma_pos
=
first_comma
)
then
if
(
unsigned
(
comma_pos
)
=
0
)
then
link_aligned
<=
'1'
;
end
if
;
cnt
<=
(
others
=>
'0'
);
else
cnt
<=
cnt
+
1
;
if
cnt
=
c_IDLE_LENGTH_LOSS
then
state
<=
SYNC_LOST
;
end
if
;
end
if
;
end
case
;
end
if
;
end
if
;
end
process
;
aligned_o
<=
link_aligned
;
link_up_o
<=
link_up
;
end
rtl
;
platform/xilinx/wr_gtp_phy/virtex6-low-phase-drift/gtx_tx_reset_lp.vhd
0 → 100644
View file @
74e929a1
library
ieee
;
use
ieee
.
std_logic_1164
.
all
;
use
ieee
.
numeric_std
.
all
;
use
work
.
gencores_pkg
.
all
;
entity
gtx_tx_reset_lp
is
port
(
-- uncorrelated clock (we use DDMTD here) to ensure repeated resetting of
-- the TX path will sooner or later get to the TX divider bin we want
clk_dmtd_i
:
in
std_logic
;
-- TX clock
clk_tx_i
:
in
std_logic
;
-- Master reset (clk_tx_i domain)
rst_i
:
in
std_logic
;
-- Sw reset (treat as async)
rst_sw_i
:
in
std_logic
;
-- TX PLL lock detect
txpll_lockdet_i
:
in
std_logic
;
-- GTX TX divider reset
gtx_test_o
:
out
std_logic_vector
(
12
downto
0
);
-- GTX TX path reset (async)
gtx_tx_reset_o
:
out
std_logic
;
-- GTX TX reset done (also async)
gtx_tx_reset_done_i
:
in
std_logic
;
-- DOne indication
done_o
:
out
std_logic
);
end
gtx_tx_reset_lp
;
architecture
behavioral
of
gtx_tx_reset_lp
is
type
t_state
is
(
IDLE
,
PAUSE
,
FIRST_RST
,
PAUSE2
,
SECOND_RST
,
DONE
);
signal
state
:
t_state
;
signal
counter
:
unsigned
(
15
downto
0
);
begin
-- behavioral
process
(
clk_tx_i
)
begin
if
rising_edge
(
clk_tx_i
)
then
if
rst_i
=
'1'
then
state
<=
IDLE
;
counter
<=
(
others
=>
'0'
);
else
case
state
is
when
IDLE
=>
counter
<=
(
others
=>
'0'
);
gtx_test_o
<=
"1000000000000"
;
if
(
txpll_lockdet_i
=
'1'
)
then
state
<=
PAUSE
;
end
if
;
when
PAUSE
=>
counter
<=
counter
+
1
;
gtx_test_o
<=
"1000000000000"
;
if
(
counter
=
1024
)
then
state
<=
FIRST_RST
;
end
if
;
when
FIRST_RST
=>
counter
<=
counter
+
1
;
gtx_test_o
<=
"1000000000010"
;
if
(
counter
=
1024
+
256
)
then
state
<=
PAUSE2
;
end
if
;
when
PAUSE2
=>
counter
<=
counter
+
1
;
gtx_test_o
<=
"1000000000000"
;
if
(
counter
=
1024
+
2
*
256
)
then
state
<=
SECOND_RST
;
end
if
;
when
SECOND_RST
=>
counter
<=
counter
+
1
;
gtx_test_o
<=
"1000000000010"
;
if
(
counter
=
1024
+
3
*
256
)
then
state
<=
DONE
;
end
if
;
when
DONE
=>
gtx_test_o
<=
"1000000000000"
;
end
case
;
end
if
;
end
if
;
end
process
;
U_SyncResetSW
:
gc_sync_ffs
port
map
(
clk_i
=>
clk_dmtd_i
,
rst_n_i
=>
'1'
,
data_i
=>
rst_sw_i
,
ppulse_o
=>
gtx_tx_reset_o
);
U_SyncTxResetDone
:
gc_sync_ffs
port
map
(
clk_i
=>
clk_tx_i
,
rst_n_i
=>
'1'
,
data_i
=>
gtx_tx_reset_done_i
,
synced_o
=>
done_o
);
end
behavioral
;
platform/xilinx/wr_gtp_phy/virtex6-low-phase-drift/whiterabbitgtx_wrapper_gtx_lp.vhd
0 → 100644
View file @
74e929a1
-------------------------------------------------------------------------------
-- ____ ____
-- / /\/ /
-- /___/ \ / Vendor: Xilinx
-- \ \ \/ Version : 1.7
-- \ \ Application : Virtex-6 FPGA GTX Transceiver Wizard
-- / / Filename : whiterabbitgtx_wrapper_gtx.vhd
-- /___/ /\ Timestamp :
-- \ \ / \
-- \___\/\___\
--
--
-- Module WHITERABBITGTX_WRAPPER_GTX (a GTX Wrapper)
-- Generated by Xilinx Virtex-6 FPGA GTX Transceiver Wizard
--
--
-- (c) Copyright 2009-2010 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
library
ieee
;
use
ieee
.
std_logic_1164
.
all
;
use
ieee
.
numeric_std
.
all
;
library
UNISIM
;
use
UNISIM
.
VCOMPONENTS
.
all
;
--***************************** Entity Declaration ****************************
entity
WHITERABBITGTX_WRAPPER_GTX_LP
is
generic
(
-- Simulation attributes
GTX_SIM_GTXRESET_SPEEDUP
:
integer
:
=
0
;
-- Set to 1 to speed up sim reset
-- Share RX PLL parameter
GTX_TX_CLK_SOURCE
:
string
:
=
"TXPLL"
;
-- Save power parameter
GTX_POWER_SAVE
:
bit_vector
:
=
"0000110000"
);
port
(
------------------------ Loopback and Powerdown Ports ----------------------
LOOPBACK_IN
:
in
std_logic_vector
(
2
downto
0
);
----------------------- Receive Ports - 8b10b Decoder ----------------------
-- RXCHARISK_OUT : out std_logic_vector(1 downto 0);
-- RXDISPERR_OUT : out std_logic_vector(1 downto 0);
-- RXNOTINTABLE_OUT : out std_logic_vector(1 downto 0);
--------------- Receive Ports - Comma Detection and Alignment --------------
-- RXBYTEISALIGNED_OUT : out std_logic;
-- RXCOMMADET_OUT : out std_logic;
-- RXSLIDE_IN : in std_logic;
------------------- Receive Ports - RX Data Path interface -----------------
RXDATA_OUT
:
out
std_logic_vector
(
19
downto
0
);
RXRECCLK_OUT
:
out
std_logic
;
RXUSRCLK2_IN
:
in
std_logic
;
------- Receive Ports - RX Driver,OOB signalling,Coupling and Eq.,CDR ------
RXCDRRESET_IN
:
in
std_logic
;
RXN_IN
:
in
std_logic
;
RXP_IN
:
in
std_logic
;
------------------------ Receive Ports - RX PLL Ports ----------------------
GTXRXRESET_IN
:
in
std_logic
;
MGTREFCLKRX_IN
:
in
std_logic_vector
(
1
downto
0
);
PLLRXRESET_IN
:
in
std_logic
;
RXPLLLKDET_OUT
:
out
std_logic
;
RXRESETDONE_OUT
:
out
std_logic
;
---------------- Transmit Ports - 8b10b Encoder Control Ports --------------
TXCHARISK_IN
:
in
std_logic_vector
(
1
downto
0
);
------------------------- Transmit Ports - GTX Ports -----------------------
GTXTEST_IN
:
in
std_logic_vector
(
12
downto
0
);
------------------ Transmit Ports - TX Data Path interface -----------------
TXDATA_IN
:
in
std_logic_vector
(
15
downto
0
);
TXOUTCLK_OUT
:
out
std_logic
;
TXUSRCLK2_IN
:
in
std_logic
;
TXRUNDISP_OUT
:
out
std_logic_vector
(
1
downto
0
);
---------------- Transmit Ports - TX Driver and OOB signaling --------------
TXN_OUT
:
out
std_logic
;
TXP_OUT
:
out
std_logic
;
-------- Transmit Ports - TX Elastic Buffer and Phase Alignment Ports ------
TXDLYALIGNDISABLE_IN
:
in
std_logic
;
TXDLYALIGNMONENB_IN
:
in
std_logic
;
TXDLYALIGNMONITOR_OUT
:
out
std_logic_vector
(
7
downto
0
);
TXDLYALIGNRESET_IN
:
in
std_logic
;
TXENPMAPHASEALIGN_IN
:
in
std_logic
;
TXPMASETPHASE_IN
:
in
std_logic
;
----------------------- Transmit Ports - TX PLL Ports ----------------------
GTXTXRESET_IN
:
in
std_logic
;
MGTREFCLKTX_IN
:
in
std_logic_vector
(
1
downto
0
);
PLLTXRESET_IN
:
in
std_logic
;
TXPLLLKDET_OUT
:
out
std_logic
;
TXRESETDONE_OUT
:
out
std_logic
);
end
WHITERABBITGTX_WRAPPER_GTX_LP
;
architecture
RTL
of
WHITERABBITGTX_WRAPPER_GTX_LP
is
--**************************** Signal Declarations ****************************
-- ground and tied_to_vcc_i signals
signal
tied_to_ground_i
:
std_logic
;
signal
tied_to_ground_vec_i
:
std_logic_vector
(
63
downto
0
);
signal
tied_to_vcc_i
:
std_logic
;
-- RX Datapath signals
signal
rxdata_int
:
std_logic_vector
(
31
downto
0
);
signal
rxcharisk_int
:
std_logic_vector
(
3
downto
0
);
signal
rxdisperr_int
:
std_logic_vector
(
3
downto
0
);
-- TX Datapath signals
signal
txdata_i
:
std_logic_vector
(
31
downto
0
);
signal
txkerr_float_i
:
std_logic_vector
(
1
downto
0
);
signal
txrundisp_int
:
std_logic_vector
(
3
downto
0
);
--******************************** Main Body of Code***************************
begin
--------------------------- Static signal Assignments ---------------------
tied_to_ground_i
<=
'0'
;
tied_to_ground_vec_i
(
63
downto
0
)
<=
(
others
=>
'0'
);
tied_to_vcc_i
<=
'1'
;
------------------- GTX Datapath byte mapping -----------------
-- The GTX provides little endian data (first byte received on RXDATA(7 downto 0))
txdata_i
<=
(
tied_to_ground_vec_i
(
15
downto
0
)
&
TXDATA_IN
);
----------------------------- GTX Instance --------------------------
gtxe1_i
:
GTXE1
generic
map
(
--_______________________ Simulation-Only Attributes ___________________
SIM_RECEIVER_DETECT_PASS
=>
(
true
),
SIM_GTXRESET_SPEEDUP
=>
(
GTX_SIM_GTXRESET_SPEEDUP
),
SIM_TX_ELEC_IDLE_LEVEL
=>
(
"X"
),
SIM_VERSION
=>
(
"2.0"
),
SIM_TXREFCLK_SOURCE
=>
(
"000"
),
SIM_RXREFCLK_SOURCE
=>
(
"000"
),
----------------------------TX PLL----------------------------
TX_CLK_SOURCE
=>
(
GTX_TX_CLK_SOURCE
),
TX_OVERSAMPLE_MODE
=>
(
false
),
TXPLL_COM_CFG
=>
(
x"21680a"
),
TXPLL_CP_CFG
=>
(
x"0D"
),
TXPLL_DIVSEL_FB
=>
(
4
),
TXPLL_DIVSEL_OUT
=>
(
2
),
TXPLL_DIVSEL_REF
=>
(
1
),
TXPLL_DIVSEL45_FB
=>
(
5
),
TXPLL_LKDET_CFG
=>
(
"111"
),
TX_CLK25_DIVIDER
=>
(
3
),
TXPLL_SATA
=>
(
"00"
),
TX_TDCC_CFG
=>
(
"00"
),
PMA_CAS_CLK_EN
=>
(
false
),
POWER_SAVE
=>
(
GTX_POWER_SAVE
),
-------------------------TX Interface-------------------------
GEN_TXUSRCLK
=>
(
true
),
TX_DATA_WIDTH
=>
(
20
),
TX_USRCLK_CFG
=>
(
x"00"
),
TXOUTCLK_CTRL
=>
(
"TXOUTCLKPMA_DIV2"
),
TXOUTCLK_DLY
=>
(
"0000000000"
),
--------------TX Buffering and Phase Alignment----------------
TX_PMADATA_OPT
=>
(
'1'
),
PMA_TX_CFG
=>
(
x"80082"
),
TX_BUFFER_USE
=>
(
false
),
TX_BYTECLK_CFG
=>
(
x"00"
),
TX_EN_RATE_RESET_BUF
=>
(
true
),
TX_XCLK_SEL
=>
(
"TXUSR"
),
TX_DLYALIGN_CTRINC
=>
(
"0100"
),
TX_DLYALIGN_LPFINC
=>
(
"0110"
),
TX_DLYALIGN_MONSEL
=>
(
"000"
),
TX_DLYALIGN_OVRDSETTING
=>
(
"10000000"
),
-------------------------TX Gearbox---------------------------
GEARBOX_ENDEC
=>
(
"000"
),
TXGEARBOX_USE
=>
(
false
),
----------------TX Driver and OOB Signalling------------------
TX_DRIVE_MODE
=>
(
"DIRECT"
),
TX_IDLE_ASSERT_DELAY
=>
(
"100"
),
TX_IDLE_DEASSERT_DELAY
=>
(
"010"
),
TXDRIVE_LOOPBACK_HIZ
=>
(
false
),
TXDRIVE_LOOPBACK_PD
=>
(
false
),
--------------TX Pipe Control for PCI Express/SATA------------
COM_BURST_VAL
=>
(
"1111"
),
------------------TX Attributes for PCI Express---------------
TX_DEEMPH_0
=>
(
"11010"
),
TX_DEEMPH_1
=>
(
"10000"
),
TX_MARGIN_FULL_0
=>
(
"1001110"
),
TX_MARGIN_FULL_1
=>
(
"1001001"
),
TX_MARGIN_FULL_2
=>
(
"1000101"
),
TX_MARGIN_FULL_3
=>
(
"1000010"
),
TX_MARGIN_FULL_4
=>
(
"1000000"
),
TX_MARGIN_LOW_0
=>
(
"1000110"
),
TX_MARGIN_LOW_1
=>
(
"1000100"
),
TX_MARGIN_LOW_2
=>
(
"1000010"
),
TX_MARGIN_LOW_3
=>
(
"1000000"
),
TX_MARGIN_LOW_4
=>
(
"1000000"
),
----------------------------RX PLL----------------------------
RX_OVERSAMPLE_MODE
=>
(
false
),
RXPLL_COM_CFG
=>
(
x"21680a"
),
RXPLL_CP_CFG
=>
(
x"0D"
),
RXPLL_DIVSEL_FB
=>
(
4
),
RXPLL_DIVSEL_OUT
=>
(
2
),
RXPLL_DIVSEL_REF
=>
(
1
),
RXPLL_DIVSEL45_FB
=>
(
5
),
RXPLL_LKDET_CFG
=>
(
"111"
),
RX_CLK25_DIVIDER
=>
(
3
),
-------------------------RX Interface-------------------------
GEN_RXUSRCLK
=>
(
true
),
RX_DATA_WIDTH
=>
(
20
),
RXRECCLK_CTRL
=>
(
"RXRECCLKPMA_DIV2"
),
RXRECCLK_DLY
=>
(
"0000000000"
),
RXUSRCLK_DLY
=>
(
x"0000"
),
----------RX Driver,OOB signalling,Coupling and Eq.,CDR-------
AC_CAP_DIS
=>
(
true
),
CDR_PH_ADJ_TIME
=>
(
"10100"
),
OOBDETECT_THRESHOLD
=>
(
"011"
),
PMA_CDR_SCAN
=>
(
x"640404C"
),
PMA_RX_CFG
=>
(
x"05ce008"
),
RCV_TERM_GND
=>
(
false
),
RCV_TERM_VTTRX
=>
(
true
),
RX_EN_IDLE_HOLD_CDR
=>
(
false
),
RX_EN_IDLE_RESET_FR
=>
(
false
),
RX_EN_IDLE_RESET_PH
=>
(
false
),
TX_DETECT_RX_CFG
=>
(
x"1832"
),
TERMINATION_CTRL
=>
(
"00000"
),
TERMINATION_OVRD
=>
(
false
),
CM_TRIM
=>
(
"01"
),
PMA_RXSYNC_CFG
=>
(
x"00"
),
PMA_CFG
=>
(
x"0040000040000000003"
),
BGTEST_CFG
=>
(
"00"
),
BIAS_CFG
=>
(
x"00000"
),
--------------RX Decision Feedback Equalizer(DFE)-------------
DFE_CAL_TIME
=>
(
"01100"
),
DFE_CFG
=>
(
"00011011"
),
RX_EN_IDLE_HOLD_DFE
=>
(
true
),
RX_EYE_OFFSET
=>
(
x"4C"
),
RX_EYE_SCANMODE
=>
(
"00"
),
-------------------------PRBS Detection-----------------------
RXPRBSERR_LOOPBACK
=>
(
'0'
),
------------------Comma Detection and Alignment---------------
ALIGN_COMMA_WORD
=>
(
2
),
COMMA_10B_ENABLE
=>
(
"0001111111"
),
COMMA_DOUBLE
=>
(
false
),
DEC_MCOMMA_DETECT
=>
(
false
),
DEC_PCOMMA_DETECT
=>
(
false
),
DEC_VALID_COMMA_ONLY
=>
(
true
),
MCOMMA_10B_VALUE
=>
(
"1010000011"
),
MCOMMA_DETECT
=>
(
true
),
PCOMMA_10B_VALUE
=>
(
"0101111100"
),
PCOMMA_DETECT
=>
(
true
),
RX_DECODE_SEQ_MATCH
=>
(
true
),
RX_SLIDE_AUTO_WAIT
=>
(
5
),
RX_SLIDE_MODE
=>
(
"OFF"
),
-- SHOW_REALIGN_COMMA => (TRUE),
SHOW_REALIGN_COMMA
=>
(
false
),
-----------------RX Loss-of-sync State Machine----------------
RX_LOS_INVALID_INCR
=>
(
8
),
RX_LOS_THRESHOLD
=>
(
128
),
RX_LOSS_OF_SYNC_FSM
=>
(
false
),
-------------------------RX Gearbox---------------------------
RXGEARBOX_USE
=>
(
false
),
-------------RX Elastic Buffer and Phase alignment------------
RX_BUFFER_USE
=>
(
true
),
RX_EN_IDLE_RESET_BUF
=>
(
false
),
RX_EN_MODE_RESET_BUF
=>
(
true
),
RX_EN_RATE_RESET_BUF
=>
(
true
),
RX_EN_REALIGN_RESET_BUF
=>
(
false
),
RX_EN_REALIGN_RESET_BUF2
=>
(
false
),
RX_FIFO_ADDR_MODE
=>
(
"FULL"
),
RX_IDLE_HI_CNT
=>
(
"1000"
),
RX_IDLE_LO_CNT
=>
(
"0000"
),
RX_XCLK_SEL
=>
(
"RXREC"
),
RX_DLYALIGN_CTRINC
=>
(
"1110"
),
RX_DLYALIGN_EDGESET
=>
(
"00010"
),
RX_DLYALIGN_LPFINC
=>
(
"1110"
),
RX_DLYALIGN_MONSEL
=>
(
"000"
),
RX_DLYALIGN_OVRDSETTING
=>
(
"10000000"
),
------------------------Clock Correction----------------------
CLK_COR_ADJ_LEN
=>
(
1
),
CLK_COR_DET_LEN
=>
(
1
),
CLK_COR_INSERT_IDLE_FLAG
=>
(
false
),
CLK_COR_KEEP_IDLE
=>
(
false
),
CLK_COR_MAX_LAT
=>
(
16
),
CLK_COR_MIN_LAT
=>
(
14
),
CLK_COR_PRECEDENCE
=>
(
true
),
CLK_COR_REPEAT_WAIT
=>
(
0
),
CLK_COR_SEQ_1_1
=>
(
"0100000000"
),
CLK_COR_SEQ_1_2
=>
(
"0100000000"
),
CLK_COR_SEQ_1_3
=>
(
"0100000000"
),
CLK_COR_SEQ_1_4
=>
(
"0100000000"
),
CLK_COR_SEQ_1_ENABLE
=>
(
"1111"
),
CLK_COR_SEQ_2_1
=>
(
"0100000000"
),
CLK_COR_SEQ_2_2
=>
(
"0100000000"
),
CLK_COR_SEQ_2_3
=>
(
"0100000000"
),
CLK_COR_SEQ_2_4
=>
(
"0100000000"
),
CLK_COR_SEQ_2_ENABLE
=>
(
"1111"
),
CLK_COR_SEQ_2_USE
=>
(
false
),
CLK_CORRECT_USE
=>
(
false
),
------------------------Channel Bonding----------------------
CHAN_BOND_1_MAX_SKEW
=>
(
1
),
CHAN_BOND_2_MAX_SKEW
=>
(
1
),
CHAN_BOND_KEEP_ALIGN
=>
(
false
),
CHAN_BOND_SEQ_1_1
=>
(
"0000000000"
),
CHAN_BOND_SEQ_1_2
=>
(
"0000000000"
),
CHAN_BOND_SEQ_1_3
=>
(
"0000000000"
),
CHAN_BOND_SEQ_1_4
=>
(
"0000000000"
),
CHAN_BOND_SEQ_1_ENABLE
=>
(
"1111"
),
CHAN_BOND_SEQ_2_1
=>
(
"0000000000"
),
CHAN_BOND_SEQ_2_2
=>
(
"0000000000"
),
CHAN_BOND_SEQ_2_3
=>
(
"0000000000"
),
CHAN_BOND_SEQ_2_4
=>
(
"0000000000"
),
CHAN_BOND_SEQ_2_CFG
=>
(
"00000"
),
CHAN_BOND_SEQ_2_ENABLE
=>
(
"1111"
),
CHAN_BOND_SEQ_2_USE
=>
(
false
),
CHAN_BOND_SEQ_LEN
=>
(
1
),
PCI_EXPRESS_MODE
=>
(
false
),
-------------RX Attributes for PCI Express/SATA/SAS----------
SAS_MAX_COMSAS
=>
(
52
),
SAS_MIN_COMSAS
=>
(
40
),
SATA_BURST_VAL
=>
(
"100"
),
SATA_IDLE_VAL
=>
(
"100"
),
SATA_MAX_BURST
=>
(
9
),
SATA_MAX_INIT
=>
(
27
),
SATA_MAX_WAKE
=>
(
9
),
SATA_MIN_BURST
=>
(
5
),
SATA_MIN_INIT
=>
(
15
),
SATA_MIN_WAKE
=>
(
5
),
TRANS_TIME_FROM_P2
=>
(
x"03c"
),
TRANS_TIME_NON_P2
=>
(
x"19"
),
TRANS_TIME_RATE
=>
(
x"ff"
),
TRANS_TIME_TO_P2
=>
(
x"064"
)
)
port
map
(
------------------------ Loopback and Powerdown Ports ----------------------
LOOPBACK
=>
LOOPBACK_IN
,
RXPOWERDOWN
=>
"00"
,
TXPOWERDOWN
=>
"00"
,
-------------- Receive Ports - 64b66b and 64b67b Gearbox Ports -------------
RXDATAVALID
=>
open
,
RXGEARBOXSLIP
=>
tied_to_ground_i
,
RXHEADER
=>
open
,
RXHEADERVALID
=>
open
,
RXSTARTOFSEQ
=>
open
,
----------------------- Receive Ports - 8b10b Decoder ----------------------
RXCHARISCOMMA
=>
open
,
RXDISPERR
=>
rxdisperr_int
,
RXCHARISK
=>
rxcharisk_int
,
RXDEC8B10BUSE
=>
'0'
,
--tied_to_vcc_i,
RXNOTINTABLE
=>
open
,
RXRUNDISP
=>
open
,
USRCODEERR
=>
tied_to_ground_i
,
------------------- Receive Ports - Channel Bonding Ports ------------------
RXCHANBONDSEQ
=>
open
,
RXCHBONDI
=>
tied_to_ground_vec_i
(
3
downto
0
),
RXCHBONDLEVEL
=>
tied_to_ground_vec_i
(
2
downto
0
),
RXCHBONDMASTER
=>
tied_to_ground_i
,
RXCHBONDO
=>
open
,
RXCHBONDSLAVE
=>
tied_to_ground_i
,
RXENCHANSYNC
=>
tied_to_ground_i
,
------------------- Receive Ports - Clock Correction Ports -----------------
RXCLKCORCNT
=>
open
,
--------------- Receive Ports - Comma Detection and Alignment --------------
RXBYTEISALIGNED
=>
open
,
RXBYTEREALIGN
=>
open
,
RXCOMMADET
=>
open
,
RXCOMMADETUSE
=>
tied_to_vcc_i
,
RXENMCOMMAALIGN
=>
tied_to_ground_i
,
RXENPCOMMAALIGN
=>
tied_to_ground_i
,
RXSLIDE
=>
'0'
,
----------------------- Receive Ports - PRBS Detection ---------------------
PRBSCNTRESET
=>
tied_to_ground_i
,
RXENPRBSTST
=>
tied_to_ground_vec_i
(
2
downto
0
),
RXPRBSERR
=>
open
,
------------------- Receive Ports - RX Data Path interface -----------------
RXDATA
=>
rxdata_int
,
RXRECCLK
=>
RXRECCLK_OUT
,
RXRECCLKPCS
=>
open
,
RXRESET
=>
tied_to_ground_i
,
RXUSRCLK
=>
tied_to_ground_i
,
RXUSRCLK2
=>
RXUSRCLK2_IN
,
------------ Receive Ports - RX Decision Feedback Equalizer(DFE) -----------
DFECLKDLYADJ
=>
tied_to_ground_vec_i
(
5
downto
0
),
DFECLKDLYADJMON
=>
open
,
DFEDLYOVRD
=>
tied_to_vcc_i
,
DFEEYEDACMON
=>
open
,
DFESENSCAL
=>
open
,
DFETAP1
=>
tied_to_ground_vec_i
(
4
downto
0
),
DFETAP1MONITOR
=>
open
,
DFETAP2
=>
tied_to_ground_vec_i
(
4
downto
0
),
DFETAP2MONITOR
=>
open
,
DFETAP3
=>
tied_to_ground_vec_i
(
3
downto
0
),
DFETAP3MONITOR
=>
open
,
DFETAP4
=>
tied_to_ground_vec_i
(
3
downto
0
),
DFETAP4MONITOR
=>
open
,
DFETAPOVRD
=>
tied_to_vcc_i
,
------- Receive Ports - RX Driver,OOB signalling,Coupling and Eq.,CDR ------
GATERXELECIDLE
=>
tied_to_vcc_i
,
IGNORESIGDET
=>
tied_to_vcc_i
,
RXCDRRESET
=>
RXCDRRESET_IN
,
RXELECIDLE
=>
open
,
RXEQMIX
=>
"0000000000"
,
RXN
=>
RXN_IN
,
RXP
=>
RXP_IN
,
-------- Receive Ports - RX Elastic Buffer and Phase Alignment Ports -------
RXBUFRESET
=>
tied_to_ground_i
,
RXBUFSTATUS
=>
open
,
RXCHANISALIGNED
=>
open
,
RXCHANREALIGN
=>
open
,
RXDLYALIGNDISABLE
=>
'1'
,
RXDLYALIGNMONENB
=>
tied_to_ground_i
,
RXDLYALIGNMONITOR
=>
open
,
RXDLYALIGNOVERRIDE
=>
tied_to_vcc_i
,
RXDLYALIGNRESET
=>
tied_to_ground_i
,
RXDLYALIGNSWPPRECURB
=>
tied_to_vcc_i
,
RXDLYALIGNUPDSW
=>
tied_to_ground_i
,
RXENPMAPHASEALIGN
=>
tied_to_ground_i
,
RXPMASETPHASE
=>
tied_to_ground_i
,
RXSTATUS
=>
open
,
--------------- Receive Ports - RX Loss-of-sync State Machine --------------
RXLOSSOFSYNC
=>
open
,
---------------------- Receive Ports - RX Oversampling ---------------------
RXENSAMPLEALIGN
=>
tied_to_ground_i
,
RXOVERSAMPLEERR
=>
open
,
------------------------ Receive Ports - RX PLL Ports ----------------------
GREFCLKRX
=>
tied_to_ground_i
,
GTXRXRESET
=>
GTXRXRESET_IN
,
MGTREFCLKRX
=>
MGTREFCLKRX_IN
,
NORTHREFCLKRX
=>
tied_to_ground_vec_i
(
1
downto
0
),
PERFCLKRX
=>
tied_to_ground_i
,
PLLRXRESET
=>
PLLRXRESET_IN
,
RXPLLLKDET
=>
RXPLLLKDET_OUT
,
RXPLLLKDETEN
=>
tied_to_vcc_i
,
RXPLLPOWERDOWN
=>
tied_to_ground_i
,
RXPLLREFSELDY
=>
tied_to_ground_vec_i
(
2
downto
0
),
RXRATE
=>
tied_to_ground_vec_i
(
1
downto
0
),
RXRATEDONE
=>
open
,
RXRESETDONE
=>
RXRESETDONE_OUT
,
SOUTHREFCLKRX
=>
tied_to_ground_vec_i
(
1
downto
0
),
-------------- Receive Ports - RX Pipe Control for PCI Express -------------
PHYSTATUS
=>
open
,
RXVALID
=>
open
,
----------------- Receive Ports - RX Polarity Control Ports ----------------
RXPOLARITY
=>
tied_to_ground_i
,
--------------------- Receive Ports - RX Ports for SATA --------------------
COMINITDET
=>
open
,
COMSASDET
=>
open
,
COMWAKEDET
=>
open
,
------------- Shared Ports - Dynamic Reconfiguration Port (DRP) ------------
DADDR
=>
tied_to_ground_vec_i
(
7
downto
0
),
DCLK
=>
tied_to_ground_i
,
DEN
=>
tied_to_ground_i
,
DI
=>
tied_to_ground_vec_i
(
15
downto
0
),
DRDY
=>
open
,
DRPDO
=>
open
,
DWE
=>
tied_to_ground_i
,
-------------- Transmit Ports - 64b66b and 64b67b Gearbox Ports ------------
TXGEARBOXREADY
=>
open
,
TXHEADER
=>
tied_to_ground_vec_i
(
2
downto
0
),
TXSEQUENCE
=>
tied_to_ground_vec_i
(
6
downto
0
),
TXSTARTSEQ
=>
tied_to_ground_i
,
---------------- Transmit Ports - 8b10b Encoder Control Ports --------------
TXBYPASS8B10B
=>
tied_to_ground_vec_i
(
3
downto
0
),
TXCHARDISPMODE
=>
tied_to_ground_vec_i
(
3
downto
0
),
TXCHARDISPVAL
=>
tied_to_ground_vec_i
(
3
downto
0
),
TXCHARISK
(
3
downto
2
)
=>
tied_to_ground_vec_i
(
1
downto
0
),
TXCHARISK
(
1
downto
0
)
=>
TXCHARISK_IN
,
TXENC8B10BUSE
=>
tied_to_vcc_i
,
TXKERR
=>
open
,
TXRUNDISP
=>
txrundisp_int
,
------------------------- Transmit Ports - GTX Ports -----------------------
GTXTEST
=>
GTXTEST_IN
,
MGTREFCLKFAB
=>
open
,
TSTCLK0
=>
tied_to_ground_i
,
TSTCLK1
=>
tied_to_ground_i
,
TSTIN
=>
"11111111111111111111"
,
TSTOUT
=>
open
,
------------------ Transmit Ports - TX Data Path interface -----------------
TXDATA
=>
txdata_i
,
TXOUTCLK
=>
TXOUTCLK_OUT
,
TXOUTCLKPCS
=>
open
,
TXRESET
=>
tied_to_ground_i
,
TXUSRCLK
=>
tied_to_ground_i
,
TXUSRCLK2
=>
TXUSRCLK2_IN
,
---------------- Transmit Ports - TX Driver and OOB signaling --------------
TXBUFDIFFCTRL
=>
"100"
,
TXDIFFCTRL
=>
"1101"
,
TXINHIBIT
=>
tied_to_ground_i
,
TXN
=>
TXN_OUT
,
TXP
=>
TXP_OUT
,
TXPOSTEMPHASIS
=>
"00000"
,
--------------- Transmit Ports - TX Driver and OOB signalling --------------
TXPREEMPHASIS
=>
"0000"
,
----------- Transmit Ports - TX Elastic Buffer and Phase Alignment ---------
TXBUFSTATUS
=>
open
,
-------- Transmit Ports - TX Elastic Buffer and Phase Alignment Ports ------
TXDLYALIGNDISABLE
=>
TXDLYALIGNDISABLE_IN
,
TXDLYALIGNMONENB
=>
TXDLYALIGNMONENB_IN
,
TXDLYALIGNMONITOR
=>
TXDLYALIGNMONITOR_OUT
,
TXDLYALIGNOVERRIDE
=>
tied_to_ground_i
,
TXDLYALIGNRESET
=>
TXDLYALIGNRESET_IN
,
TXDLYALIGNUPDSW
=>
tied_to_ground_i
,
TXENPMAPHASEALIGN
=>
TXENPMAPHASEALIGN_IN
,
TXPMASETPHASE
=>
TXPMASETPHASE_IN
,
----------------------- Transmit Ports - TX PLL Ports ----------------------
GREFCLKTX
=>
tied_to_ground_i
,
GTXTXRESET
=>
GTXTXRESET_IN
,
MGTREFCLKTX
=>
MGTREFCLKTX_IN
,
NORTHREFCLKTX
=>
tied_to_ground_vec_i
(
1
downto
0
),
PERFCLKTX
=>
tied_to_ground_i
,
PLLTXRESET
=>
PLLTXRESET_IN
,
SOUTHREFCLKTX
=>
tied_to_ground_vec_i
(
1
downto
0
),
TXPLLLKDET
=>
TXPLLLKDET_OUT
,
TXPLLLKDETEN
=>
tied_to_vcc_i
,
TXPLLPOWERDOWN
=>
tied_to_ground_i
,
TXPLLREFSELDY
=>
tied_to_ground_vec_i
(
2
downto
0
),
TXRATE
=>
tied_to_ground_vec_i
(
1
downto
0
),
TXRATEDONE
=>
open
,
TXRESETDONE
=>
TXRESETDONE_OUT
,
--------------------- Transmit Ports - TX PRBS Generator -------------------
TXENPRBSTST
=>
tied_to_ground_vec_i
(
2
downto
0
),
TXPRBSFORCEERR
=>
tied_to_ground_i
,
-------------------- Transmit Ports - TX Polarity Control ------------------
TXPOLARITY
=>
tied_to_ground_i
,
----------------- Transmit Ports - TX Ports for PCI Express ----------------
TXDEEMPH
=>
tied_to_ground_i
,
TXDETECTRX
=>
tied_to_ground_i
,
TXELECIDLE
=>
tied_to_ground_i
,
TXMARGIN
=>
tied_to_ground_vec_i
(
2
downto
0
),
TXPDOWNASYNCH
=>
tied_to_ground_i
,
TXSWING
=>
tied_to_ground_i
,
--------------------- Transmit Ports - TX Ports for SATA -------------------
COMFINISH
=>
open
,
TXCOMINIT
=>
tied_to_ground_i
,
TXCOMSAS
=>
tied_to_ground_i
,
TXCOMWAKE
=>
tied_to_ground_i
);
TXRUNDISP_OUT
<=
txrundisp_int
(
1
downto
0
);
RXDATA_OUT
(
19
)
<=
rxdisperr_int
(
1
);
RXDATA_OUT
(
18
)
<=
rxcharisk_int
(
1
);
RXDATA_OUT
(
17
downto
10
)
<=
rxdata_int
(
15
downto
8
);
RXDATA_OUT
(
9
)
<=
rxdisperr_int
(
0
);
RXDATA_OUT
(
8
)
<=
rxcharisk_int
(
0
);
RXDATA_OUT
(
7
downto
0
)
<=
rxdata_int
(
7
downto
0
);
end
RTL
;
platform/xilinx/wr_gtp_phy/virtex6-low-phase-drift/wr_gtx_phy_virtex6_lp.vhd
0 → 100644
View file @
74e929a1
-------------------------------------------------------------------------------
-- Title : Deterministic Xilinx GTP wrapper - Spartan-6 top module
-- Project : White Rabbit Switch
-------------------------------------------------------------------------------
-- File : wr_gtp_phy_spartan6.vhd
-- Author : Tomasz Wlostowski
-- Company : CERN BE-CO-HT
-- Created : 2010-11-18
-- Last update: 2018-07-05
-- Platform : FPGA-generic
-- Standard : VHDL'93
-------------------------------------------------------------------------------
-- Description: Dual channel wrapper for Xilinx Spartan-6 GTP adapted for
-- deterministic delays at 1.25 Gbps.
-------------------------------------------------------------------------------
--
-- Copyright (c) 2010 CERN / Tomasz Wlostowski
--
-- This source file is free software; you can redistribute it
-- and/or modify it under the terms of the GNU Lesser General
-- Public License as published by the Free Software Foundation;
-- either version 2.1 of the License, or (at your option) any
-- later version.
--
-- This source is distributed in the hope that it will be
-- useful, but WITHOUT ANY WARRANTY; without even the implied
-- warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR
-- PURPOSE. See the GNU Lesser General Public License for more
-- details.
--
-- You should have received a copy of the GNU Lesser General
-- Public License along with this source; if not, download it
-- from http://www.gnu.org/licenses/lgpl-2.1.html
--
--
-------------------------------------------------------------------------------
-- Revisions :
-- Date Version Author Description
-- 2010-11-18 0.4 twlostow Initial release
-- 2011-02-07 0.5 twlostow Verified on Spartan6 GTP (single channel only)
-------------------------------------------------------------------------------
library
ieee
;
use
ieee
.
std_logic_1164
.
all
;
use
ieee
.
numeric_std
.
all
;
library
unisim
;
use
unisim
.
vcomponents
.
all
;
library
work
;
use
work
.
gencores_pkg
.
all
;
use
work
.
disparity_gen_pkg
.
all
;
entity
wr_gtx_phy_virtex6_lp
is
generic
(
-- set to non-zero value to speed up the simulation by reducing some delays
g_simulation
:
integer
:
=
0
;
g_use_slave_tx_clock
:
integer
:
=
0
;
g_use_bufr
:
boolean
:
=
false
;
g_id
:
integer
:
=
0
);
port
(
-- Reference 62.5 MHz clock input for the TX/RX logic (not the GTX itself)
clk_ref_i
:
in
std_logic
;
-- Reference 62.5 MHz clock for the GTX transceiver
clk_gtx_i
:
in
std_logic
;
-- DMTD clock for phase measurements (done in the PHY module as we need to
-- multiplex between several GTX clock outputs)
clk_dmtd_i
:
in
std_logic
;
-- TX path, clk_ref_i - synchronous:
-- data input (8 bits, not 8b10b-encoded)
tx_data_i
:
in
std_logic_vector
(
15
downto
0
);
-- 1 when tx_data_i contains a control code, 0 when it's a data byte
tx_k_i
:
in
std_logic_vector
(
1
downto
0
);
-- disparity of the currently transmitted 8b10b code (1 = plus, 0 = minus).
-- Necessary for the PCS to generate proper frame termination sequences.
-- Generated for the 2nd byte (LSB) of tx_data_i.
tx_disparity_o
:
out
std_logic
;
-- Encoding error indication (1 = error, 0 = no error)
tx_enc_err_o
:
out
std_logic
;
-- RX path, synchronous to ch0_rx_rbclk_o.
-- RX recovered clock
rx_rbclk_o
:
out
std_logic
;
rx_rbclk_sampled_o
:
out
std_logic
;
-- 8b10b-decoded data output. The data output must be kept invalid before
-- the transceiver is locked on the incoming signal to prevent the EP from
-- detecting a false carrier.
rx_data_o
:
out
std_logic_vector
(
15
downto
0
);
-- 1 when the byte on rx_data_o is a control code
rx_k_o
:
out
std_logic_vector
(
1
downto
0
);
-- encoding error indication
rx_enc_err_o
:
out
std_logic
;
-- RX bitslide indication, indicating the delay of the RX path of the
-- transceiver (in UIs). Must be valid when ch0_rx_data_o is valid.
rx_bitslide_o
:
out
std_logic_vector
(
4
downto
0
);
-- reset input, active hi
rst_i
:
in
std_logic
;
loopen_i
:
in
std_logic
;
pad_txn_o
:
out
std_logic
;
pad_txp_o
:
out
std_logic
;
pad_rxn_i
:
in
std_logic
:
=
'0'
;
pad_rxp_i
:
in
std_logic
:
=
'0'
;
rdy_o
:
out
std_logic
;
debug_i
:
in
std_logic_vector
(
15
downto
0
)
:
=
x"0000"
;
debug_o
:
out
std_logic_vector
(
15
downto
0
);
TX_CLK_o
:
out
std_logic
);
end
wr_gtx_phy_virtex6_lp
;
architecture
rtl
of
wr_gtx_phy_virtex6_lp
is
signal
rx_data_o_int
:
std_logic_vector
(
15
downto
0
);
signal
rx_k_o_int
:
std_logic_vector
(
1
downto
0
);
signal
rx_enc_err_o_int
:
std_logic
;
component
WHITERABBITGTX_WRAPPER_GTX_LP
generic
(
GTX_SIM_GTXRESET_SPEEDUP
:
integer
;
GTX_TX_CLK_SOURCE
:
string
;
GTX_POWER_SAVE
:
bit_vector
);
port
(
LOOPBACK_IN
:
in
std_logic_vector
(
2
downto
0
);
-- RXCHARISK_OUT : out std_logic_vector(1 downto 0);
-- RXDISPERR_OUT : out std_logic_vector(1 downto 0);
-- RXNOTINTABLE_OUT : out std_logic_vector(1 downto 0);
-- RXBYTEISALIGNED_OUT : out std_logic;
-- RXCOMMADET_OUT : out std_logic;
-- RXSLIDE_IN : in std_logic;
RXDATA_OUT
:
out
std_logic_vector
(
19
downto
0
);
RXRECCLK_OUT
:
out
std_logic
;
RXUSRCLK2_IN
:
in
std_logic
;
RXCDRRESET_IN
:
in
std_logic
;
RXN_IN
:
in
std_logic
;
RXP_IN
:
in
std_logic
;
GTXRXRESET_IN
:
in
std_logic
;
MGTREFCLKRX_IN
:
in
std_logic_vector
(
1
downto
0
);
PLLRXRESET_IN
:
in
std_logic
;
RXPLLLKDET_OUT
:
out
std_logic
;
RXRESETDONE_OUT
:
out
std_logic
;
TXCHARISK_IN
:
in
std_logic_vector
(
1
downto
0
);
GTXTEST_IN
:
in
std_logic_vector
(
12
downto
0
);
TXDATA_IN
:
in
std_logic_vector
(
15
downto
0
);
TXOUTCLK_OUT
:
out
std_logic
;
TXUSRCLK2_IN
:
in
std_logic
;
TXRUNDISP_OUT
:
out
std_logic_vector
(
1
downto
0
);
TXN_OUT
:
out
std_logic
;
TXP_OUT
:
out
std_logic
;
TXDLYALIGNDISABLE_IN
:
in
std_logic
;
TXDLYALIGNMONENB_IN
:
in
std_logic
;
TXDLYALIGNMONITOR_OUT
:
out
std_logic_vector
(
7
downto
0
);
TXDLYALIGNRESET_IN
:
in
std_logic
;
TXENPMAPHASEALIGN_IN
:
in
std_logic
;
TXPMASETPHASE_IN
:
in
std_logic
;
GTXTXRESET_IN
:
in
std_logic
;
MGTREFCLKTX_IN
:
in
std_logic_vector
(
1
downto
0
);
PLLTXRESET_IN
:
in
std_logic
;
TXPLLLKDET_OUT
:
out
std_logic
;
TXRESETDONE_OUT
:
out
std_logic
);
end
component
;
component
BUFG
port
(
O
:
out
std_ulogic
;
I
:
in
std_ulogic
);
end
component
;
component
BUFR
generic
(
BUFR_DIVIDE
:
string
:
=
"BYPASS"
;
SIM_DEVICE
:
string
:
=
"VIRTEX6"
);
port
(
O
:
out
std_ulogic
;
CE
:
in
std_ulogic
:
=
'1'
;
CLR
:
in
std_ulogic
:
=
'0'
;
I
:
in
std_ulogic
);
end
component
;
component
dmtd_sampler
is
generic
(
g_divide_input_by_2
:
boolean
;
g_reverse
:
boolean
);
port
(
clk_in_i
:
in
std_logic
;
clk_dmtd_i
:
in
std_logic
;
clk_sampled_o
:
out
std_logic
);
end
component
dmtd_sampler
;
signal
gtx_rst
:
std_logic
;
signal
gtx_loopback
:
std_logic_vector
(
2
downto
0
);
signal
gtx_reset_done
:
std_logic
;
signal
gtx_pll_lockdet
:
std_logic
;
signal
rst_synced
:
std_logic
;
signal
rst_d0
:
std_logic
;
signal
reset_counter
:
unsigned
(
9
downto
0
);
signal
gtx_test
:
std_logic_vector
(
12
downto
0
);
signal
rx_rec_clk_bufin
:
std_logic
;
signal
rx_rec_clk
:
std_logic
;
signal
rx_comma_det
:
std_logic
;
signal
rx_byte_is_aligned
:
std_logic
;
signal
tx_dly_align_disable
:
std_logic
;
signal
tx_dly_align_reset
:
std_logic
;
signal
tx_en_pma_phase_align
:
std_logic
;
signal
tx_pma_set_phase
:
std_logic
;
signal
align_enable
:
std_logic
;
signal
align_done
:
std_logic
;
signal
gtx_tx_rst_done
,
rx_rst_done
:
std_logic
;
signal
txpll_lockdet
,
rxpll_lockdet
:
std_logic
;
signal
pll_lockdet
:
std_logic
;
signal
serdes_ready
:
std_logic
;
signal
rx_slide
:
std_logic
;
signal
rx_cdr_rst
:
std_logic
;
signal
rx_synced
:
std_logic
;
signal
rst_done
:
std_logic
;
signal
everything_ready
:
std_logic
;
signal
mgtrefclk_in
:
std_logic_vector
(
1
downto
0
);
signal
rx_k_int
:
std_logic_vector
(
1
downto
0
);
signal
rx_data_int
:
std_logic_vector
(
15
downto
0
);
signal
rx_data_raw
:
std_logic_vector
(
19
downto
0
);
signal
rx_disp_err
,
rx_code_err
:
std_logic_vector
(
1
downto
0
);
signal
tx_is_k_swapped
:
std_logic_vector
(
1
downto
0
);
signal
tx_data_swapped
:
std_logic_vector
(
15
downto
0
);
signal
cur_disp
:
t_8b10b_disparity
;
signal
tx_out_clk
,
tx_out_clk_buf
:
std_logic
;
signal
rx_rec_clk_sampled
,
tx_out_clk_sampled
:
std_logic
;
signal
tx_rundisp_v6
:
std_logic_vector
(
1
downto
0
);
signal
gtx_tx_reset_a
:
std_logic
;
signal
tx_reset_done
:
std_logic
;
signal
link_up
,
link_aligned
:
std_logic
;
signal
tx_enable
,
tx_enable_refclk
:
std_logic
;
signal
tx_sw_reset
:
std_logic
;
signal
rx_enable
,
rx_enable_rxclk
:
std_logic
;
signal
gtx_rx_rst_a
:
std_logic
;
signal
rx_sw_reset
:
std_logic
;
function
f_reverse_bits
(
x
:
std_logic_vector
)
return
std_logic_vector
is
variable
rv
:
std_logic_vector
(
x
'reverse_range
);
begin
for
i
in
x
'range
loop
rv
(
i
)
:
=
x
(
i
);
end
loop
;
return
rv
;
end
f_reverse_bits
;
signal
gtx_rst_n
:
std_logic
;
begin
-- rtl
tx_sw_reset
<=
debug_i
(
0
);
tx_enable
<=
debug_i
(
1
);
rx_enable
<=
debug_i
(
2
);
rx_sw_reset
<=
debug_i
(
3
);
U_SyncTxEnable
:
gc_sync_ffs
port
map
(
clk_i
=>
clk_ref_i
,
rst_n_i
=>
'1'
,
data_i
=>
tx_enable
,
synced_o
=>
tx_enable_refclk
);
U_SyncRxEnable
:
gc_sync_ffs
port
map
(
clk_i
=>
rx_rec_clk
,
rst_n_i
=>
'1'
,
data_i
=>
rx_enable
,
synced_o
=>
rx_enable_rxclk
);
U_SyncRxReset
:
gc_sync_ffs
port
map
(
clk_i
=>
clk_dmtd_i
,
rst_n_i
=>
'1'
,
data_i
=>
rx_sw_reset
,
synced_o
=>
gtx_rx_rst_a
);
BUFR_1
:
BUFG
port
map
(
O
=>
tx_out_clk
,
I
=>
tx_out_clk_buf
);
TX_CLK_o
<=
tx_out_clk
;
U_Sampler_RX
:
dmtd_sampler
generic
map
(
g_divide_input_by_2
=>
false
,
g_reverse
=>
true
)
port
map
(
clk_in_i
=>
rx_rec_clk
,
clk_dmtd_i
=>
clk_dmtd_i
,
clk_sampled_o
=>
rx_rec_clk_sampled
);
U_Sampler_TX
:
dmtd_sampler
generic
map
(
g_divide_input_by_2
=>
false
,
g_reverse
=>
true
)
port
map
(
clk_in_i
=>
tx_out_clk
,
clk_dmtd_i
=>
clk_dmtd_i
,
clk_sampled_o
=>
tx_out_clk_sampled
);
process
(
rx_rec_clk_sampled
,
tx_out_clk_sampled
,
debug_i
)
begin
case
debug_i
(
15
downto
14
)
is
when
"00"
=>
rx_rbclk_sampled_o
<=
rx_rec_clk_sampled
;
when
"01"
=>
rx_rbclk_sampled_o
<=
tx_out_clk_sampled
;
when
others
=>
rx_rbclk_sampled_o
<=
'0'
;
end
case
;
end
process
;
tx_enc_err_o
<=
'0'
;
-- Near-end PMA loopback if loopen_i active
gtx_loopback
<=
"010"
when
loopen_i
=
'1'
else
"000"
;
p_gen_reset
:
process
(
clk_ref_i
)
begin
if
rising_edge
(
clk_ref_i
)
then
rst_d0
<=
rst_i
;
rst_synced
<=
rst_d0
;
if
(
rst_synced
=
'1'
)
then
reset_counter
<=
(
others
=>
'0'
);
else
if
(
reset_counter
(
reset_counter
'left
)
=
'0'
)
then
reset_counter
<=
reset_counter
+
1
;
end
if
;
end
if
;
end
if
;
end
process
;
gtx_rst
<=
rst_synced
or
std_logic
(
not
reset_counter
(
reset_counter
'left
));
U_Tx_Reset_Gen
:
entity
work
.
gtx_tx_reset_lp
port
map
(
clk_dmtd_i
=>
clk_dmtd_i
,
clk_tx_i
=>
clk_ref_i
,
rst_i
=>
gtx_rst
,
rst_sw_i
=>
tx_sw_reset
,
txpll_lockdet_i
=>
txpll_lockdet
,
gtx_test_o
=>
gtx_test
,
gtx_tx_reset_o
=>
gtx_tx_reset_a
,
gtx_tx_reset_done_i
=>
gtx_tx_rst_done
,
done_o
=>
tx_reset_done
);
debug_o
(
0
)
<=
tx_reset_done
;
gen_rx_bufg
:
if
(
g_use_bufr
=
false
)
generate
U_BUF_RxRecClk
:
BUFG
port
map
(
I
=>
rx_rec_clk_bufin
,
O
=>
rx_rec_clk
);
end
generate
gen_rx_bufg
;
gen_rx_bufr
:
if
(
g_use_bufr
=
true
)
generate
U_BUF_RxRecClk
:
BUFR
port
map
(
I
=>
rx_rec_clk_bufin
,
O
=>
rx_rec_clk
);
end
generate
gen_rx_bufr
;
rx_rbclk_o
<=
rx_rec_clk
;
process
(
clk_ref_i
)
begin
if
rising_edge
(
clk_ref_i
)
then
if
tx_enable_refclk
=
'0'
then
tx_is_k_swapped
<=
"00"
;
tx_data_swapped
<=
(
others
=>
'0'
);
else
tx_is_k_swapped
<=
tx_k_i
(
0
)
&
tx_k_i
(
1
);
tx_data_swapped
<=
tx_data_i
(
7
downto
0
)
&
tx_data_i
(
15
downto
8
);
end
if
;
end
if
;
end
process
;
U_GTX_INST
:
WHITERABBITGTX_WRAPPER_GTX_LP
generic
map
(
GTX_SIM_GTXRESET_SPEEDUP
=>
1
,
GTX_TX_CLK_SOURCE
=>
"TXPLL"
,
GTX_POWER_SAVE
=>
"0000110000"
)
port
map
(
LOOPBACK_IN
=>
gtx_loopback
,
-- RXCHARISK_OUT => rx_k_int,
-- RXDISPERR_OUT => rx_disp_err,
-- RXNOTINTABLE_OUT => rx_code_err,
-- RXBYTEISALIGNED_OUT => open,
-- RXCOMMADET_OUT => open,
-- RXSLIDE_IN => '0',
RXDATA_OUT
=>
rx_data_raw
,
RXRECCLK_OUT
=>
rx_rec_clk_bufin
,
RXUSRCLK2_IN
=>
rx_rec_clk
,
RXCDRRESET_IN
=>
'0'
,
RXN_IN
=>
pad_rxn_i
,
RXP_IN
=>
pad_rxp_i
,
GTXRXRESET_IN
=>
gtx_rx_rst_a
,
MGTREFCLKRX_IN
=>
mgtrefclk_in
,
PLLRXRESET_IN
=>
'0'
,
RXPLLLKDET_OUT
=>
rxpll_lockdet
,
RXRESETDONE_OUT
=>
rx_rst_done
,
TXCHARISK_IN
=>
tx_is_k_swapped
,
GTXTEST_IN
=>
gtx_test
,
TXDATA_IN
=>
tx_data_swapped
,
TXOUTCLK_OUT
=>
tx_out_clk_buf
,
TXUSRCLK2_IN
=>
clk_ref_i
,
TXRUNDISP_OUT
=>
open
,
TXN_OUT
=>
pad_txn_o
,
TXP_OUT
=>
pad_txp_o
,
TXDLYALIGNDISABLE_IN
=>
'1'
,
TXDLYALIGNMONENB_IN
=>
'1'
,
TXDLYALIGNMONITOR_OUT
=>
open
,
TXDLYALIGNRESET_IN
=>
'0'
,
TXENPMAPHASEALIGN_IN
=>
'0'
,
TXPMASETPHASE_IN
=>
'0'
,
GTXTXRESET_IN
=>
gtx_tx_reset_a
,
MGTREFCLKTX_IN
=>
mgtrefclk_in
,
PLLTXRESET_IN
=>
'0'
,
TXPLLLKDET_OUT
=>
txpll_lockdet
,
TXRESETDONE_OUT
=>
gtx_tx_rst_done
);
mgtrefclk_in
<=
'0'
&
clk_gtx_i
;
rx_synced
<=
'0'
;
rst_done
<=
rx_rst_done
and
tx_reset_done
;
pll_lockdet
<=
txpll_lockdet
and
rxpll_lockdet
;
serdes_ready
<=
rst_done
and
pll_lockdet
;
align_enable
<=
serdes_ready
;
everything_ready
<=
serdes_ready
and
align_done
;
rdy_o
<=
serdes_ready
;
--everything_ready;
U_Comma_Detect
:
entity
work
.
gtx_comma_detect_lp
generic
map
(
g_id
=>
g_id
)
port
map
(
clk_rx_i
=>
rx_rec_clk
,
rst_i
=>
gtx_rst
,
rx_data_raw_i
=>
rx_data_raw
,
link_up_o
=>
link_up
,
aligned_o
=>
link_aligned
,
rx_data_i
=>
rx_data_o_int
,
rx_k_i
=>
rx_k_o_int
,
rx_error_i
=>
rx_enc_err_o_int
);
gtx_rst_n
<=
not
gtx_rst
;
U_Dec1
:
gc_dec_8b10b
port
map
(
clk_i
=>
rx_rec_clk
,
rst_n_i
=>
gtx_rst_n
,
in_10b_i
=>
(
rx_data_raw
(
19
downto
10
)),
ctrl_o
=>
rx_k_int
(
1
),
code_err_o
=>
rx_code_err
(
1
),
rdisp_err_o
=>
open
,
out_8b_o
=>
rx_data_int
(
15
downto
8
));
U_Dec2
:
gc_dec_8b10b
port
map
(
clk_i
=>
rx_rec_clk
,
rst_n_i
=>
gtx_rst_n
,
in_10b_i
=>
(
rx_data_raw
(
9
downto
0
)),
ctrl_o
=>
rx_k_int
(
0
),
code_err_o
=>
rx_code_err
(
0
),
rdisp_err_o
=>
open
,
out_8b_o
=>
rx_data_int
(
7
downto
0
));
rx_disp_err
<=
(
others
=>
'0'
);
debug_o
(
1
)
<=
link_up
;
debug_o
(
2
)
<=
link_aligned
;
p_gen_rx_outputs
:
process
(
rx_rec_clk
,
gtx_rst
)
begin
if
(
gtx_rst
=
'1'
)
then
rx_data_o_int
<=
(
others
=>
'0'
);
rx_k_o_int
<=
(
others
=>
'0'
);
rx_enc_err_o_int
<=
'0'
;
elsif
rising_edge
(
rx_rec_clk
)
then
if
(
rx_enable_rxclk
=
'1'
)
then
rx_data_o_int
<=
rx_data_int
(
7
downto
0
)
&
rx_data_int
(
15
downto
8
);
rx_k_o_int
<=
rx_k_int
(
0
)
&
rx_k_int
(
1
);
rx_enc_err_o_int
<=
rx_disp_err
(
0
)
or
rx_disp_err
(
1
)
or
rx_code_err
(
0
)
or
rx_code_err
(
1
);
else
rx_data_o_int
<=
(
others
=>
'1'
);
rx_k_o_int
<=
(
others
=>
'1'
);
rx_enc_err_o_int
<=
'1'
;
end
if
;
end
if
;
end
process
;
p_gen_tx_disparity
:
process
(
clk_ref_i
)
begin
if
rising_edge
(
clk_ref_i
)
then
if
tx_enable_refclk
=
'0'
then
cur_disp
<=
RD_MINUS
;
else
cur_disp
<=
f_next_8b10b_disparity16
(
cur_disp
,
tx_k_i
,
tx_data_i
);
end
if
;
end
if
;
end
process
;
tx_disparity_o
<=
to_std_logic
(
cur_disp
);
rx_data_o
<=
rx_data_o_int
;
rx_k_o
<=
rx_k_o_int
;
rx_enc_err_o
<=
'0'
;
-- rx_enc_err_o_int;
end
rtl
;
platform/xilinx/wr_gtp_phy/whiterabbitgtx_wrapper_gtx_old.vhd
0 → 100644
View file @
74e929a1
-------------------------------------------------------------------------------
-- ____ ____
-- / /\/ /
-- /___/ \ / Vendor: Xilinx
-- \ \ \/ Version : 1.7
-- \ \ Application : Virtex-6 FPGA GTX Transceiver Wizard
-- / / Filename : whiterabbitgtx_wrapper_gtx.vhd
-- /___/ /\ Timestamp :
-- \ \ / \
-- \___\/\___\
--
--
-- Module WHITERABBITGTX_WRAPPER_GTX (a GTX Wrapper)
-- Generated by Xilinx Virtex-6 FPGA GTX Transceiver Wizard
--
--
-- (c) Copyright 2009-2010 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
library
ieee
;
use
ieee
.
std_logic_1164
.
all
;
use
ieee
.
numeric_std
.
all
;
library
UNISIM
;
use
UNISIM
.
VCOMPONENTS
.
all
;
--***************************** Entity Declaration ****************************
entity
WHITERABBITGTX_WRAPPER_GTX_OLD
is
generic
(
-- Simulation attributes
GTX_SIM_GTXRESET_SPEEDUP
:
integer
:
=
0
;
-- Set to 1 to speed up sim reset
-- Share RX PLL parameter
GTX_TX_CLK_SOURCE
:
string
:
=
"TXPLL"
;
-- Save power parameter
GTX_POWER_SAVE
:
bit_vector
:
=
"0000000000"
);
port
(
------------------------ Loopback and Powerdown Ports ----------------------
LOOPBACK_IN
:
in
std_logic_vector
(
2
downto
0
);
----------------------- Receive Ports - 8b10b Decoder ----------------------
RXCHARISK_OUT
:
out
std_logic_vector
(
1
downto
0
);
RXDISPERR_OUT
:
out
std_logic_vector
(
1
downto
0
);
RXNOTINTABLE_OUT
:
out
std_logic_vector
(
1
downto
0
);
--------------- Receive Ports - Comma Detection and Alignment --------------
RXBYTEISALIGNED_OUT
:
out
std_logic
;
RXCOMMADET_OUT
:
out
std_logic
;
RXSLIDE_IN
:
in
std_logic
;
------------------- Receive Ports - RX Data Path interface -----------------
RXDATA_OUT
:
out
std_logic_vector
(
15
downto
0
);
RXRECCLK_OUT
:
out
std_logic
;
RXUSRCLK2_IN
:
in
std_logic
;
------- Receive Ports - RX Driver,OOB signalling,Coupling and Eq.,CDR ------
RXCDRRESET_IN
:
in
std_logic
;
RXN_IN
:
in
std_logic
;
RXP_IN
:
in
std_logic
;
------------------------ Receive Ports - RX PLL Ports ----------------------
GTXRXRESET_IN
:
in
std_logic
;
MGTREFCLKRX_IN
:
in
std_logic_vector
(
1
downto
0
);
PLLRXRESET_IN
:
in
std_logic
;
RXPLLLKDET_OUT
:
out
std_logic
;
RXRESETDONE_OUT
:
out
std_logic
;
---------------- Transmit Ports - 8b10b Encoder Control Ports --------------
TXCHARISK_IN
:
in
std_logic_vector
(
1
downto
0
);
------------------------- Transmit Ports - GTX Ports -----------------------
GTXTEST_IN
:
in
std_logic_vector
(
12
downto
0
);
------------------ Transmit Ports - TX Data Path interface -----------------
TXDATA_IN
:
in
std_logic_vector
(
15
downto
0
);
TXOUTCLK_OUT
:
out
std_logic
;
TXUSRCLK2_IN
:
in
std_logic
;
TXRUNDISP_OUT
:
out
std_logic_vector
(
1
downto
0
);
---------------- Transmit Ports - TX Driver and OOB signaling --------------
TXN_OUT
:
out
std_logic
;
TXP_OUT
:
out
std_logic
;
-------- Transmit Ports - TX Elastic Buffer and Phase Alignment Ports ------
TXDLYALIGNDISABLE_IN
:
in
std_logic
;
TXDLYALIGNMONENB_IN
:
in
std_logic
;
TXDLYALIGNMONITOR_OUT
:
out
std_logic_vector
(
7
downto
0
);
TXDLYALIGNRESET_IN
:
in
std_logic
;
TXENPMAPHASEALIGN_IN
:
in
std_logic
;
TXPMASETPHASE_IN
:
in
std_logic
;
----------------------- Transmit Ports - TX PLL Ports ----------------------
GTXTXRESET_IN
:
in
std_logic
;
MGTREFCLKTX_IN
:
in
std_logic_vector
(
1
downto
0
);
PLLTXRESET_IN
:
in
std_logic
;
TXPLLLKDET_OUT
:
out
std_logic
;
TXRESETDONE_OUT
:
out
std_logic
);
end
WHITERABBITGTX_WRAPPER_GTX_OLD
;
architecture
RTL
of
WHITERABBITGTX_WRAPPER_GTX_OLD
is
--**************************** Signal Declarations ****************************
-- ground and tied_to_vcc_i signals
signal
tied_to_ground_i
:
std_logic
;
signal
tied_to_ground_vec_i
:
std_logic_vector
(
63
downto
0
);
signal
tied_to_vcc_i
:
std_logic
;
-- RX Datapath signals
signal
rxdata_i
:
std_logic_vector
(
31
downto
0
);
signal
rxchariscomma_float_i
:
std_logic_vector
(
1
downto
0
);
signal
rxcharisk_float_i
:
std_logic_vector
(
1
downto
0
);
signal
rxdisperr_float_i
:
std_logic_vector
(
1
downto
0
);
signal
rxnotintable_float_i
:
std_logic_vector
(
1
downto
0
);
signal
rxrundisp_float_i
:
std_logic_vector
(
1
downto
0
);
-- TX Datapath signals
signal
txdata_i
:
std_logic_vector
(
31
downto
0
);
signal
txkerr_float_i
:
std_logic_vector
(
1
downto
0
);
signal
txrundisp_int
:
std_logic_vector
(
3
downto
0
);
--******************************** Main Body of Code***************************
begin
--------------------------- Static signal Assignments ---------------------
tied_to_ground_i
<=
'0'
;
tied_to_ground_vec_i
(
63
downto
0
)
<=
(
others
=>
'0'
);
tied_to_vcc_i
<=
'1'
;
------------------- GTX Datapath byte mapping -----------------
-- The GTX provides little endian data (first byte received on RXDATA(7 downto 0))
RXDATA_OUT
<=
rxdata_i
(
15
downto
0
);
txdata_i
<=
(
tied_to_ground_vec_i
(
15
downto
0
)
&
TXDATA_IN
);
----------------------------- GTX Instance --------------------------
gtxe1_i
:
GTXE1
generic
map
(
--_______________________ Simulation-Only Attributes ___________________
SIM_RECEIVER_DETECT_PASS
=>
(
true
),
SIM_GTXRESET_SPEEDUP
=>
(
GTX_SIM_GTXRESET_SPEEDUP
),
SIM_TX_ELEC_IDLE_LEVEL
=>
(
"X"
),
SIM_VERSION
=>
(
"2.0"
),
SIM_TXREFCLK_SOURCE
=>
(
"000"
),
SIM_RXREFCLK_SOURCE
=>
(
"000"
),
----------------------------TX PLL----------------------------
TX_CLK_SOURCE
=>
(
GTX_TX_CLK_SOURCE
),
TX_OVERSAMPLE_MODE
=>
(
false
),
TXPLL_COM_CFG
=>
(
x"21680a"
),
TXPLL_CP_CFG
=>
(
x"0D"
),
TXPLL_DIVSEL_FB
=>
(
4
),
TXPLL_DIVSEL_OUT
=>
(
2
),
TXPLL_DIVSEL_REF
=>
(
1
),
TXPLL_DIVSEL45_FB
=>
(
5
),
TXPLL_LKDET_CFG
=>
(
"111"
),
TX_CLK25_DIVIDER
=>
(
3
),
TXPLL_SATA
=>
(
"00"
),
TX_TDCC_CFG
=>
(
"00"
),
PMA_CAS_CLK_EN
=>
(
false
),
POWER_SAVE
=>
(
GTX_POWER_SAVE
),
-------------------------TX Interface-------------------------
GEN_TXUSRCLK
=>
(
true
),
TX_DATA_WIDTH
=>
(
20
),
TX_USRCLK_CFG
=>
(
x"00"
),
TXOUTCLK_CTRL
=>
(
"TXPLLREFCLK_DIV2"
),
TXOUTCLK_DLY
=>
(
"0000000000"
),
--------------TX Buffering and Phase Alignment----------------
TX_PMADATA_OPT
=>
(
'1'
),
PMA_TX_CFG
=>
(
x"80082"
),
TX_BUFFER_USE
=>
(
false
),
TX_BYTECLK_CFG
=>
(
x"00"
),
TX_EN_RATE_RESET_BUF
=>
(
true
),
TX_XCLK_SEL
=>
(
"TXUSR"
),
TX_DLYALIGN_CTRINC
=>
(
"0100"
),
TX_DLYALIGN_LPFINC
=>
(
"0110"
),
TX_DLYALIGN_MONSEL
=>
(
"000"
),
TX_DLYALIGN_OVRDSETTING
=>
(
"10000000"
),
-------------------------TX Gearbox---------------------------
GEARBOX_ENDEC
=>
(
"000"
),
TXGEARBOX_USE
=>
(
false
),
----------------TX Driver and OOB Signalling------------------
TX_DRIVE_MODE
=>
(
"DIRECT"
),
TX_IDLE_ASSERT_DELAY
=>
(
"100"
),
TX_IDLE_DEASSERT_DELAY
=>
(
"010"
),
TXDRIVE_LOOPBACK_HIZ
=>
(
false
),
TXDRIVE_LOOPBACK_PD
=>
(
false
),
--------------TX Pipe Control for PCI Express/SATA------------
COM_BURST_VAL
=>
(
"1111"
),
------------------TX Attributes for PCI Express---------------
TX_DEEMPH_0
=>
(
"11010"
),
TX_DEEMPH_1
=>
(
"10000"
),
TX_MARGIN_FULL_0
=>
(
"1001110"
),
TX_MARGIN_FULL_1
=>
(
"1001001"
),
TX_MARGIN_FULL_2
=>
(
"1000101"
),
TX_MARGIN_FULL_3
=>
(
"1000010"
),
TX_MARGIN_FULL_4
=>
(
"1000000"
),
TX_MARGIN_LOW_0
=>
(
"1000110"
),
TX_MARGIN_LOW_1
=>
(
"1000100"
),
TX_MARGIN_LOW_2
=>
(
"1000010"
),
TX_MARGIN_LOW_3
=>
(
"1000000"
),
TX_MARGIN_LOW_4
=>
(
"1000000"
),
----------------------------RX PLL----------------------------
RX_OVERSAMPLE_MODE
=>
(
false
),
RXPLL_COM_CFG
=>
(
x"21680a"
),
RXPLL_CP_CFG
=>
(
x"0D"
),
RXPLL_DIVSEL_FB
=>
(
4
),
RXPLL_DIVSEL_OUT
=>
(
2
),
RXPLL_DIVSEL_REF
=>
(
1
),
RXPLL_DIVSEL45_FB
=>
(
5
),
RXPLL_LKDET_CFG
=>
(
"111"
),
RX_CLK25_DIVIDER
=>
(
3
),
-------------------------RX Interface-------------------------
GEN_RXUSRCLK
=>
(
true
),
RX_DATA_WIDTH
=>
(
20
),
RXRECCLK_CTRL
=>
(
"RXRECCLKPMA_DIV2"
),
RXRECCLK_DLY
=>
(
"0000000000"
),
RXUSRCLK_DLY
=>
(
x"0000"
),
----------RX Driver,OOB signalling,Coupling and Eq.,CDR-------
AC_CAP_DIS
=>
(
true
),
CDR_PH_ADJ_TIME
=>
(
"10100"
),
OOBDETECT_THRESHOLD
=>
(
"011"
),
PMA_CDR_SCAN
=>
(
x"640404C"
),
PMA_RX_CFG
=>
(
x"05ce008"
),
RCV_TERM_GND
=>
(
false
),
RCV_TERM_VTTRX
=>
(
true
),
RX_EN_IDLE_HOLD_CDR
=>
(
false
),
RX_EN_IDLE_RESET_FR
=>
(
false
),
RX_EN_IDLE_RESET_PH
=>
(
false
),
TX_DETECT_RX_CFG
=>
(
x"1832"
),
TERMINATION_CTRL
=>
(
"00000"
),
TERMINATION_OVRD
=>
(
false
),
CM_TRIM
=>
(
"01"
),
PMA_RXSYNC_CFG
=>
(
x"00"
),
PMA_CFG
=>
(
x"0040000040000000003"
),
BGTEST_CFG
=>
(
"00"
),
BIAS_CFG
=>
(
x"00000"
),
--------------RX Decision Feedback Equalizer(DFE)-------------
DFE_CAL_TIME
=>
(
"01100"
),
DFE_CFG
=>
(
"00011011"
),
RX_EN_IDLE_HOLD_DFE
=>
(
true
),
RX_EYE_OFFSET
=>
(
x"4C"
),
RX_EYE_SCANMODE
=>
(
"00"
),
-------------------------PRBS Detection-----------------------
RXPRBSERR_LOOPBACK
=>
(
'0'
),
------------------Comma Detection and Alignment---------------
ALIGN_COMMA_WORD
=>
(
2
),
COMMA_10B_ENABLE
=>
(
"0001111111"
),
COMMA_DOUBLE
=>
(
false
),
DEC_MCOMMA_DETECT
=>
(
false
),
DEC_PCOMMA_DETECT
=>
(
false
),
DEC_VALID_COMMA_ONLY
=>
(
true
),
MCOMMA_10B_VALUE
=>
(
"1010000011"
),
MCOMMA_DETECT
=>
(
true
),
PCOMMA_10B_VALUE
=>
(
"0101111100"
),
PCOMMA_DETECT
=>
(
true
),
RX_DECODE_SEQ_MATCH
=>
(
true
),
RX_SLIDE_AUTO_WAIT
=>
(
5
),
RX_SLIDE_MODE
=>
(
"PCS"
),
-- SHOW_REALIGN_COMMA => (TRUE),
SHOW_REALIGN_COMMA
=>
(
false
),
-----------------RX Loss-of-sync State Machine----------------
RX_LOS_INVALID_INCR
=>
(
8
),
RX_LOS_THRESHOLD
=>
(
128
),
RX_LOSS_OF_SYNC_FSM
=>
(
false
),
-------------------------RX Gearbox---------------------------
RXGEARBOX_USE
=>
(
false
),
-------------RX Elastic Buffer and Phase alignment------------
RX_BUFFER_USE
=>
(
true
),
RX_EN_IDLE_RESET_BUF
=>
(
false
),
RX_EN_MODE_RESET_BUF
=>
(
true
),
RX_EN_RATE_RESET_BUF
=>
(
true
),
RX_EN_REALIGN_RESET_BUF
=>
(
false
),
RX_EN_REALIGN_RESET_BUF2
=>
(
false
),
RX_FIFO_ADDR_MODE
=>
(
"FULL"
),
RX_IDLE_HI_CNT
=>
(
"1000"
),
RX_IDLE_LO_CNT
=>
(
"0000"
),
RX_XCLK_SEL
=>
(
"RXREC"
),
RX_DLYALIGN_CTRINC
=>
(
"1110"
),
RX_DLYALIGN_EDGESET
=>
(
"00010"
),
RX_DLYALIGN_LPFINC
=>
(
"1110"
),
RX_DLYALIGN_MONSEL
=>
(
"000"
),
RX_DLYALIGN_OVRDSETTING
=>
(
"10000000"
),
------------------------Clock Correction----------------------
CLK_COR_ADJ_LEN
=>
(
1
),
CLK_COR_DET_LEN
=>
(
1
),
CLK_COR_INSERT_IDLE_FLAG
=>
(
false
),
CLK_COR_KEEP_IDLE
=>
(
false
),
CLK_COR_MAX_LAT
=>
(
16
),
CLK_COR_MIN_LAT
=>
(
14
),
CLK_COR_PRECEDENCE
=>
(
true
),
CLK_COR_REPEAT_WAIT
=>
(
0
),
CLK_COR_SEQ_1_1
=>
(
"0100000000"
),
CLK_COR_SEQ_1_2
=>
(
"0100000000"
),
CLK_COR_SEQ_1_3
=>
(
"0100000000"
),
CLK_COR_SEQ_1_4
=>
(
"0100000000"
),
CLK_COR_SEQ_1_ENABLE
=>
(
"1111"
),
CLK_COR_SEQ_2_1
=>
(
"0100000000"
),
CLK_COR_SEQ_2_2
=>
(
"0100000000"
),
CLK_COR_SEQ_2_3
=>
(
"0100000000"
),
CLK_COR_SEQ_2_4
=>
(
"0100000000"
),
CLK_COR_SEQ_2_ENABLE
=>
(
"1111"
),
CLK_COR_SEQ_2_USE
=>
(
false
),
CLK_CORRECT_USE
=>
(
false
),
------------------------Channel Bonding----------------------
CHAN_BOND_1_MAX_SKEW
=>
(
1
),
CHAN_BOND_2_MAX_SKEW
=>
(
1
),
CHAN_BOND_KEEP_ALIGN
=>
(
false
),
CHAN_BOND_SEQ_1_1
=>
(
"0000000000"
),
CHAN_BOND_SEQ_1_2
=>
(
"0000000000"
),
CHAN_BOND_SEQ_1_3
=>
(
"0000000000"
),
CHAN_BOND_SEQ_1_4
=>
(
"0000000000"
),
CHAN_BOND_SEQ_1_ENABLE
=>
(
"1111"
),
CHAN_BOND_SEQ_2_1
=>
(
"0000000000"
),
CHAN_BOND_SEQ_2_2
=>
(
"0000000000"
),
CHAN_BOND_SEQ_2_3
=>
(
"0000000000"
),
CHAN_BOND_SEQ_2_4
=>
(
"0000000000"
),
CHAN_BOND_SEQ_2_CFG
=>
(
"00000"
),
CHAN_BOND_SEQ_2_ENABLE
=>
(
"1111"
),
CHAN_BOND_SEQ_2_USE
=>
(
false
),
CHAN_BOND_SEQ_LEN
=>
(
1
),
PCI_EXPRESS_MODE
=>
(
false
),
-------------RX Attributes for PCI Express/SATA/SAS----------
SAS_MAX_COMSAS
=>
(
52
),
SAS_MIN_COMSAS
=>
(
40
),
SATA_BURST_VAL
=>
(
"100"
),
SATA_IDLE_VAL
=>
(
"100"
),
SATA_MAX_BURST
=>
(
9
),
SATA_MAX_INIT
=>
(
27
),
SATA_MAX_WAKE
=>
(
9
),
SATA_MIN_BURST
=>
(
5
),
SATA_MIN_INIT
=>
(
15
),
SATA_MIN_WAKE
=>
(
5
),
TRANS_TIME_FROM_P2
=>
(
x"03c"
),
TRANS_TIME_NON_P2
=>
(
x"19"
),
TRANS_TIME_RATE
=>
(
x"ff"
),
TRANS_TIME_TO_P2
=>
(
x"064"
)
)
port
map
(
------------------------ Loopback and Powerdown Ports ----------------------
LOOPBACK
=>
LOOPBACK_IN
,
RXPOWERDOWN
=>
"00"
,
TXPOWERDOWN
=>
"00"
,
-------------- Receive Ports - 64b66b and 64b67b Gearbox Ports -------------
RXDATAVALID
=>
open
,
RXGEARBOXSLIP
=>
tied_to_ground_i
,
RXHEADER
=>
open
,
RXHEADERVALID
=>
open
,
RXSTARTOFSEQ
=>
open
,
----------------------- Receive Ports - 8b10b Decoder ----------------------
RXCHARISCOMMA
=>
open
,
RXCHARISK
(
3
downto
2
)
=>
rxcharisk_float_i
,
RXCHARISK
(
1
downto
0
)
=>
RXCHARISK_OUT
,
RXDEC8B10BUSE
=>
tied_to_vcc_i
,
RXDISPERR
(
3
downto
2
)
=>
rxdisperr_float_i
,
RXDISPERR
(
1
downto
0
)
=>
RXDISPERR_OUT
,
RXNOTINTABLE
(
3
downto
2
)
=>
rxnotintable_float_i
,
RXNOTINTABLE
(
1
downto
0
)
=>
RXNOTINTABLE_OUT
,
RXRUNDISP
=>
open
,
USRCODEERR
=>
tied_to_ground_i
,
------------------- Receive Ports - Channel Bonding Ports ------------------
RXCHANBONDSEQ
=>
open
,
RXCHBONDI
=>
tied_to_ground_vec_i
(
3
downto
0
),
RXCHBONDLEVEL
=>
tied_to_ground_vec_i
(
2
downto
0
),
RXCHBONDMASTER
=>
tied_to_ground_i
,
RXCHBONDO
=>
open
,
RXCHBONDSLAVE
=>
tied_to_ground_i
,
RXENCHANSYNC
=>
tied_to_ground_i
,
------------------- Receive Ports - Clock Correction Ports -----------------
RXCLKCORCNT
=>
open
,
--------------- Receive Ports - Comma Detection and Alignment --------------
RXBYTEISALIGNED
=>
RXBYTEISALIGNED_OUT
,
RXBYTEREALIGN
=>
open
,
RXCOMMADET
=>
RXCOMMADET_OUT
,
RXCOMMADETUSE
=>
tied_to_vcc_i
,
RXENMCOMMAALIGN
=>
tied_to_ground_i
,
RXENPCOMMAALIGN
=>
tied_to_ground_i
,
RXSLIDE
=>
RXSLIDE_IN
,
----------------------- Receive Ports - PRBS Detection ---------------------
PRBSCNTRESET
=>
tied_to_ground_i
,
RXENPRBSTST
=>
tied_to_ground_vec_i
(
2
downto
0
),
RXPRBSERR
=>
open
,
------------------- Receive Ports - RX Data Path interface -----------------
RXDATA
=>
rxdata_i
,
RXRECCLK
=>
RXRECCLK_OUT
,
RXRECCLKPCS
=>
open
,
RXRESET
=>
tied_to_ground_i
,
RXUSRCLK
=>
tied_to_ground_i
,
RXUSRCLK2
=>
RXUSRCLK2_IN
,
------------ Receive Ports - RX Decision Feedback Equalizer(DFE) -----------
DFECLKDLYADJ
=>
tied_to_ground_vec_i
(
5
downto
0
),
DFECLKDLYADJMON
=>
open
,
DFEDLYOVRD
=>
tied_to_vcc_i
,
DFEEYEDACMON
=>
open
,
DFESENSCAL
=>
open
,
DFETAP1
=>
tied_to_ground_vec_i
(
4
downto
0
),
DFETAP1MONITOR
=>
open
,
DFETAP2
=>
tied_to_ground_vec_i
(
4
downto
0
),
DFETAP2MONITOR
=>
open
,
DFETAP3
=>
tied_to_ground_vec_i
(
3
downto
0
),
DFETAP3MONITOR
=>
open
,
DFETAP4
=>
tied_to_ground_vec_i
(
3
downto
0
),
DFETAP4MONITOR
=>
open
,
DFETAPOVRD
=>
tied_to_vcc_i
,
------- Receive Ports - RX Driver,OOB signalling,Coupling and Eq.,CDR ------
GATERXELECIDLE
=>
tied_to_vcc_i
,
IGNORESIGDET
=>
tied_to_vcc_i
,
RXCDRRESET
=>
RXCDRRESET_IN
,
RXELECIDLE
=>
open
,
RXEQMIX
=>
"0000000000"
,
RXN
=>
RXN_IN
,
RXP
=>
RXP_IN
,
-------- Receive Ports - RX Elastic Buffer and Phase Alignment Ports -------
RXBUFRESET
=>
tied_to_ground_i
,
RXBUFSTATUS
=>
open
,
RXCHANISALIGNED
=>
open
,
RXCHANREALIGN
=>
open
,
RXDLYALIGNDISABLE
=>
tied_to_ground_i
,
RXDLYALIGNMONENB
=>
tied_to_ground_i
,
RXDLYALIGNMONITOR
=>
open
,
RXDLYALIGNOVERRIDE
=>
tied_to_vcc_i
,
RXDLYALIGNRESET
=>
tied_to_ground_i
,
RXDLYALIGNSWPPRECURB
=>
tied_to_vcc_i
,
RXDLYALIGNUPDSW
=>
tied_to_ground_i
,
RXENPMAPHASEALIGN
=>
tied_to_ground_i
,
RXPMASETPHASE
=>
tied_to_ground_i
,
RXSTATUS
=>
open
,
--------------- Receive Ports - RX Loss-of-sync State Machine --------------
RXLOSSOFSYNC
=>
open
,
---------------------- Receive Ports - RX Oversampling ---------------------
RXENSAMPLEALIGN
=>
tied_to_ground_i
,
RXOVERSAMPLEERR
=>
open
,
------------------------ Receive Ports - RX PLL Ports ----------------------
GREFCLKRX
=>
tied_to_ground_i
,
GTXRXRESET
=>
GTXRXRESET_IN
,
MGTREFCLKRX
=>
MGTREFCLKRX_IN
,
NORTHREFCLKRX
=>
tied_to_ground_vec_i
(
1
downto
0
),
PERFCLKRX
=>
tied_to_ground_i
,
PLLRXRESET
=>
PLLRXRESET_IN
,
RXPLLLKDET
=>
RXPLLLKDET_OUT
,
RXPLLLKDETEN
=>
tied_to_vcc_i
,
RXPLLPOWERDOWN
=>
tied_to_ground_i
,
RXPLLREFSELDY
=>
tied_to_ground_vec_i
(
2
downto
0
),
RXRATE
=>
tied_to_ground_vec_i
(
1
downto
0
),
RXRATEDONE
=>
open
,
RXRESETDONE
=>
RXRESETDONE_OUT
,
SOUTHREFCLKRX
=>
tied_to_ground_vec_i
(
1
downto
0
),
-------------- Receive Ports - RX Pipe Control for PCI Express -------------
PHYSTATUS
=>
open
,
RXVALID
=>
open
,
----------------- Receive Ports - RX Polarity Control Ports ----------------
RXPOLARITY
=>
tied_to_ground_i
,
--------------------- Receive Ports - RX Ports for SATA --------------------
COMINITDET
=>
open
,
COMSASDET
=>
open
,
COMWAKEDET
=>
open
,
------------- Shared Ports - Dynamic Reconfiguration Port (DRP) ------------
DADDR
=>
tied_to_ground_vec_i
(
7
downto
0
),
DCLK
=>
tied_to_ground_i
,
DEN
=>
tied_to_ground_i
,
DI
=>
tied_to_ground_vec_i
(
15
downto
0
),
DRDY
=>
open
,
DRPDO
=>
open
,
DWE
=>
tied_to_ground_i
,
-------------- Transmit Ports - 64b66b and 64b67b Gearbox Ports ------------
TXGEARBOXREADY
=>
open
,
TXHEADER
=>
tied_to_ground_vec_i
(
2
downto
0
),
TXSEQUENCE
=>
tied_to_ground_vec_i
(
6
downto
0
),
TXSTARTSEQ
=>
tied_to_ground_i
,
---------------- Transmit Ports - 8b10b Encoder Control Ports --------------
TXBYPASS8B10B
=>
tied_to_ground_vec_i
(
3
downto
0
),
TXCHARDISPMODE
=>
tied_to_ground_vec_i
(
3
downto
0
),
TXCHARDISPVAL
=>
tied_to_ground_vec_i
(
3
downto
0
),
TXCHARISK
(
3
downto
2
)
=>
tied_to_ground_vec_i
(
1
downto
0
),
TXCHARISK
(
1
downto
0
)
=>
TXCHARISK_IN
,
TXENC8B10BUSE
=>
tied_to_vcc_i
,
TXKERR
=>
open
,
TXRUNDISP
=>
txrundisp_int
,
------------------------- Transmit Ports - GTX Ports -----------------------
GTXTEST
=>
GTXTEST_IN
,
MGTREFCLKFAB
=>
open
,
TSTCLK0
=>
tied_to_ground_i
,
TSTCLK1
=>
tied_to_ground_i
,
TSTIN
=>
"11111111111111111111"
,
TSTOUT
=>
open
,
------------------ Transmit Ports - TX Data Path interface -----------------
TXDATA
=>
txdata_i
,
TXOUTCLK
=>
TXOUTCLK_OUT
,
TXOUTCLKPCS
=>
open
,
TXRESET
=>
tied_to_ground_i
,
TXUSRCLK
=>
tied_to_ground_i
,
TXUSRCLK2
=>
TXUSRCLK2_IN
,
---------------- Transmit Ports - TX Driver and OOB signaling --------------
TXBUFDIFFCTRL
=>
"100"
,
TXDIFFCTRL
=>
"1101"
,
TXINHIBIT
=>
tied_to_ground_i
,
TXN
=>
TXN_OUT
,
TXP
=>
TXP_OUT
,
TXPOSTEMPHASIS
=>
"00000"
,
--------------- Transmit Ports - TX Driver and OOB signalling --------------
TXPREEMPHASIS
=>
"0000"
,
----------- Transmit Ports - TX Elastic Buffer and Phase Alignment ---------
TXBUFSTATUS
=>
open
,
-------- Transmit Ports - TX Elastic Buffer and Phase Alignment Ports ------
TXDLYALIGNDISABLE
=>
TXDLYALIGNDISABLE_IN
,
TXDLYALIGNMONENB
=>
TXDLYALIGNMONENB_IN
,
TXDLYALIGNMONITOR
=>
TXDLYALIGNMONITOR_OUT
,
TXDLYALIGNOVERRIDE
=>
tied_to_ground_i
,
TXDLYALIGNRESET
=>
TXDLYALIGNRESET_IN
,
TXDLYALIGNUPDSW
=>
tied_to_ground_i
,
TXENPMAPHASEALIGN
=>
TXENPMAPHASEALIGN_IN
,
TXPMASETPHASE
=>
TXPMASETPHASE_IN
,
----------------------- Transmit Ports - TX PLL Ports ----------------------
GREFCLKTX
=>
tied_to_ground_i
,
GTXTXRESET
=>
GTXTXRESET_IN
,
MGTREFCLKTX
=>
MGTREFCLKTX_IN
,
NORTHREFCLKTX
=>
tied_to_ground_vec_i
(
1
downto
0
),
PERFCLKTX
=>
tied_to_ground_i
,
PLLTXRESET
=>
PLLTXRESET_IN
,
SOUTHREFCLKTX
=>
tied_to_ground_vec_i
(
1
downto
0
),
TXPLLLKDET
=>
TXPLLLKDET_OUT
,
TXPLLLKDETEN
=>
tied_to_vcc_i
,
TXPLLPOWERDOWN
=>
tied_to_ground_i
,
TXPLLREFSELDY
=>
tied_to_ground_vec_i
(
2
downto
0
),
TXRATE
=>
tied_to_ground_vec_i
(
1
downto
0
),
TXRATEDONE
=>
open
,
TXRESETDONE
=>
TXRESETDONE_OUT
,
--------------------- Transmit Ports - TX PRBS Generator -------------------
TXENPRBSTST
=>
tied_to_ground_vec_i
(
2
downto
0
),
TXPRBSFORCEERR
=>
tied_to_ground_i
,
-------------------- Transmit Ports - TX Polarity Control ------------------
TXPOLARITY
=>
tied_to_ground_i
,
----------------- Transmit Ports - TX Ports for PCI Express ----------------
TXDEEMPH
=>
tied_to_ground_i
,
TXDETECTRX
=>
tied_to_ground_i
,
TXELECIDLE
=>
tied_to_ground_i
,
TXMARGIN
=>
tied_to_ground_vec_i
(
2
downto
0
),
TXPDOWNASYNCH
=>
tied_to_ground_i
,
TXSWING
=>
tied_to_ground_i
,
--------------------- Transmit Ports - TX Ports for SATA -------------------
COMFINISH
=>
open
,
TXCOMINIT
=>
tied_to_ground_i
,
TXCOMSAS
=>
tied_to_ground_i
,
TXCOMWAKE
=>
tied_to_ground_i
);
TXRUNDISP_OUT
<=
txrundisp_int
(
1
downto
0
);
end
RTL
;
platform/xilinx/wr_gtp_phy/wr_gtx_phy_virtex6_old.vhd
0 → 100644
View file @
74e929a1
-------------------------------------------------------------------------------
-- Title : Deterministic Xilinx GTP wrapper - Spartan-6 top module
-- Project : White Rabbit Switch
-------------------------------------------------------------------------------
-- File : wr_gtp_phy_spartan6.vhd
-- Author : Tomasz Wlostowski
-- Company : CERN BE-CO-HT
-- Created : 2010-11-18
-- Last update: 2018-08-08
-- Platform : FPGA-generic
-- Standard : VHDL'93
-------------------------------------------------------------------------------
-- Description: Dual channel wrapper for Xilinx Spartan-6 GTP adapted for
-- deterministic delays at 1.25 Gbps.
-------------------------------------------------------------------------------
--
-- Copyright (c) 2010 CERN / Tomasz Wlostowski
--
-- This source file is free software; you can redistribute it
-- and/or modify it under the terms of the GNU Lesser General
-- Public License as published by the Free Software Foundation;
-- either version 2.1 of the License, or (at your option) any
-- later version.
--
-- This source is distributed in the hope that it will be
-- useful, but WITHOUT ANY WARRANTY; without even the implied
-- warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR
-- PURPOSE. See the GNU Lesser General Public License for more
-- details.
--
-- You should have received a copy of the GNU Lesser General
-- Public License along with this source; if not, download it
-- from http://www.gnu.org/licenses/lgpl-2.1.html
--
--
-------------------------------------------------------------------------------
-- Revisions :
-- Date Version Author Description
-- 2010-11-18 0.4 twlostow Initial release
-- 2011-02-07 0.5 twlostow Verified on Spartan6 GTP (single channel only)
-------------------------------------------------------------------------------
library
ieee
;
use
ieee
.
std_logic_1164
.
all
;
use
ieee
.
numeric_std
.
all
;
library
unisim
;
use
unisim
.
vcomponents
.
all
;
library
work
;
use
work
.
gencores_pkg
.
all
;
use
work
.
disparity_gen_pkg
.
all
;
entity
wr_gtx_phy_virtex6_old
is
generic
(
-- set to non-zero value to speed up the simulation by reducing some delays
g_simulation
:
integer
:
=
0
;
g_use_slave_tx_clock
:
integer
:
=
0
;
g_use_bufr
:
boolean
:
=
false
;
g_id
:
integer
:
=
0
);
port
(
-- Reference 62.5 MHz clock input for the TX/RX logic (not the GTX itself)
clk_ref_i
:
in
std_logic
;
-- Reference 62.5 MHz clock for the GTX transceiver
clk_gtx_i
:
in
std_logic
;
-- DMTD clock for phase measurements (done in the PHY module as we need to
-- multiplex between several GTX clock outputs)
clk_dmtd_i
:
in
std_logic
;
-- TX path, clk_ref_i - synchronous:
-- data input (8 bits, not 8b10b-encoded)
tx_data_i
:
in
std_logic_vector
(
15
downto
0
);
-- 1 when tx_data_i contains a control code, 0 when it's a data byte
tx_k_i
:
in
std_logic_vector
(
1
downto
0
);
-- disparity of the currently transmitted 8b10b code (1 = plus, 0 = minus).
-- Necessary for the PCS to generate proper frame termination sequences.
-- Generated for the 2nd byte (LSB) of tx_data_i.
tx_disparity_o
:
out
std_logic
;
-- Encoding error indication (1 = error, 0 = no error)
tx_enc_err_o
:
out
std_logic
;
-- RX path, synchronous to ch0_rx_rbclk_o.
-- RX recovered clock
rx_rbclk_o
:
out
std_logic
;
rx_rbclk_sampled_o
:
out
std_logic
;
-- 8b10b-decoded data output. The data output must be kept invalid before
-- the transceiver is locked on the incoming signal to prevent the EP from
-- detecting a false carrier.
rx_data_o
:
out
std_logic_vector
(
15
downto
0
);
-- 1 when the byte on rx_data_o is a control code
rx_k_o
:
out
std_logic_vector
(
1
downto
0
);
-- encoding error indication
rx_enc_err_o
:
out
std_logic
;
-- RX bitslide indication, indicating the delay of the RX path of the
-- transceiver (in UIs). Must be valid when ch0_rx_data_o is valid.
rx_bitslide_o
:
out
std_logic_vector
(
4
downto
0
);
-- reset input, active hi
rst_i
:
in
std_logic
;
loopen_i
:
in
std_logic
;
pad_txn_o
:
out
std_logic
;
pad_txp_o
:
out
std_logic
;
pad_rxn_i
:
in
std_logic
:
=
'0'
;
pad_rxp_i
:
in
std_logic
:
=
'0'
;
rdy_o
:
out
std_logic
;
debug_i
:
in
std_logic_vector
(
15
downto
0
)
:
=
x"0000"
;
debug_o
:
out
std_logic_vector
(
15
downto
0
);
TX_CLK_o
:
out
std_logic
);
end
wr_gtx_phy_virtex6_old
;
architecture
rtl
of
wr_gtx_phy_virtex6_old
is
component
WHITERABBITGTX_WRAPPER_GTX_OLD
generic
(
GTX_SIM_GTXRESET_SPEEDUP
:
integer
;
GTX_TX_CLK_SOURCE
:
string
;
GTX_POWER_SAVE
:
bit_vector
);
port
(
LOOPBACK_IN
:
in
std_logic_vector
(
2
downto
0
);
RXCHARISK_OUT
:
out
std_logic_vector
(
1
downto
0
);
RXDISPERR_OUT
:
out
std_logic_vector
(
1
downto
0
);
RXNOTINTABLE_OUT
:
out
std_logic_vector
(
1
downto
0
);
RXBYTEISALIGNED_OUT
:
out
std_logic
;
RXCOMMADET_OUT
:
out
std_logic
;
RXSLIDE_IN
:
in
std_logic
;
RXDATA_OUT
:
out
std_logic_vector
(
15
downto
0
);
RXRECCLK_OUT
:
out
std_logic
;
RXUSRCLK2_IN
:
in
std_logic
;
RXCDRRESET_IN
:
in
std_logic
;
RXN_IN
:
in
std_logic
;
RXP_IN
:
in
std_logic
;
GTXRXRESET_IN
:
in
std_logic
;
MGTREFCLKRX_IN
:
in
std_logic_vector
(
1
downto
0
);
PLLRXRESET_IN
:
in
std_logic
;
RXPLLLKDET_OUT
:
out
std_logic
;
RXRESETDONE_OUT
:
out
std_logic
;
TXCHARISK_IN
:
in
std_logic_vector
(
1
downto
0
);
GTXTEST_IN
:
in
std_logic_vector
(
12
downto
0
);
TXDATA_IN
:
in
std_logic_vector
(
15
downto
0
);
TXOUTCLK_OUT
:
out
std_logic
;
TXUSRCLK2_IN
:
in
std_logic
;
TXRUNDISP_OUT
:
out
std_logic_vector
(
1
downto
0
);
TXN_OUT
:
out
std_logic
;
TXP_OUT
:
out
std_logic
;
TXDLYALIGNDISABLE_IN
:
in
std_logic
;
TXDLYALIGNMONENB_IN
:
in
std_logic
;
TXDLYALIGNMONITOR_OUT
:
out
std_logic_vector
(
7
downto
0
);
TXDLYALIGNRESET_IN
:
in
std_logic
;
TXENPMAPHASEALIGN_IN
:
in
std_logic
;
TXPMASETPHASE_IN
:
in
std_logic
;
GTXTXRESET_IN
:
in
std_logic
;
MGTREFCLKTX_IN
:
in
std_logic_vector
(
1
downto
0
);
PLLTXRESET_IN
:
in
std_logic
;
TXPLLLKDET_OUT
:
out
std_logic
;
TXRESETDONE_OUT
:
out
std_logic
);
end
component
;
component
BUFG
port
(
O
:
out
std_ulogic
;
I
:
in
std_ulogic
);
end
component
;
component
BUFR
generic
(
BUFR_DIVIDE
:
string
:
=
"BYPASS"
;
SIM_DEVICE
:
string
:
=
"VIRTEX6"
);
port
(
O
:
out
std_ulogic
;
CE
:
in
std_ulogic
:
=
'1'
;
CLR
:
in
std_ulogic
:
=
'0'
;
I
:
in
std_ulogic
);
end
component
;
component
dmtd_sampler
is
generic
(
g_divide_input_by_2
:
boolean
;
g_reverse
:
boolean
);
port
(
clk_in_i
:
in
std_logic
;
clk_dmtd_i
:
in
std_logic
;
clk_sampled_o
:
out
std_logic
);
end
component
dmtd_sampler
;
component
gtp_bitslide
generic
(
g_simulation
:
integer
;
g_target
:
string
:
=
"virtex6"
);
port
(
gtp_rst_i
:
in
std_logic
;
gtp_rx_clk_i
:
in
std_logic
;
gtp_rx_comma_det_i
:
in
std_logic
;
gtp_rx_byte_is_aligned_i
:
in
std_logic
;
serdes_ready_i
:
in
std_logic
;
gtp_rx_slide_o
:
out
std_logic
;
gtp_rx_cdr_rst_o
:
out
std_logic
;
bitslide_o
:
out
std_logic_vector
(
4
downto
0
);
synced_o
:
out
std_logic
);
end
component
;
component
gtx_reset
port
(
clk_tx_i
:
in
std_logic
;
rst_i
:
in
std_logic
;
txpll_lockdet_i
:
in
std_logic
;
gtx_test_o
:
out
std_logic_vector
(
12
downto
0
));
end
component
;
signal
trig0
,
trig1
,
trig2
,
trig3
:
std_logic_vector
(
31
downto
0
);
signal
gtx_rst
:
std_logic
;
signal
gtx_loopback
:
std_logic_vector
(
2
downto
0
);
signal
gtx_reset_done
:
std_logic
;
signal
gtx_pll_lockdet
:
std_logic
;
signal
rst_synced
:
std_logic
;
signal
rst_d0
:
std_logic
;
signal
reset_counter
:
unsigned
(
9
downto
0
);
signal
gtx_test
:
std_logic_vector
(
12
downto
0
);
signal
rx_rec_clk_bufin
:
std_logic
;
signal
rx_rec_clk
:
std_logic
;
signal
rx_comma_det
:
std_logic
;
signal
rx_byte_is_aligned
:
std_logic
;
signal
tx_dly_align_disable
:
std_logic
;
signal
tx_dly_align_reset
:
std_logic
;
signal
tx_en_pma_phase_align
:
std_logic
;
signal
tx_pma_set_phase
:
std_logic
;
signal
align_enable
:
std_logic
;
signal
align_done
:
std_logic
;
signal
tx_rst_done
,
rx_rst_done
:
std_logic
;
signal
txpll_lockdet
,
rxpll_lockdet
:
std_logic
;
signal
pll_lockdet
:
std_logic
;
signal
serdes_ready
:
std_logic
;
signal
rx_slide
:
std_logic
;
signal
rx_cdr_rst
:
std_logic
;
signal
rx_synced
:
std_logic
;
signal
rst_done
:
std_logic
;
signal
everything_ready
:
std_logic
;
signal
mgtrefclk_in
:
std_logic_vector
(
1
downto
0
);
signal
rx_k_int
:
std_logic_vector
(
1
downto
0
);
signal
rx_data_int
:
std_logic_vector
(
15
downto
0
);
signal
rx_disp_err
,
rx_code_err
:
std_logic_vector
(
1
downto
0
);
signal
tx_is_k_swapped
:
std_logic_vector
(
1
downto
0
);
signal
tx_data_swapped
:
std_logic_vector
(
15
downto
0
);
signal
cur_disp
:
t_8b10b_disparity
;
signal
tx_out_clk
,
tx_out_clk_buf
:
std_logic
;
signal
rx_rec_clk_sampled
,
tx_out_clk_sampled
:
std_logic
;
signal
tx_rundisp_v6
:
std_logic_vector
(
1
downto
0
);
begin
-- rtl
tx_enc_err_o
<=
'0'
;
U_Sampler_RX
:
dmtd_sampler
generic
map
(
g_divide_input_by_2
=>
false
,
g_reverse
=>
true
)
port
map
(
clk_in_i
=>
rx_rec_clk
,
clk_dmtd_i
=>
clk_dmtd_i
,
clk_sampled_o
=>
rx_rec_clk_sampled
);
U_Sampler_TX
:
dmtd_sampler
generic
map
(
g_divide_input_by_2
=>
false
,
g_reverse
=>
true
)
port
map
(
clk_in_i
=>
tx_out_clk
,
clk_dmtd_i
=>
clk_dmtd_i
,
clk_sampled_o
=>
tx_out_clk_sampled
);
process
(
rx_rec_clk_sampled
,
tx_out_clk_sampled
,
debug_i
)
begin
case
debug_i
(
15
downto
14
)
is
when
"00"
=>
rx_rbclk_sampled_o
<=
rx_rec_clk_sampled
;
when
"01"
=>
rx_rbclk_sampled_o
<=
tx_out_clk_sampled
;
when
others
=>
rx_rbclk_sampled_o
<=
'0'
;
end
case
;
end
process
;
-- Near-end PMA loopback if loopen_i active
gtx_loopback
<=
"010"
when
loopen_i
=
'1'
else
"000"
;
p_gen_reset
:
process
(
clk_ref_i
)
begin
if
rising_edge
(
clk_ref_i
)
then
rst_d0
<=
rst_i
;
rst_synced
<=
rst_d0
;
if
(
rst_synced
=
'1'
)
then
reset_counter
<=
(
others
=>
'0'
);
else
if
(
reset_counter
(
reset_counter
'left
)
=
'0'
)
then
reset_counter
<=
reset_counter
+
1
;
end
if
;
end
if
;
end
if
;
end
process
;
gtx_rst
<=
rst_synced
or
std_logic
(
not
reset_counter
(
reset_counter
'left
));
U_Twice_Reset_Gen
:
gtx_reset
port
map
(
clk_tx_i
=>
clk_ref_i
,
rst_i
=>
gtx_rst
,
txpll_lockdet_i
=>
txpll_lockdet
,
gtx_test_o
=>
gtx_test
);
gen_rx_bufg
:
if
(
g_use_bufr
=
false
)
generate
U_BUF_RxRecClk
:
BUFG
port
map
(
I
=>
rx_rec_clk_bufin
,
O
=>
rx_rec_clk
);
end
generate
gen_rx_bufg
;
gen_rx_bufr
:
if
(
g_use_bufr
=
true
)
generate
U_BUF_RxRecClk
:
BUFR
port
map
(
I
=>
rx_rec_clk_bufin
,
O
=>
rx_rec_clk
);
end
generate
gen_rx_bufr
;
rx_rbclk_o
<=
rx_rec_clk
;
tx_is_k_swapped
<=
tx_k_i
(
0
)
&
tx_k_i
(
1
);
tx_data_swapped
<=
tx_data_i
(
7
downto
0
)
&
tx_data_i
(
15
downto
8
);
U_GTX_INST
:
WHITERABBITGTX_WRAPPER_GTX_OLD
generic
map
(
GTX_SIM_GTXRESET_SPEEDUP
=>
1
,
GTX_TX_CLK_SOURCE
=>
"TXPLL"
,
GTX_POWER_SAVE
=>
"0000110000"
)
port
map
(
LOOPBACK_IN
=>
gtx_loopback
,
RXCHARISK_OUT
=>
rx_k_int
,
RXDISPERR_OUT
=>
rx_disp_err
,
RXNOTINTABLE_OUT
=>
rx_code_err
,
RXBYTEISALIGNED_OUT
=>
rx_byte_is_aligned
,
RXCOMMADET_OUT
=>
rx_comma_det
,
RXSLIDE_IN
=>
rx_slide
,
RXDATA_OUT
=>
rx_data_int
,
RXRECCLK_OUT
=>
rx_rec_clk_bufin
,
RXUSRCLK2_IN
=>
rx_rec_clk
,
RXCDRRESET_IN
=>
rx_cdr_rst
,
RXN_IN
=>
pad_rxn_i
,
RXP_IN
=>
pad_rxp_i
,
GTXRXRESET_IN
=>
gtx_rst
,
MGTREFCLKRX_IN
=>
mgtrefclk_in
,
PLLRXRESET_IN
=>
'0'
,
RXPLLLKDET_OUT
=>
rxpll_lockdet
,
RXRESETDONE_OUT
=>
rx_rst_done
,
TXCHARISK_IN
=>
tx_is_k_swapped
,
GTXTEST_IN
=>
gtx_test
,
TXDATA_IN
=>
tx_data_swapped
,
TXOUTCLK_OUT
=>
open
,
TXUSRCLK2_IN
=>
clk_ref_i
,
TXRUNDISP_OUT
=>
tx_rundisp_v6
,
TXN_OUT
=>
pad_txn_o
,
TXP_OUT
=>
pad_txp_o
,
TXDLYALIGNDISABLE_IN
=>
tx_dly_align_disable
,
TXDLYALIGNMONENB_IN
=>
'1'
,
TXDLYALIGNMONITOR_OUT
=>
open
,
TXDLYALIGNRESET_IN
=>
tx_dly_align_reset
,
TXENPMAPHASEALIGN_IN
=>
tx_en_pma_phase_align
,
TXPMASETPHASE_IN
=>
tx_pma_set_phase
,
GTXTXRESET_IN
=>
gtx_rst
,
MGTREFCLKTX_IN
=>
mgtrefclk_in
,
PLLTXRESET_IN
=>
'0'
,
TXPLLLKDET_OUT
=>
txpll_lockdet
,
TXRESETDONE_OUT
=>
tx_rst_done
);
mgtrefclk_in
<=
'0'
&
clk_gtx_i
;
U_Phase_Align
:
entity
work
.
gtp_phase_align_virtex6
generic
map
(
g_simulation
=>
g_simulation
)
port
map
(
gtp_rst_i
=>
gtx_rst
,
gtp_tx_clk_i
=>
clk_ref_i
,
gtp_tx_en_pma_phase_align_o
=>
tx_en_pma_phase_align
,
gtp_tx_pma_set_phase_o
=>
tx_pma_set_phase
,
gtp_tx_dly_align_disable_o
=>
tx_dly_align_disable
,
gtp_tx_dly_align_reset_o
=>
tx_dly_align_reset
,
align_en_i
=>
align_enable
,
align_done_o
=>
align_done
);
U_Bitslide
:
gtp_bitslide
generic
map
(
g_simulation
=>
g_simulation
,
g_target
=>
"virtex6"
)
port
map
(
gtp_rst_i
=>
gtx_rst
,
gtp_rx_clk_i
=>
rx_rec_clk
,
gtp_rx_comma_det_i
=>
rx_comma_det
,
gtp_rx_byte_is_aligned_i
=>
rx_byte_is_aligned
,
serdes_ready_i
=>
everything_ready
,
gtp_rx_slide_o
=>
rx_slide
,
gtp_rx_cdr_rst_o
=>
rx_cdr_rst
,
bitslide_o
=>
rx_bitslide_o
,
synced_o
=>
rx_synced
);
rst_done
<=
rx_rst_done
and
tx_rst_done
;
pll_lockdet
<=
txpll_lockdet
and
rxpll_lockdet
;
serdes_ready
<=
rst_done
and
pll_lockdet
;
align_enable
<=
serdes_ready
;
everything_ready
<=
serdes_ready
and
align_done
;
rdy_o
<=
everything_ready
;
trig2
(
3
)
<=
rx_rst_done
;
trig2
(
4
)
<=
tx_rst_done
;
trig2
(
5
)
<=
txpll_lockdet
;
trig2
(
6
)
<=
rxpll_lockdet
;
trig2
(
7
)
<=
align_done
;
p_gen_rx_outputs
:
process
(
rx_rec_clk
,
gtx_rst
)
begin
if
(
gtx_rst
=
'1'
)
then
rx_data_o
<=
(
others
=>
'0'
);
rx_k_o
<=
(
others
=>
'0'
);
rx_enc_err_o
<=
'0'
;
elsif
rising_edge
(
rx_rec_clk
)
then
if
(
everything_ready
=
'1'
and
rx_synced
=
'1'
)
then
rx_data_o
<=
rx_data_int
(
7
downto
0
)
&
rx_data_int
(
15
downto
8
);
rx_k_o
<=
rx_k_int
(
0
)
&
rx_k_int
(
1
);
rx_enc_err_o
<=
rx_disp_err
(
0
)
or
rx_disp_err
(
1
)
or
rx_code_err
(
0
)
or
rx_code_err
(
1
);
else
rx_data_o
<=
(
others
=>
'1'
);
rx_k_o
<=
(
others
=>
'1'
);
rx_enc_err_o
<=
'1'
;
end
if
;
end
if
;
end
process
;
p_gen_tx_disparity
:
process
(
clk_ref_i
)
begin
if
rising_edge
(
clk_ref_i
)
then
if
gtx_rst
=
'1'
then
cur_disp
<=
RD_MINUS
;
else
cur_disp
<=
f_next_8b10b_disparity16
(
cur_disp
,
tx_k_i
,
tx_data_i
);
end
if
;
end
if
;
end
process
;
tx_disparity_o
<=
to_std_logic
(
cur_disp
);
end
rtl
;
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