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Commit 678491f4 authored by Tomasz Wlostowski's avatar Tomasz Wlostowski Committed by Grzegorz Daniluk
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platform: hacking the GTXE2 wrapper

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platform/xilinx/wr_gtp_phy/kintex7/gtwizard_0_common.vhd 0 → 100644
View file @ 678491f4
---------------------------------------------------------------------------------------------------
-- ____ ____
-- / /\/ /
-- /___/ \ / Vendor: Xilinx
-- \ \ \/ Version : 3.6
-- \ \ Application : 7 Series FPGAs Transceivers Wizard
-- / / Filename : gtwizard_0_common.vhd
-- /___/ /\
-- \ \ / \
-- \___\/\___\
--
--
-- Module gtwizard_0_common
-- Generated by Xilinx 7 Series FPGAs Transceivers Wizard
--
--
-- (c) Copyright 2010-2012 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
--***************************** Entity Declaration ****************************
entity gtwizard_0_common is
generic
(
-- Simulation attributes
WRAPPER_SIM_GTRESET_SPEEDUP : string := "TRUE"; -- Set to "true" to speed up sim reset
SIM_QPLLREFCLK_SEL : bit_vector := "001"
);
port
(
QPLLREFCLKSEL_IN : in std_logic_vector(2 downto 0);
GTREFCLK1_IN : in std_logic;
GTREFCLK0_IN : in std_logic;
QPLLLOCK_OUT : out std_logic;
QPLLLOCKDETCLK_IN : in std_logic;
QPLLOUTCLK_OUT : out std_logic;
QPLLOUTREFCLK_OUT : out std_logic;
QPLLREFCLKLOST_OUT : out std_logic;
QPLLRESET_IN : in std_logic
);
end gtwizard_0_common;
architecture RTL of gtwizard_0_common is
attribute CORE_GENERATION_INFO : string;
attribute CORE_GENERATION_INFO of RTL : architecture is "gtwizard_0_common,gtwizard_v3_6_8,{protocol_file=gigabit_ethernet_CC}";
--***********************************Parameter Declarations********************
constant DLY : time := 1 ns;
--*************************Logic to set Attribute QPLL_FB_DIV*****************************
impure function conv_qpll_fbdiv_top (qpllfbdiv_top : in integer) return bit_vector is
begin
if (qpllfbdiv_top = 16) then
return "0000100000";
elsif (qpllfbdiv_top = 20) then
return "0000110000" ;
elsif (qpllfbdiv_top = 32) then
return "0001100000" ;
elsif (qpllfbdiv_top = 40) then
return "0010000000" ;
elsif (qpllfbdiv_top = 64) then
return "0011100000" ;
elsif (qpllfbdiv_top = 66) then
return "0101000000" ;
elsif (qpllfbdiv_top = 80) then
return "0100100000" ;
elsif (qpllfbdiv_top = 100) then
return "0101110000" ;
else
return "0000000000" ;
end if;
end function;
impure function conv_qpll_fbdiv_ratio (qpllfbdiv_top : in integer) return bit is
begin
if (qpllfbdiv_top = 16) then
return '1';
elsif (qpllfbdiv_top = 20) then
return '1' ;
elsif (qpllfbdiv_top = 32) then
return '1' ;
elsif (qpllfbdiv_top = 40) then
return '1' ;
elsif (qpllfbdiv_top = 64) then
return '1' ;
elsif (qpllfbdiv_top = 66) then
return '0' ;
elsif (qpllfbdiv_top = 80) then
return '1' ;
elsif (qpllfbdiv_top = 100) then
return '1' ;
else
return '1' ;
end if;
end function;
constant QPLL_FBDIV_TOP : integer := 80;
constant QPLL_FBDIV_IN : bit_vector(9 downto 0) := conv_qpll_fbdiv_top(QPLL_FBDIV_TOP);
constant QPLL_FBDIV_RATIO : bit := conv_qpll_fbdiv_ratio(QPLL_FBDIV_TOP);
-- ground and tied_to_vcc_i signals
signal tied_to_ground_i : std_logic;
signal tied_to_ground_vec_i : std_logic_vector(63 downto 0);
signal tied_to_vcc_i : std_logic;
signal tied_to_vcc_vec_i : std_logic_vector(63 downto 0);
begin
tied_to_ground_i <= '0';
tied_to_ground_vec_i(63 downto 0) <= (others => '0');
tied_to_vcc_i <= '1';
tied_to_vcc_vec_i(63 downto 0) <= (others => '1');
--_________________________________________________________________________
--_________________________________________________________________________
--_________________________GTXE2_COMMON____________________________________
gtxe2_common_i : GTXE2_COMMON
generic map
(
-- Simulation attributes
SIM_RESET_SPEEDUP => WRAPPER_SIM_GTRESET_SPEEDUP,
SIM_QPLLREFCLK_SEL => (SIM_QPLLREFCLK_SEL),
SIM_VERSION => "4.0",
------------------COMMON BLOCK Attributes---------------
BIAS_CFG => (x"0000040000001000"),
COMMON_CFG => (x"00000000"),
QPLL_CFG => (x"0680181"),
QPLL_CLKOUT_CFG => ("0000"),
QPLL_COARSE_FREQ_OVRD => ("010000"),
QPLL_COARSE_FREQ_OVRD_EN => ('0'),
QPLL_CP => ("0000011111"),
QPLL_CP_MONITOR_EN => ('0'),
QPLL_DMONITOR_SEL => ('0'),
QPLL_FBDIV => (QPLL_FBDIV_IN),
QPLL_FBDIV_MONITOR_EN => ('0'),
QPLL_FBDIV_RATIO => (QPLL_FBDIV_RATIO),
QPLL_INIT_CFG => (x"000006"),
QPLL_LOCK_CFG => (x"21E8"),
QPLL_LPF => ("1111"),
QPLL_REFCLK_DIV => (1)
)
port map
(
------------- Common Block - Dynamic Reconfiguration Port (DRP) -----------
DRPADDR => tied_to_ground_vec_i(7 downto 0),
DRPCLK => tied_to_ground_i,
DRPDI => tied_to_ground_vec_i(15 downto 0),
DRPDO => open,
DRPEN => tied_to_ground_i,
DRPRDY => open,
DRPWE => tied_to_ground_i,
---------------------- Common Block - Ref Clock Ports ---------------------
GTGREFCLK => tied_to_ground_i,
GTNORTHREFCLK0 => tied_to_ground_i,
GTNORTHREFCLK1 => tied_to_ground_i,
GTREFCLK0 => GTREFCLK0_IN,
GTREFCLK1 => GTREFCLK1_IN,
GTSOUTHREFCLK0 => tied_to_ground_i,
GTSOUTHREFCLK1 => tied_to_ground_i,
------------------------- Common Block - QPLL Ports -----------------------
QPLLDMONITOR => open,
----------------------- Common Block - Clocking Ports ----------------------
QPLLOUTCLK => QPLLOUTCLK_OUT,
QPLLOUTREFCLK => QPLLOUTREFCLK_OUT,
REFCLKOUTMONITOR => open,
------------------------- Common Block - QPLL Ports ------------------------
QPLLFBCLKLOST => open,
QPLLLOCK => QPLLLOCK_OUT,
QPLLLOCKDETCLK => QPLLLOCKDETCLK_IN,
QPLLLOCKEN => tied_to_vcc_i,
QPLLOUTRESET => tied_to_ground_i,
QPLLPD => tied_to_ground_i,
QPLLREFCLKLOST => QPLLREFCLKLOST_OUT,
QPLLREFCLKSEL => QPLLREFCLKSEL_IN,
QPLLRESET => QPLLRESET_IN,
QPLLRSVD1 => "0000000000000000",
QPLLRSVD2 => "11111",
--------------------------------- QPLL Ports -------------------------------
BGBYPASSB => tied_to_vcc_i,
BGMONITORENB => tied_to_vcc_i,
BGPDB => tied_to_vcc_i,
BGRCALOVRD => "11111",
PMARSVD => "00000000",
RCALENB => tied_to_vcc_i
);
end RTL;
platform/xilinx/wr_gtp_phy/wr_gtx_phy_kintex7.vhd 0 → 100644
View file @ 678491f4
-------------------------------------------------------------------------------
-- Title : Deterministic Xilinx GTX wrapper - kintex-7 top module
-- Project : White Rabbit Switch
-------------------------------------------------------------------------------
-- File : wr_gtx_phy_kintex7.vhd
-- Author : Peter Jansweijer, Tomasz Wlostowski
-- Company : CERN BE-CO-HT
-- Created : 2013-04-08
-- Last update: 2013-04-08
-- Platform : FPGA-generic
-- Standard : VHDL'93
-------------------------------------------------------------------------------
-- Description: Dual channel wrapper for Xilinx Kintex-7 GTX adapted for
-- deterministic delays at 1.25 Gbps.
-------------------------------------------------------------------------------
--
-- Copyright (c) 2010 CERN / Tomasz Wlostowski
--
-- This source file is free software; you can redistribute it
-- and/or modify it under the terms of the GNU Lesser General
-- Public License as published by the Free Software Foundation;
-- either version 2.1 of the License, or (at your option) any
-- later version.
--
-- This source is distributed in the hope that it will be
-- useful, but WITHOUT ANY WARRANTY; without even the implied
-- warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR
-- PURPOSE. See the GNU Lesser General Public License for more
-- details.
--
-- You should have received a copy of the GNU Lesser General
-- Public License along with this source; if not, download it
-- from http://www.gnu.org/licenses/lgpl-2.1.html
--
--
-------------------------------------------------------------------------------
-- Revisions :
-- Date Version Author Description
-- 2013-04-08 0.1 PeterJ Initial release based on "wr_gtx_phy_virtex6.vhd"
-- 2013-08-19 0.2 PeterJ Implemented a small delay before a rx_cdr_lock is propgated
-- 2014-02_19 0.3 Peterj Added tx_locked_o to indicate that the cpll reached the lock status
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use work.gencores_pkg.all;
library unisim;
use unisim.vcomponents.all;
library work;
--use work.gencores_pkg.all;
use work.disparity_gen_pkg.all;
entity wr_gtx_phy_kintex7 is
generic (
-- set to non-zero value to speed up the simulation by reducing some delays
g_simulation : integer := 0
);
port (
-- Dedicated reference 125 MHz clock for the GTX transceiver
clk_gtx_i : in std_logic;
qpll_clk_i : in std_logic;
qpll_refclk_i : in std_logic;
qpll_lockdet_i : in std_logic;
-- TX path, synchronous to tx_out_clk_o (62.5 MHz):
tx_out_clk_o : out std_logic;
tx_locked_o : out std_logic;
-- data input (8 bits, not 8b10b-encoded)
tx_data_i : in std_logic_vector(15 downto 0);
-- 1 when tx_data_i contains a control code, 0 when it's a data byte
tx_k_i : in std_logic_vector(1 downto 0);
-- disparity of the currently transmitted 8b10b code (1 = plus, 0 = minus).
-- Necessary for the PCS to generate proper frame termination sequences.
-- Generated for the 2nd byte (LSB) of tx_data_i.
tx_disparity_o : out std_logic;
-- Encoding error indication (1 = error, 0 = no error)
tx_enc_err_o : out std_logic;
-- RX path, synchronous to ch0_rx_rbclk_o.
-- RX recovered clock
rx_rbclk_o : out std_logic;
-- 8b10b-decoded data output. The data output must be kept invalid before
-- the transceiver is locked on the incoming signal to prevent the EP from
-- detecting a false carrier.
rx_data_o : out std_logic_vector(15 downto 0);
-- 1 when the byte on rx_data_o is a control code
rx_k_o : out std_logic_vector(1 downto 0);
-- encoding error indication
rx_enc_err_o : out std_logic;
-- RX bitslide indication, indicating the delay of the RX path of the
-- transceiver (in UIs). Must be valid when ch0_rx_data_o is valid.
rx_bitslide_o : out std_logic_vector(4 downto 0);
-- reset input, active hi
rst_i : in std_logic;
loopen_i : in std_logic_vector(2 downto 0);
tx_prbs_sel_i : in std_logic_vector(2 downto 0);
pad_txn_o : out std_logic;
pad_txp_o : out std_logic;
pad_rxn_i : in std_logic := '0';
pad_rxp_i : in std_logic := '0';
rdy_o : out std_logic);
end wr_gtx_phy_kintex7;
architecture rtl of wr_gtx_phy_kintex7 is
component WHITERABBIT_GTXE2_CHANNEL_WRAPPER_GT is
generic
(
-- Simulation attributes
GT_SIM_GTRESET_SPEEDUP : string := "TRUE"; -- Set to "TRUE" to speed up sim reset (Need Capital Letters!)
RX_DFE_KL_CFG2_IN : bit_vector := X"3010D90C";
PMA_RSV_IN : bit_vector := X"00018480";
PCS_RSVD_ATTR_IN : bit_vector := X"000000000000"
);
port
(
--------------------------------- CPLL Ports -------------------------------
CPLLFBCLKLOST_OUT : out std_logic;
CPLLLOCK_OUT : out std_logic;
CPLLLOCKDETCLK_IN : in std_logic;
CPLLREFCLKLOST_OUT : out std_logic;
CPLLRESET_IN : in std_logic;
-------------------------- Channel - Clocking Ports ------------------------
GTREFCLK0_IN : in std_logic;
---------------------------- Channel - DRP Ports --------------------------
DRPADDR_IN : in std_logic_vector(8 downto 0);
DRPCLK_IN : in std_logic;
DRPDI_IN : in std_logic_vector(15 downto 0);
DRPDO_OUT : out std_logic_vector(15 downto 0);
DRPEN_IN : in std_logic;
DRPRDY_OUT : out std_logic;
DRPWE_IN : in std_logic;
------------------------------- Clocking Ports -----------------------------
QPLLCLK_IN : in std_logic;
QPLLREFCLK_IN : in std_logic;
------------------------------- Loopback Ports -----------------------------
LOOPBACK_IN : in std_logic_vector(2 downto 0);
--------------------- RX Initialization and Reset Ports --------------------
RXUSERRDY_IN : in std_logic;
-------------------------- RX Margin Analysis Ports ------------------------
EYESCANDATAERROR_OUT : out std_logic;
------------------------- Receive Ports - CDR Ports ------------------------
RXCDRLOCK_OUT : out std_logic;
RXCDRRESET_IN : in std_logic;
------------------ Receive Ports - FPGA RX Interface Ports -----------------
RXUSRCLK_IN : in std_logic;
RXUSRCLK2_IN : in std_logic;
------------------ Receive Ports - FPGA RX interface Ports -----------------
RXDATA_OUT : out std_logic_vector(15 downto 0);
------------------ Receive Ports - RX 8B/10B Decoder Ports -----------------
RXDISPERR_OUT : out std_logic_vector(1 downto 0);
RXNOTINTABLE_OUT : out std_logic_vector(1 downto 0);
--------------------------- Receive Ports - RX AFE -------------------------
GTXRXP_IN : in std_logic;
------------------------ Receive Ports - RX AFE Ports ----------------------
GTXRXN_IN : in std_logic;
-------------- Receive Ports - RX Byte and Word Alignment Ports ------------
RXBYTEISALIGNED_OUT : out std_logic;
RXCOMMADET_OUT : out std_logic;
--------------------- Receive Ports - RX Equilizer Ports -------------------
RXLPMHFHOLD_IN : in std_logic;
RXLPMLFHOLD_IN : in std_logic;
--------------- Receive Ports - RX Fabric Output Control Ports -------------
RXOUTCLK_OUT : out std_logic;
------------- Receive Ports - RX Initialization and Reset Ports ------------
GTRXRESET_IN : in std_logic;
RXPMARESET_IN : in std_logic;
---------------------- Receive Ports - RX gearbox ports --------------------
RXSLIDE_IN : in std_logic;
------------------- Receive Ports - RX8B/10B Decoder Ports -----------------
RXCHARISK_OUT : out std_logic_vector(1 downto 0);
-------------- Receive Ports -RX Initialization and Reset Ports ------------
RXRESETDONE_OUT : out std_logic;
--------------------- TX Initialization and Reset Ports --------------------
GTTXRESET_IN : in std_logic;
TXUSERRDY_IN : in std_logic;
------------------ Transmit Ports - FPGA TX Interface Ports ----------------
TXUSRCLK_IN : in std_logic;
TXUSRCLK2_IN : in std_logic;
------------------ Transmit Ports - TX Data Path interface -----------------
TXDATA_IN : in std_logic_vector(15 downto 0);
---------------- Transmit Ports - TX Driver and OOB signaling --------------
GTXTXN_OUT : out std_logic;
GTXTXP_OUT : out std_logic;
----------- Transmit Ports - TX Fabric Clock Output Control Ports ----------
TXOUTCLK_OUT : out std_logic;
TXOUTCLKFABRIC_OUT : out std_logic;
TXOUTCLKPCS_OUT : out std_logic;
--------------------- Transmit Ports - TX Gearbox Ports --------------------
TXCHARISK_IN : in std_logic_vector(1 downto 0);
------------- Transmit Ports - TX Initialization and Reset Ports -----------
TXRESETDONE_OUT : out std_logic;
------------------ Transmit Ports - pattern Generator Ports ----------------
TXPRBSSEL_IN : in std_logic_vector(2 downto 0)
);
end component WHITERABBIT_GTXE2_CHANNEL_WRAPPER_GT;
component BUFG
port (
O : out std_ulogic;
I : in std_ulogic);
end component;
component gtp_bitslide
generic (
g_simulation : integer;
g_target : string := "virtex6");
port (
gtp_rst_i : in std_logic;
gtp_rx_clk_i : in std_logic;
gtp_rx_comma_det_i : in std_logic;
gtp_rx_byte_is_aligned_i : in std_logic;
serdes_ready_i : in std_logic;
gtp_rx_slide_o : out std_logic;
gtp_rx_cdr_rst_o : out std_logic;
bitslide_o : out std_logic_vector(4 downto 0);
synced_o : out std_logic);
end component;
constant c_rxcdrlock_max : integer := 3;
constant c_reset_cnt_max : integer := 64; -- Reset pulse width 64 * 8 = 512 ns
signal rst_synced : std_logic;
signal rst_int : std_logic;
-- signal trig0, trig1, trig2, trig3 : std_logic_vector(31 downto 0);
signal rx_rec_clk_bufin : std_logic;
signal rx_rec_clk : std_logic;
signal tx_out_clk_bufin : std_logic;
signal tx_out_clk : std_logic;
signal rx_cdr_lock : std_logic;
signal rx_cdr_lock_filtered : std_logic;
signal tx_rst_done, rx_rst_done : std_logic;
signal txpll_lockdet, rxpll_lockdet : std_logic;
signal pll_lockdet : std_logic;
-- signal cpll_lockdet : std_logic;
signal gtreset : std_logic;
signal rx_comma_det : std_logic;
signal rx_byte_is_aligned : std_logic;
signal everything_ready : std_logic;
signal rx_slide : std_logic;
signal rx_cdr_rst : std_logic;
signal rx_synced : std_logic;
signal rst_done : std_logic;
signal rst_done_n : std_logic;
signal rx_k_int : std_logic_vector(1 downto 0);
signal rx_data_int : std_logic_vector(15 downto 0);
signal rx_disp_err, rx_code_err : std_logic_vector(1 downto 0);
signal tx_is_k_swapped : std_logic_vector(1 downto 0);
signal tx_data_swapped : std_logic_vector(15 downto 0);
signal cur_disp : t_8b10b_disparity;
begin -- rtl
-- There is a hen and egg problem with the reset in wr_core. Some reset signals are
-- synchronized by rx_rbclk_o but this signal is de-asserted by the same reset.
-- Therefore the rst_i is made edge sensitive and an internal reset pulse is generated for the PHY.
-- After this reset pulse signal rx_rbclk_o starts clocking again and the (still asserted) system
-- wide reset signal can by synchronized with this clock.
-- Note that the rst_i originates from the clk_sys domain. Synchronisation is not needed
-- when the clk_sys is phase locked with clk_gtx_i (which is usually the case) but is a safety
-- measure. Add a false path for U_EdgeDet_rst_i_reg_sync0 to the timing constraints.
U_EdgeDet_rst_i : gc_sync_ffs port map (
clk_i => clk_gtx_i,
rst_n_i => '1',
data_i => rst_i,
ppulse_o => rst_synced);
p_reset_pulse : process(clk_gtx_i, rst_synced)
variable reset_cnt : integer range 0 to c_reset_cnt_max;
begin
if(rst_synced = '1') then
reset_cnt := 0;
rst_int <= '1';
elsif rising_edge(clk_gtx_i) then
if reset_cnt /= c_reset_cnt_max then
reset_cnt := reset_cnt + 1;
rst_int <= '1';
else
rst_int <= '0';
end if;
end if;
end process;
tx_enc_err_o <= '0';
U_BUF_TxOutClk : BUFG
port map (
I => tx_out_clk_bufin,
O => tx_out_clk);
tx_out_clk_o <= tx_out_clk;
tx_locked_o <= qpll_lockdet_i;
U_BUF_RxRecClk : BUFG
port map (
I => rx_rec_clk_bufin,
O => rx_rec_clk);
rx_rbclk_o <= rx_rec_clk;
tx_is_k_swapped <= tx_k_i(0) & tx_k_i(1);
tx_data_swapped <= tx_data_i(7 downto 0) & tx_data_i(15 downto 8);
U_GTX_INST : WHITERABBIT_GTXE2_CHANNEL_WRAPPER_GT
generic map
(
-- Simulation attributes
GT_SIM_GTRESET_SPEEDUP => "TRUE" -- Set to "true" to speed up sim reset
)
port map
(
--------------------------------- CPLL Ports -------------------------------
CPLLFBCLKLOST_OUT => open,
CPLLLOCK_OUT => open,
CPLLLOCKDETCLK_IN => '0',
CPLLREFCLKLOST_OUT => open,
CPLLRESET_IN => rst_int,
-------------------------- Channel - Clocking Ports ------------------------
GTREFCLK0_IN => '0',
---------------------------- Channel - DRP Ports --------------------------
DRPADDR_IN => (Others => '0'),
DRPCLK_IN => '0',
DRPDI_IN => (Others => '0'),
DRPDO_OUT => open,
DRPEN_IN => '0',
DRPRDY_OUT => open,
DRPWE_IN => '0',
------------------------------- Clocking Ports -----------------------------
QPLLCLK_IN => qpll_clk_i,
QPLLREFCLK_IN => qpll_refclk_i,
------------------------------- Loopback Ports -----------------------------
LOOPBACK_IN => loopen_i,
--------------------- RX Initialization and Reset Ports --------------------
-- RXUSERRDY_IN => rx_cdr_lock,
RXUSERRDY_IN => rx_cdr_lock_filtered,
-------------------------- RX Margin Analysis Ports ------------------------
EYESCANDATAERROR_OUT => open,
------------------------- Receive Ports - CDR Ports ------------------------
RXCDRLOCK_OUT => rx_cdr_lock,
RXCDRRESET_IN => rx_cdr_rst, -- this port cannot be generated by the CoreGen GUI, it cannot be turnes "on" : in std_logic;
------------------ Receive Ports - FPGA RX Interface Ports -----------------
RXUSRCLK_IN => rx_rec_clk,
RXUSRCLK2_IN => rx_rec_clk,
------------------ Receive Ports - FPGA RX interface Ports -----------------
RXDATA_OUT => rx_data_int,
------------------ Receive Ports - RX 8B/10B Decoder Ports -----------------
RXDISPERR_OUT => rx_disp_err,
RXNOTINTABLE_OUT => rx_code_err,
--------------------------- Receive Ports - RX AFE -------------------------
GTXRXP_IN => pad_rxp_i,
------------------------ Receive Ports - RX AFE Ports ----------------------
GTXRXN_IN => pad_rxn_i,
-------------- Receive Ports - RX Byte and Word Alignment Ports ------------
RXBYTEISALIGNED_OUT => rx_byte_is_aligned,
RXCOMMADET_OUT => rx_comma_det,
--------------------- Receive Ports - RX Equilizer Ports -------------------
RXLPMHFHOLD_IN => '0', -- this port is always generated by the CoreGen GUI and cannot be turned "off"
RXLPMLFHOLD_IN => '0', -- this port is always generated by the CoreGen GUI and cannot be turned "off"
--------------- Receive Ports - RX Fabric Output Control Ports -------------
RXOUTCLK_OUT => rx_rec_clk_bufin,
------------- Receive Ports - RX Initialization and Reset Ports ------------
GTRXRESET_IN => gtreset,
RXPMARESET_IN => '0',
---------------------- Receive Ports - RX gearbox ports --------------------
RXSLIDE_IN => rx_slide,
------------------- Receive Ports - RX8B/10B Decoder Ports -----------------
RXCHARISK_OUT => rx_k_int,
-------------- Receive Ports -RX Initialization and Reset Ports ------------
RXRESETDONE_OUT => rx_rst_done,
--------------------- TX Initialization and Reset Ports --------------------
GTTXRESET_IN => gtreset,
TXUSERRDY_IN => qpll_lockdet_i,
------------------ Transmit Ports - FPGA TX Interface Ports ----------------
TXUSRCLK_IN => tx_out_clk,
TXUSRCLK2_IN => tx_out_clk,
------------------ Transmit Ports - TX Data Path interface -----------------
TXDATA_IN => tx_data_swapped,
-- TXDATA_IN => tx_data_i,
---------------- Transmit Ports - TX Driver and OOB signaling --------------
GTXTXN_OUT => pad_txn_o,
GTXTXP_OUT => pad_txp_o,
----------- Transmit Ports - TX Fabric Clock Output Control Ports ----------
TXOUTCLK_OUT => tx_out_clk_bufin,
TXOUTCLKFABRIC_OUT => open,
TXOUTCLKPCS_OUT => open,
--------------------- Transmit Ports - TX Gearbox Ports --------------------
TXCHARISK_IN => tx_is_k_swapped,
-- TXCHARISK_IN => tx_k_i,
------------- Transmit Ports - TX Initialization and Reset Ports -----------
TXRESETDONE_OUT => tx_rst_done,
------------------ Transmit Ports - pattern Generator Ports ----------------
TXPRBSSEL_IN => tx_prbs_sel_i
);
U_Bitslide : gtp_bitslide
generic map (
g_simulation => g_simulation,
g_target => "kintex7")
port map (
gtp_rst_i => rst_done_n,
gtp_rx_clk_i => rx_rec_clk,
gtp_rx_comma_det_i => rx_comma_det,
gtp_rx_byte_is_aligned_i => rx_byte_is_aligned,
serdes_ready_i => everything_ready,
gtp_rx_slide_o => rx_slide,
gtp_rx_cdr_rst_o => rx_cdr_rst,
bitslide_o => rx_bitslide_o,
synced_o => rx_synced);
txpll_lockdet <= qpll_lockdet_i;
rxpll_lockdet <= rx_cdr_lock;
-- rxpll_lockdet <= rx_cdr_lock_filtered; mattia
gtreset <= not qpll_lockdet_i;
rst_done <= rx_rst_done and tx_rst_done;
rst_done_n <= not rst_done;
pll_lockdet <= txpll_lockdet and rxpll_lockdet;
everything_ready <= rst_done and pll_lockdet;
rdy_o <= everything_ready;
-- trig2(3) <= rx_rst_done;
-- trig2(4) <= tx_rst_done;
-- trig2(5) <= txpll_lockdet;
-- trig2(6) <= rxpll_lockdet;
-- trig2(7) <= '1';
-- 2013 August 19: Peterj
-- The family 7 GTX seem to have an artifact in rx_cdr_lock. For no reason lock may be lost for a clock cycle
-- There is not much information on the web but examples of "Series-7 Integrated Block for PCI Express" (pipe_user.v)
-- show that Xilinx itself implements a small delay before an rx_cdr_lock is propagated.
p_rx_cdr_lock_filter : process(rx_rec_clk, rst_int)
variable rxcdrlock_cnt : integer range 0 to c_rxcdrlock_max;
begin
if(rst_int = '1') then
rxcdrlock_cnt := 0;
rx_cdr_lock_filtered <= '0';
elsif rising_edge(rx_rec_clk) then
if rx_cdr_lock = '0' then
if rxcdrlock_cnt /= c_rxcdrlock_max then
rxcdrlock_cnt := rxcdrlock_cnt + 1;
else
rx_cdr_lock_filtered <= '0';
end if;
else
rxcdrlock_cnt := 0;
rx_cdr_lock_filtered <= '1';
end if;
end if;
end process;
p_gen_rx_outputs : process(rx_rec_clk, rst_done_n)
begin
if(rst_done_n = '1') then
rx_data_o <= (others => '0');
rx_k_o <= (others => '0');
rx_enc_err_o <= '0';
elsif rising_edge(rx_rec_clk) then
if(everything_ready = '1' and rx_synced = '1') then
rx_data_o <= rx_data_int(7 downto 0) & rx_data_int(15 downto 8);
rx_k_o <= rx_k_int(0) & rx_k_int(1);
rx_enc_err_o <= rx_disp_err(0) or rx_disp_err(1) or rx_code_err(0) or rx_code_err(1);
else
rx_data_o <= (others => '1');
rx_k_o <= (others => '1');
rx_enc_err_o <= '1';
end if;
end if;
end process;
p_gen_tx_disparity : process(tx_out_clk, rst_done_n)
begin
if rising_edge(tx_out_clk) then
if rst_done_n = '1' then
cur_disp <= RD_MINUS;
else
cur_disp <= f_next_8b10b_disparity16(cur_disp, tx_k_i, tx_data_i);
end if;
end if;
end process;
tx_disparity_o <= to_std_logic(cur_disp);
end rtl;
platform/xilinx/wr_gtxe2_channel_wrapper_gt.vhd 0 → 100644
View file @ 678491f4
-------------------------------------------------------------------------------
-- ____ ____
-- / /\/ /
-- /___/ \ / Vendor: Xilinx
-- \ \ \/ Version : 2.5
-- \ \ Application : 7 Series FPGAs Transceivers Wizard
-- / / Filename : whiterabbit_gtxe2_channel_wrapper_gt.vhd
-- /___/ /\
-- \ \ / \
-- \___\/\___\
--
--
-- Module whiterabbit_gtxe2_channel_wrapper_GT (a GT Wrapper)
-- Generated by Xilinx 7 Series FPGAs Transceivers Wizard
--
--
-- (c) Copyright 2010-2012 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
--***************************** Entity Declaration ****************************
entity whiterabbit_gtxe2_channel_wrapper_GT is
generic
(
-- Simulation attributes
GT_SIM_GTRESET_SPEEDUP : string := "FALSE"; -- Set to "true" to speed up sim reset
RX_DFE_KL_CFG2_IN : bit_vector := X"3010D90C";
PMA_RSV_IN : bit_vector := x"00018480";
PCS_RSVD_ATTR_IN : bit_vector := X"000000000000"
);
port
(
--------------------------------- CPLL Ports -------------------------------
CPLLFBCLKLOST_OUT : out std_logic;
CPLLLOCK_OUT : out std_logic;
CPLLLOCKDETCLK_IN : in std_logic;
CPLLREFCLKLOST_OUT : out std_logic;
CPLLRESET_IN : in std_logic;
-------------------------- Channel - Clocking Ports ------------------------
GTREFCLK0_IN : in std_logic;
---------------------------- Channel - DRP Ports --------------------------
DRPADDR_IN : in std_logic_vector(8 downto 0);
DRPCLK_IN : in std_logic;
DRPDI_IN : in std_logic_vector(15 downto 0);
DRPDO_OUT : out std_logic_vector(15 downto 0);
DRPEN_IN : in std_logic;
DRPRDY_OUT : out std_logic;
DRPWE_IN : in std_logic;
------------------------------- Clocking Ports -----------------------------
QPLLCLK_IN : in std_logic;
QPLLREFCLK_IN : in std_logic;
------------------------------- Loopback Ports -----------------------------
LOOPBACK_IN : in std_logic_vector(2 downto 0);
--------------------- RX Initialization and Reset Ports --------------------
RXUSERRDY_IN : in std_logic;
-------------------------- RX Margin Analysis Ports ------------------------
EYESCANDATAERROR_OUT : out std_logic;
------------------------- Receive Ports - CDR Ports ------------------------
RXCDRLOCK_OUT : out std_logic;
RXCDRRESET_IN : in std_logic;
------------------ Receive Ports - FPGA RX Interface Ports -----------------
RXUSRCLK_IN : in std_logic;
RXUSRCLK2_IN : in std_logic;
------------------ Receive Ports - FPGA RX interface Ports -----------------
RXDATA_OUT : out std_logic_vector(15 downto 0);
------------------ Receive Ports - RX 8B/10B Decoder Ports -----------------
RXDISPERR_OUT : out std_logic_vector(1 downto 0);
RXNOTINTABLE_OUT : out std_logic_vector(1 downto 0);
--------------------------- Receive Ports - RX AFE -------------------------
GTXRXP_IN : in std_logic;
------------------------ Receive Ports - RX AFE Ports ----------------------
GTXRXN_IN : in std_logic;
-------------- Receive Ports - RX Byte and Word Alignment Ports ------------
RXBYTEISALIGNED_OUT : out std_logic;
RXCOMMADET_OUT : out std_logic;
--------------------- Receive Ports - RX Equilizer Ports -------------------
RXLPMHFHOLD_IN : in std_logic;
RXLPMLFHOLD_IN : in std_logic;
--------------- Receive Ports - RX Fabric Output Control Ports -------------
RXOUTCLK_OUT : out std_logic;
------------- Receive Ports - RX Initialization and Reset Ports ------------
GTRXRESET_IN : in std_logic;
RXPMARESET_IN : in std_logic;
---------------------- Receive Ports - RX gearbox ports --------------------
RXSLIDE_IN : in std_logic;
------------------- Receive Ports - RX8B/10B Decoder Ports -----------------
RXCHARISK_OUT : out std_logic_vector(1 downto 0);
-------------- Receive Ports -RX Initialization and Reset Ports ------------
RXRESETDONE_OUT : out std_logic;
--------------------- TX Initialization and Reset Ports --------------------
GTTXRESET_IN : in std_logic;
TXUSERRDY_IN : in std_logic;
------------------ Transmit Ports - FPGA TX Interface Ports ----------------
TXUSRCLK_IN : in std_logic;
TXUSRCLK2_IN : in std_logic;
------------------ Transmit Ports - TX Data Path interface -----------------
TXDATA_IN : in std_logic_vector(15 downto 0);
---------------- Transmit Ports - TX Driver and OOB signaling --------------
GTXTXN_OUT : out std_logic;
GTXTXP_OUT : out std_logic;
----------- Transmit Ports - TX Fabric Clock Output Control Ports ----------
TXOUTCLK_OUT : out std_logic;
TXOUTCLKFABRIC_OUT : out std_logic;
TXOUTCLKPCS_OUT : out std_logic;
--------------------- Transmit Ports - TX Gearbox Ports --------------------
TXCHARISK_IN : in std_logic_vector(1 downto 0);
------------- Transmit Ports - TX Initialization and Reset Ports -----------
TXRESETDONE_OUT : out std_logic;
------------------ Transmit Ports - pattern Generator Ports ----------------
TXPRBSSEL_IN : in std_logic_vector(2 downto 0)
);
end whiterabbit_gtxe2_channel_wrapper_GT;
architecture RTL of whiterabbit_gtxe2_channel_wrapper_GT is
--**************************** Signal Declarations ****************************
-- ground and tied_to_vcc_i signals
signal tied_to_ground_i : std_logic;
signal tied_to_ground_vec_i : std_logic_vector(63 downto 0);
signal tied_to_vcc_i : std_logic;
-- RX Datapath signals
signal rxdata_i : std_logic_vector(63 downto 0);
signal rxchariscomma_float_i : std_logic_vector(5 downto 0);
signal rxcharisk_float_i : std_logic_vector(5 downto 0);
signal rxdisperr_float_i : std_logic_vector(5 downto 0);
signal rxnotintable_float_i : std_logic_vector(5 downto 0);
signal rxrundisp_float_i : std_logic_vector(5 downto 0);
-- TX Datapath signals
signal txdata_i : std_logic_vector(63 downto 0);
signal txkerr_float_i : std_logic_vector(5 downto 0);
signal txrundisp_float_i : std_logic_vector(5 downto 0);
--******************************** Main Body of Code***************************
begin
--------------------------- Static signal Assignments ---------------------
tied_to_ground_i <= '0';
tied_to_ground_vec_i(63 downto 0) <= (others => '0');
tied_to_vcc_i <= '1';
------------------- GT Datapath byte mapping -----------------
RXDATA_OUT <= rxdata_i(15 downto 0);
txdata_i <= (tied_to_ground_vec_i(47 downto 0) & TXDATA_IN);
----------------------------- GTXE2 Instance --------------------------
gtxe2_i :GTXE2_CHANNEL
generic map
(
--_______________________ Simulation-Only Attributes ___________________
SIM_RECEIVER_DETECT_PASS => ("TRUE"),
SIM_RESET_SPEEDUP => (GT_SIM_GTRESET_SPEEDUP),
SIM_TX_EIDLE_DRIVE_LEVEL => ("X"),
SIM_CPLLREFCLK_SEL => ("001"),
SIM_VERSION => ("4.0"),
------------------RX Byte and Word Alignment Attributes---------------
ALIGN_COMMA_DOUBLE => ("FALSE"),
ALIGN_COMMA_ENABLE => ("0001111111"),
ALIGN_COMMA_WORD => (2),
ALIGN_MCOMMA_DET => ("TRUE"),
ALIGN_MCOMMA_VALUE => ("1010000011"),
ALIGN_PCOMMA_DET => ("TRUE"),
ALIGN_PCOMMA_VALUE => ("0101111100"),
SHOW_REALIGN_COMMA => ("FALSE"),
RXSLIDE_AUTO_WAIT => (7),
RXSLIDE_MODE => ("PCS"),
RX_SIG_VALID_DLY => (10),
------------------RX 8B/10B Decoder Attributes---------------
RX_DISPERR_SEQ_MATCH => ("TRUE"),
DEC_MCOMMA_DETECT => ("TRUE"),
DEC_PCOMMA_DETECT => ("TRUE"),
DEC_VALID_COMMA_ONLY => ("TRUE"),
------------------------RX Clock Correction Attributes----------------------
CBCC_DATA_SOURCE_SEL => ("DECODED"),
CLK_COR_SEQ_2_USE => ("FALSE"),
CLK_COR_KEEP_IDLE => ("FALSE"),
CLK_COR_MAX_LAT => (10),
CLK_COR_MIN_LAT => (8),
CLK_COR_PRECEDENCE => ("TRUE"),
CLK_COR_REPEAT_WAIT => (0),
CLK_COR_SEQ_LEN => (1),
CLK_COR_SEQ_1_ENABLE => ("1111"),
CLK_COR_SEQ_1_1 => ("0000000000"),
CLK_COR_SEQ_1_2 => ("0000000000"),
CLK_COR_SEQ_1_3 => ("0000000000"),
CLK_COR_SEQ_1_4 => ("0000000000"),
CLK_CORRECT_USE => ("FALSE"),
CLK_COR_SEQ_2_ENABLE => ("1111"),
CLK_COR_SEQ_2_1 => ("0000000000"),
CLK_COR_SEQ_2_2 => ("0000000000"),
CLK_COR_SEQ_2_3 => ("0000000000"),
CLK_COR_SEQ_2_4 => ("0000000000"),
------------------------RX Channel Bonding Attributes----------------------
CHAN_BOND_KEEP_ALIGN => ("FALSE"),
CHAN_BOND_MAX_SKEW => (1),
CHAN_BOND_SEQ_LEN => (1),
CHAN_BOND_SEQ_1_1 => ("0000000000"),
CHAN_BOND_SEQ_1_2 => ("0000000000"),
CHAN_BOND_SEQ_1_3 => ("0000000000"),
CHAN_BOND_SEQ_1_4 => ("0000000000"),
CHAN_BOND_SEQ_1_ENABLE => ("1111"),
CHAN_BOND_SEQ_2_1 => ("0000000000"),
CHAN_BOND_SEQ_2_2 => ("0000000000"),
CHAN_BOND_SEQ_2_3 => ("0000000000"),
CHAN_BOND_SEQ_2_4 => ("0000000000"),
CHAN_BOND_SEQ_2_ENABLE => ("1111"),
CHAN_BOND_SEQ_2_USE => ("FALSE"),
FTS_DESKEW_SEQ_ENABLE => ("1111"),
FTS_LANE_DESKEW_CFG => ("1111"),
FTS_LANE_DESKEW_EN => ("FALSE"),
---------------------------RX Margin Analysis Attributes----------------------------
ES_CONTROL => ("000000"),
ES_ERRDET_EN => ("FALSE"),
ES_EYE_SCAN_EN => ("TRUE"),
ES_HORZ_OFFSET => (x"000"),
ES_PMA_CFG => ("0000000000"),
ES_PRESCALE => ("00000"),
ES_QUALIFIER => (x"00000000000000000000"),
ES_QUAL_MASK => (x"00000000000000000000"),
ES_SDATA_MASK => (x"00000000000000000000"),
ES_VERT_OFFSET => ("000000000"),
-------------------------FPGA RX Interface Attributes-------------------------
RX_DATA_WIDTH => (20),
---------------------------PMA Attributes----------------------------
OUTREFCLK_SEL_INV => ("11"),
PMA_RSV => (PMA_RSV_IN),
PMA_RSV2 => (x"2040"),
PMA_RSV3 => ("00"),
PMA_RSV4 => (x"00000000"),
RX_BIAS_CFG => ("000000000100"),
DMONITOR_CFG => (x"000A00"),
RX_CM_SEL => ("00"),
RX_CM_TRIM => ("000"),
RX_DEBUG_CFG => ("000000000000"),
RX_OS_CFG => ("0000010000000"),
TERM_RCAL_CFG => ("10000"),
TERM_RCAL_OVRD => ('0'),
TST_RSV => (x"00000000"),
RX_CLK25_DIV => (5),
TX_CLK25_DIV => (5),
UCODEER_CLR => ('0'),
---------------------------PCI Express Attributes----------------------------
PCS_PCIE_EN => ("FALSE"),
---------------------------PCS Attributes----------------------------
PCS_RSVD_ATTR => (PCS_RSVD_ATTR_IN),
-------------RX Buffer Attributes------------
RXBUF_ADDR_MODE => ("FAST"),
RXBUF_EIDLE_HI_CNT => ("1000"),
RXBUF_EIDLE_LO_CNT => ("0000"),
RXBUF_EN => ("TRUE"),
RX_BUFFER_CFG => ("000000"),
RXBUF_RESET_ON_CB_CHANGE => ("TRUE"),
RXBUF_RESET_ON_COMMAALIGN => ("FALSE"),
RXBUF_RESET_ON_EIDLE => ("FALSE"),
RXBUF_RESET_ON_RATE_CHANGE => ("TRUE"),
RXBUFRESET_TIME => ("00001"),
RXBUF_THRESH_OVFLW => (61),
RXBUF_THRESH_OVRD => ("FALSE"),
RXBUF_THRESH_UNDFLW => (4),
RXDLY_CFG => (x"001F"),
RXDLY_LCFG => (x"030"),
RXDLY_TAP_CFG => (x"0000"),
RXPH_CFG => (x"000000"),
RXPHDLY_CFG => (x"084020"),
RXPH_MONITOR_SEL => ("00000"),
RX_XCLK_SEL => ("RXREC"),
RX_DDI_SEL => ("000000"),
RX_DEFER_RESET_BUF_EN => ("TRUE"),
-----------------------CDR Attributes-------------------------
--For GTX only: Display Port, HBR/RBR- set RXCDR_CFG=72'h0380008bff40200002
--For GTX only: Display Port, HBR2 - set RXCDR_CFG=72'h03000023ff10200020
RXCDR_CFG => (x"03000023ff10100020"),
RXCDR_FR_RESET_ON_EIDLE => ('0'),
RXCDR_HOLD_DURING_EIDLE => ('0'),
RXCDR_PH_RESET_ON_EIDLE => ('0'),
RXCDR_LOCK_CFG => ("010101"),
-------------------RX Initialization and Reset Attributes-------------------
RXCDRFREQRESET_TIME => ("00001"),
RXCDRPHRESET_TIME => ("00001"),
RXISCANRESET_TIME => ("00001"),
RXPCSRESET_TIME => ("00001"),
RXPMARESET_TIME => ("00011"),
-------------------RX OOB Signaling Attributes-------------------
RXOOB_CFG => ("0000110"),
-------------------------RX Gearbox Attributes---------------------------
RXGEARBOX_EN => ("FALSE"),
GEARBOX_MODE => ("000"),
-------------------------PRBS Detection Attribute-----------------------
RXPRBS_ERR_LOOPBACK => ('0'),
-------------Power-Down Attributes----------
PD_TRANS_TIME_FROM_P2 => (x"03c"),
PD_TRANS_TIME_NONE_P2 => (x"3c"),
PD_TRANS_TIME_TO_P2 => (x"64"),
-------------RX OOB Signaling Attributes----------
SAS_MAX_COM => (64),
SAS_MIN_COM => (36),
SATA_BURST_SEQ_LEN => ("1111"),
SATA_BURST_VAL => ("100"),
SATA_EIDLE_VAL => ("100"),
SATA_MAX_BURST => (8),
SATA_MAX_INIT => (21),
SATA_MAX_WAKE => (7),
SATA_MIN_BURST => (4),
SATA_MIN_INIT => (12),
SATA_MIN_WAKE => (4),
-------------RX Fabric Clock Output Control Attributes----------
TRANS_TIME_RATE => (x"0E"),
--------------TX Buffer Attributes----------------
TXBUF_EN => ("TRUE"),
TXBUF_RESET_ON_RATE_CHANGE => ("TRUE"),
TXDLY_CFG => (x"001F"),
TXDLY_LCFG => (x"030"),
TXDLY_TAP_CFG => (x"0000"),
TXPH_CFG => (x"0780"),
TXPHDLY_CFG => (x"084020"),
TXPH_MONITOR_SEL => ("00000"),
TX_XCLK_SEL => ("TXOUT"),
-------------------------FPGA TX Interface Attributes-------------------------
TX_DATA_WIDTH => (20),
-------------------------TX Configurable Driver Attributes-------------------------
TX_DEEMPH0 => ("00000"),
TX_DEEMPH1 => ("00000"),
TX_EIDLE_ASSERT_DELAY => ("110"),
TX_EIDLE_DEASSERT_DELAY => ("100"),
TX_LOOPBACK_DRIVE_HIZ => ("FALSE"),
TX_MAINCURSOR_SEL => ('0'),
TX_DRIVE_MODE => ("DIRECT"),
TX_MARGIN_FULL_0 => ("1001110"),
TX_MARGIN_FULL_1 => ("1001001"),
TX_MARGIN_FULL_2 => ("1000101"),
TX_MARGIN_FULL_3 => ("1000010"),
TX_MARGIN_FULL_4 => ("1000000"),
TX_MARGIN_LOW_0 => ("1000110"),
TX_MARGIN_LOW_1 => ("1000100"),
TX_MARGIN_LOW_2 => ("1000010"),
TX_MARGIN_LOW_3 => ("1000000"),
TX_MARGIN_LOW_4 => ("1000000"),
-------------------------TX Gearbox Attributes--------------------------
TXGEARBOX_EN => ("FALSE"),
-------------------------TX Initialization and Reset Attributes--------------------------
TXPCSRESET_TIME => ("00001"),
TXPMARESET_TIME => ("00001"),
-------------------------TX Receiver Detection Attributes--------------------------
TX_RXDETECT_CFG => (x"1832"),
TX_RXDETECT_REF => ("100"),
----------------------------CPLL Attributes----------------------------
CPLL_CFG => (x"BC07DC"),
CPLL_FBDIV => (4),
CPLL_FBDIV_45 => (5),
CPLL_INIT_CFG => (x"00001E"),
CPLL_LOCK_CFG => (x"01E8"),
CPLL_REFCLK_DIV => (1),
RXOUT_DIV => (4),
TXOUT_DIV => (4),
SATA_CPLL_CFG => ("VCO_3000MHZ"),
--------------RX Initialization and Reset Attributes-------------
RXDFELPMRESET_TIME => ("0001111"),
--------------RX Equalizer Attributes-------------
RXLPM_HF_CFG => ("00000011110000"),
RXLPM_LF_CFG => ("00000011110000"),
RX_DFE_GAIN_CFG => (x"020FEA"),
RX_DFE_H2_CFG => ("000000000000"),
RX_DFE_H3_CFG => ("000001000000"),
RX_DFE_H4_CFG => ("00011110000"),
RX_DFE_H5_CFG => ("00011100000"),
RX_DFE_KL_CFG => ("0000011111110"),
RX_DFE_LPM_CFG => (x"0904"),
RX_DFE_LPM_HOLD_DURING_EIDLE => ('0'),
RX_DFE_UT_CFG => ("10001111000000000"),
RX_DFE_VP_CFG => ("00011111100000011"),
-------------------------Power-Down Attributes-------------------------
RX_CLKMUX_PD => ('1'),
TX_CLKMUX_PD => ('1'),
-------------------------FPGA RX Interface Attribute-------------------------
RX_INT_DATAWIDTH => (0),
-------------------------FPGA TX Interface Attribute-------------------------
TX_INT_DATAWIDTH => (0),
------------------TX Configurable Driver Attributes---------------
TX_QPI_STATUS_EN => ('0'),
-------------------------RX Equalizer Attributes--------------------------
RX_DFE_KL_CFG2 => (RX_DFE_KL_CFG2_IN),
RX_DFE_XYD_CFG => ("0000000000000"),
-------------------------TX Configurable Driver Attributes--------------------------
TX_PREDRIVER_MODE => ('0')
)
port map
(
--------------------------------- CPLL Ports -------------------------------
CPLLFBCLKLOST => CPLLFBCLKLOST_OUT,
CPLLLOCK => CPLLLOCK_OUT,
CPLLLOCKDETCLK => CPLLLOCKDETCLK_IN,
CPLLLOCKEN => tied_to_vcc_i,
CPLLPD => tied_to_ground_i,
CPLLREFCLKLOST => CPLLREFCLKLOST_OUT,
CPLLREFCLKSEL => "001",
CPLLRESET => CPLLRESET_IN,
GTRSVD => "0000000000000000",
PCSRSVDIN => "0000000000000000",
PCSRSVDIN2 => "00000",
PMARSVDIN => "00000",
PMARSVDIN2 => "00000",
TSTIN => "11111111111111111111",
TSTOUT => open,
---------------------------------- Channel ---------------------------------
CLKRSVD => "0000",
-------------------------- Channel - Clocking Ports ------------------------
GTGREFCLK => tied_to_ground_i,
GTNORTHREFCLK0 => tied_to_ground_i,
GTNORTHREFCLK1 => tied_to_ground_i,
GTREFCLK0 => GTREFCLK0_IN,
GTREFCLK1 => tied_to_ground_i,
GTSOUTHREFCLK0 => tied_to_ground_i,
GTSOUTHREFCLK1 => tied_to_ground_i,
---------------------------- Channel - DRP Ports --------------------------
DRPADDR => DRPADDR_IN,
DRPCLK => DRPCLK_IN,
DRPDI => DRPDI_IN,
DRPDO => DRPDO_OUT,
DRPEN => DRPEN_IN,
DRPRDY => DRPRDY_OUT,
DRPWE => DRPWE_IN,
------------------------------- Clocking Ports -----------------------------
GTREFCLKMONITOR => open,
QPLLCLK => QPLLCLK_IN,
QPLLREFCLK => QPLLREFCLK_IN,
RXSYSCLKSEL => "00",
TXSYSCLKSEL => "00",
--------------------------- Digital Monitor Ports --------------------------
DMONITOROUT => open,
----------------- FPGA TX Interface Datapath Configuration ----------------
TX8B10BEN => tied_to_vcc_i,
------------------------------- Loopback Ports -----------------------------
LOOPBACK => LOOPBACK_IN,
----------------------------- PCI Express Ports ----------------------------
PHYSTATUS => open,
RXRATE => tied_to_ground_vec_i(2 downto 0),
RXVALID => open,
------------------------------ Power-Down Ports ----------------------------
RXPD => "00",
TXPD => "00",
-------------------------- RX 8B/10B Decoder Ports -------------------------
SETERRSTATUS => tied_to_ground_i,
--------------------- RX Initialization and Reset Ports --------------------
EYESCANRESET => tied_to_ground_i,
RXUSERRDY => RXUSERRDY_IN,
-------------------------- RX Margin Analysis Ports ------------------------
EYESCANDATAERROR => EYESCANDATAERROR_OUT,
EYESCANMODE => tied_to_ground_i,
EYESCANTRIGGER => tied_to_ground_i,
------------------------- Receive Ports - CDR Ports ------------------------
RXCDRFREQRESET => tied_to_ground_i,
RXCDRHOLD => tied_to_ground_i,
RXCDRLOCK => RXCDRLOCK_OUT,
RXCDROVRDEN => tied_to_ground_i,
-- RXCDRRESET => tied_to_ground_i,
RXCDRRESET => RXCDRRESET_IN,
RXCDRRESETRSV => tied_to_ground_i,
------------------- Receive Ports - Clock Correction Ports -----------------
RXCLKCORCNT => open,
---------- Receive Ports - FPGA RX Interface Datapath Configuration --------
RX8B10BEN => tied_to_vcc_i,
------------------ Receive Ports - FPGA RX Interface Ports -----------------
RXUSRCLK => RXUSRCLK_IN,
RXUSRCLK2 => RXUSRCLK2_IN,
------------------ Receive Ports - FPGA RX interface Ports -----------------
RXDATA => rxdata_i,
------------------- Receive Ports - Pattern Checker Ports ------------------
RXPRBSERR => open,
RXPRBSSEL => tied_to_ground_vec_i(2 downto 0),
------------------- Receive Ports - Pattern Checker ports ------------------
RXPRBSCNTRESET => tied_to_ground_i,
-------------------- Receive Ports - RX Equalizer Ports -------------------
RXDFEXYDEN => tied_to_ground_i,
RXDFEXYDHOLD => tied_to_ground_i,
RXDFEXYDOVRDEN => tied_to_ground_i,
------------------ Receive Ports - RX 8B/10B Decoder Ports -----------------
RXDISPERR(7 downto 2) => rxdisperr_float_i,
RXDISPERR(1 downto 0) => RXDISPERR_OUT,
RXNOTINTABLE(7 downto 2) => rxnotintable_float_i,
RXNOTINTABLE(1 downto 0) => RXNOTINTABLE_OUT,
--------------------------- Receive Ports - RX AFE -------------------------
GTXRXP => GTXRXP_IN,
------------------------ Receive Ports - RX AFE Ports ----------------------
GTXRXN => GTXRXN_IN,
------------------- Receive Ports - RX Buffer Bypass Ports -----------------
RXBUFRESET => tied_to_ground_i,
RXBUFSTATUS => open,
RXDDIEN => tied_to_ground_i,
RXDLYBYPASS => tied_to_vcc_i,
RXDLYEN => tied_to_ground_i,
RXDLYOVRDEN => tied_to_ground_i,
RXDLYSRESET => tied_to_ground_i,
RXDLYSRESETDONE => open,
RXPHALIGN => tied_to_ground_i,
RXPHALIGNDONE => open,
RXPHALIGNEN => tied_to_ground_i,
RXPHDLYPD => tied_to_ground_i,
RXPHDLYRESET => tied_to_ground_i,
RXPHMONITOR => open,
RXPHOVRDEN => tied_to_ground_i,
RXPHSLIPMONITOR => open,
RXSTATUS => open,
-------------- Receive Ports - RX Byte and Word Alignment Ports ------------
RXBYTEISALIGNED => RXBYTEISALIGNED_OUT,
RXBYTEREALIGN => open,
RXCOMMADET => RXCOMMADET_OUT,
RXCOMMADETEN => tied_to_vcc_i,
RXMCOMMAALIGNEN => tied_to_ground_i,
RXPCOMMAALIGNEN => tied_to_ground_i,
------------------ Receive Ports - RX Channel Bonding Ports ----------------
RXCHANBONDSEQ => open,
RXCHBONDEN => tied_to_ground_i,
RXCHBONDLEVEL => tied_to_ground_vec_i(2 downto 0),
RXCHBONDMASTER => tied_to_ground_i,
RXCHBONDO => open,
RXCHBONDSLAVE => tied_to_ground_i,
----------------- Receive Ports - RX Channel Bonding Ports ----------------
RXCHANISALIGNED => open,
RXCHANREALIGN => open,
--------------------- Receive Ports - RX Equalizer Ports -------------------
RXDFEAGCHOLD => tied_to_ground_i,
RXDFEAGCOVRDEN => tied_to_ground_i,
RXDFECM1EN => tied_to_ground_i,
RXDFELFHOLD => tied_to_ground_i,
RXDFELFOVRDEN => tied_to_ground_i,
RXDFELPMRESET => tied_to_ground_i,
RXDFETAP2HOLD => tied_to_ground_i,
RXDFETAP2OVRDEN => tied_to_ground_i,
RXDFETAP3HOLD => tied_to_ground_i,
RXDFETAP3OVRDEN => tied_to_ground_i,
RXDFETAP4HOLD => tied_to_ground_i,
RXDFETAP4OVRDEN => tied_to_ground_i,
RXDFETAP5HOLD => tied_to_ground_i,
RXDFETAP5OVRDEN => tied_to_ground_i,
RXDFEUTHOLD => tied_to_ground_i,
RXDFEUTOVRDEN => tied_to_ground_i,
RXDFEVPHOLD => tied_to_ground_i,
RXDFEVPOVRDEN => tied_to_ground_i,
RXDFEVSEN => tied_to_ground_i,
RXLPMLFKLOVRDEN => tied_to_ground_i,
RXMONITOROUT => open,
RXMONITORSEL => "00",
RXOSHOLD => tied_to_ground_i,
RXOSOVRDEN => tied_to_ground_i,
--------------------- Receive Ports - RX Equilizer Ports -------------------
RXLPMHFHOLD => RXLPMHFHOLD_IN,
RXLPMHFOVRDEN => tied_to_ground_i,
RXLPMLFHOLD => RXLPMLFHOLD_IN,
------------ Receive Ports - RX Fabric ClocK Output Control Ports ----------
RXRATEDONE => open,
--------------- Receive Ports - RX Fabric Output Control Ports -------------
RXOUTCLK => RXOUTCLK_OUT,
RXOUTCLKFABRIC => open,
RXOUTCLKPCS => open,
RXOUTCLKSEL => "010",
---------------------- Receive Ports - RX Gearbox Ports --------------------
RXDATAVALID => open,
RXHEADER => open,
RXHEADERVALID => open,
RXSTARTOFSEQ => open,
--------------------- Receive Ports - RX Gearbox Ports --------------------
RXGEARBOXSLIP => tied_to_ground_i,
------------- Receive Ports - RX Initialization and Reset Ports ------------
GTRXRESET => GTRXRESET_IN,
RXOOBRESET => tied_to_ground_i,
RXPCSRESET => tied_to_ground_i,
RXPMARESET => RXPMARESET_IN,
------------------ Receive Ports - RX Margin Analysis ports ----------------
RXLPMEN => tied_to_vcc_i,
------------------- Receive Ports - RX OOB Signaling ports -----------------
RXCOMSASDET => open,
RXCOMWAKEDET => open,
------------------ Receive Ports - RX OOB Signaling ports -----------------
RXCOMINITDET => open,
------------------ Receive Ports - RX OOB signalling Ports -----------------
RXELECIDLE => open,
RXELECIDLEMODE => "11",
----------------- Receive Ports - RX Polarity Control Ports ----------------
RXPOLARITY => tied_to_ground_i,
---------------------- Receive Ports - RX gearbox ports --------------------
RXSLIDE => RXSLIDE_IN,
------------------- Receive Ports - RX8B/10B Decoder Ports -----------------
RXCHARISCOMMA => open,
RXCHARISK(7 downto 2) => rxcharisk_float_i,
RXCHARISK(1 downto 0) => RXCHARISK_OUT,
------------------ Receive Ports - Rx Channel Bonding Ports ----------------
RXCHBONDI => "00000",
-------------- Receive Ports -RX Initialization and Reset Ports ------------
RXRESETDONE => RXRESETDONE_OUT,
-------------------------------- Rx AFE Ports ------------------------------
RXQPIEN => tied_to_ground_i,
RXQPISENN => open,
RXQPISENP => open,
--------------------------- TX Buffer Bypass Ports -------------------------
TXPHDLYTSTCLK => tied_to_ground_i,
------------------------ TX Configurable Driver Ports ----------------------
TXPOSTCURSOR => "00000",
TXPOSTCURSORINV => tied_to_ground_i,
TXPRECURSOR => tied_to_ground_vec_i(4 downto 0),
TXPRECURSORINV => tied_to_ground_i,
TXQPIBIASEN => tied_to_ground_i,
TXQPISTRONGPDOWN => tied_to_ground_i,
TXQPIWEAKPUP => tied_to_ground_i,
--------------------- TX Initialization and Reset Ports --------------------
CFGRESET => tied_to_ground_i,
GTTXRESET => GTTXRESET_IN,
PCSRSVDOUT => open,
TXUSERRDY => TXUSERRDY_IN,
---------------------- Transceiver Reset Mode Operation --------------------
GTRESETSEL => tied_to_ground_i,
RESETOVRD => tied_to_ground_i,
---------------- Transmit Ports - 8b10b Encoder Control Ports --------------
TXCHARDISPMODE => tied_to_ground_vec_i(7 downto 0),
TXCHARDISPVAL => tied_to_ground_vec_i(7 downto 0),
------------------ Transmit Ports - FPGA TX Interface Ports ----------------
TXUSRCLK => TXUSRCLK_IN,
TXUSRCLK2 => TXUSRCLK2_IN,
--------------------- Transmit Ports - PCI Express Ports -------------------
TXELECIDLE => tied_to_ground_i,
TXMARGIN => tied_to_ground_vec_i(2 downto 0),
TXRATE => tied_to_ground_vec_i(2 downto 0),
TXSWING => tied_to_ground_i,
------------------ Transmit Ports - Pattern Generator Ports ----------------
TXPRBSFORCEERR => tied_to_ground_i,
------------------ Transmit Ports - TX Buffer Bypass Ports -----------------
TXDLYBYPASS => tied_to_vcc_i,
TXDLYEN => tied_to_ground_i,
TXDLYHOLD => tied_to_ground_i,
TXDLYOVRDEN => tied_to_ground_i,
TXDLYSRESET => tied_to_ground_i,
TXDLYSRESETDONE => open,
TXDLYUPDOWN => tied_to_ground_i,
TXPHALIGN => tied_to_ground_i,
TXPHALIGNDONE => open,
TXPHALIGNEN => tied_to_ground_i,
TXPHDLYPD => tied_to_ground_i,
TXPHDLYRESET => tied_to_ground_i,
TXPHINIT => tied_to_ground_i,
TXPHINITDONE => open,
TXPHOVRDEN => tied_to_ground_i,
---------------------- Transmit Ports - TX Buffer Ports --------------------
TXBUFSTATUS => open,
--------------- Transmit Ports - TX Configurable Driver Ports --------------
TXBUFDIFFCTRL => "100",
TXDEEMPH => tied_to_ground_i,
TXDIFFCTRL => "1000",
TXDIFFPD => tied_to_ground_i,
TXINHIBIT => tied_to_ground_i,
TXMAINCURSOR => "0000000",
TXPISOPD => tied_to_ground_i,
------------------ Transmit Ports - TX Data Path interface -----------------
TXDATA => txdata_i,
---------------- Transmit Ports - TX Driver and OOB signaling --------------
GTXTXN => GTXTXN_OUT,
GTXTXP => GTXTXP_OUT,
----------- Transmit Ports - TX Fabric Clock Output Control Ports ----------
TXOUTCLK => TXOUTCLK_OUT,
TXOUTCLKFABRIC => TXOUTCLKFABRIC_OUT,
TXOUTCLKPCS => TXOUTCLKPCS_OUT,
TXOUTCLKSEL => "010",
TXRATEDONE => open,
--------------------- Transmit Ports - TX Gearbox Ports --------------------
TXCHARISK(7 downto 2) => tied_to_ground_vec_i(5 downto 0),
TXCHARISK(1 downto 0) => TXCHARISK_IN,
TXGEARBOXREADY => open,
TXHEADER => tied_to_ground_vec_i(2 downto 0),
TXSEQUENCE => tied_to_ground_vec_i(6 downto 0),
TXSTARTSEQ => tied_to_ground_i,
------------- Transmit Ports - TX Initialization and Reset Ports -----------
TXPCSRESET => tied_to_ground_i,
TXPMARESET => tied_to_ground_i,
TXRESETDONE => TXRESETDONE_OUT,
------------------ Transmit Ports - TX OOB signalling Ports ----------------
TXCOMFINISH => open,
TXCOMINIT => tied_to_ground_i,
TXCOMSAS => tied_to_ground_i,
TXCOMWAKE => tied_to_ground_i,
TXPDELECIDLEMODE => tied_to_ground_i,
----------------- Transmit Ports - TX Polarity Control Ports ---------------
TXPOLARITY => tied_to_ground_i,
--------------- Transmit Ports - TX Receiver Detection Ports --------------
TXDETECTRX => tied_to_ground_i,
------------------ Transmit Ports - TX8b/10b Encoder Ports -----------------
TX8B10BBYPASS => tied_to_ground_vec_i(7 downto 0),
------------------ Transmit Ports - pattern Generator Ports ----------------
TXPRBSSEL => TXPRBSSEL_IN,
----------------------- Tx Configurable Driver Ports ----------------------
TXQPISENN => open,
TXQPISENP => open
);
end RTL;
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