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5886ad1e
Commit
5886ad1e
authored
May 17, 2022
by
Peter Jansweijer
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Plain Diff
clbv2, clbv4 use low phase drift phy
parent
9d6045b8
Pipeline
#3703
failed with stage
Changes
10
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1
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10 changed files
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626 additions
and
297 deletions
+626
-297
wr_clbv2_pkg.vhd
board/clbv2/wr_clbv2_pkg.vhd
+5
-5
wrc_board_clbv2.vhd
board/clbv2/wrc_board_clbv2.vhd
+9
-5
xwrc_board_clbv2.vhd
board/clbv2/xwrc_board_clbv2.vhd
+250
-56
wr_clbv4_pkg.vhd
board/clbv4/wr_clbv4_pkg.vhd
+139
-139
wrc_board_clbv4.vhd
board/clbv4/wrc_board_clbv4.vhd
+5
-5
xwrc_board_clbv4.vhd
board/clbv4/xwrc_board_clbv4.vhd
+194
-59
clbv2_wr_ref_top.vhd
top/clbv2_ref_design/clbv2_wr_ref_top.vhd
+4
-4
clbv2_wr_ref_top.xdc
top/clbv2_ref_design/clbv2_wr_ref_top.xdc
+12
-13
clbv4_wr_ref_top.vhd
top/clbv4_ref_design/clbv4_wr_ref_top.vhd
+4
-5
clbv4_wr_ref_top.xdc
top/clbv4_ref_design/clbv4_wr_ref_top.xdc
+4
-6
No files found.
board/clbv2/wr_clbv2_pkg.vhd
View file @
5886ad1e
...
...
@@ -7,7 +7,7 @@
-- Author(s) : Peter Jansweijer <peterj@nikhef.nl>
-- Company : Nikhef
-- Created : 2017-11-08
-- Last update: 20
17-11-0
8
-- Last update: 20
22-05-1
8
-- Standard : VHDL'93
-------------------------------------------------------------------------------
-- Copyright (c) 2017 Nikhef
...
...
@@ -63,8 +63,8 @@ package wr_clbv2_pkg is
areset_n_i
:
in
std_logic
;
areset_edge_n_i
:
in
std_logic
:
=
'1'
;
clk_20m_vcxo_i
:
in
std_logic
;
clk_125m_gt
p
_n_i
:
in
std_logic
;
clk_125m_gt
p
_p_i
:
in
std_logic
;
clk_125m_gt
x
_n_i
:
in
std_logic
;
clk_125m_gt
x
_p_i
:
in
std_logic
;
clk_aux_i
:
in
std_logic_vector
(
g_aux_clks
-1
downto
0
)
:
=
(
others
=>
'0'
);
clk_10m_ext_i
:
in
std_logic
:
=
'0'
;
pps_ext_i
:
in
std_logic
:
=
'0'
;
...
...
@@ -158,8 +158,8 @@ package wr_clbv2_pkg is
areset_n_i
:
in
std_logic
;
areset_edge_n_i
:
in
std_logic
:
=
'1'
;
clk_20m_vcxo_i
:
in
std_logic
;
clk_125m_gt
p
_n_i
:
in
std_logic
;
clk_125m_gt
p
_p_i
:
in
std_logic
;
clk_125m_gt
x
_n_i
:
in
std_logic
;
clk_125m_gt
x
_p_i
:
in
std_logic
;
clk_10m_ext_i
:
in
std_logic
:
=
'0'
;
pps_ext_i
:
in
std_logic
:
=
'0'
;
clk_sys_62m5_o
:
out
std_logic
;
...
...
board/clbv2/wrc_board_clbv2.vhd
View file @
5886ad1e
...
...
@@ -7,7 +7,7 @@
-- Author(s) : Peter Jansweijer <peterj@nikhef.nl>
-- Company : Nikhef
-- Created : 2017-11-08
-- Last update: 20
17-11-0
8
-- Last update: 20
22-05-1
8
-- Standard : VHDL'93
-------------------------------------------------------------------------------
-- Description: Top-level wrapper for WR PTP core including all the modules
...
...
@@ -88,8 +88,8 @@ entity wrc_board_clbv2 is
areset_edge_n_i
:
in
std_logic
:
=
'1'
;
-- Clock inputs from the board
clk_20m_vcxo_i
:
in
std_logic
;
clk_125m_gt
p
_n_i
:
in
std_logic
;
clk_125m_gt
p
_p_i
:
in
std_logic
;
clk_125m_gt
x
_n_i
:
in
std_logic
;
clk_125m_gt
x
_p_i
:
in
std_logic
;
-- 10MHz ext ref clock input (g_with_external_clock_input = TRUE)
clk_10m_ext_i
:
in
std_logic
:
=
'0'
;
-- External PPS input (g_with_external_clock_input = TRUE)
...
...
@@ -287,6 +287,10 @@ architecture std_wrapper of wrc_board_clbv2 is
signal
wrf_snk_out
:
t_wrf_sink_out
;
signal
wrf_snk_in
:
t_wrf_sink_in
;
-- External WB interface
-- Etherbone interface
-- Aux diagnostics
constant
c_diag_ro_size
:
integer
:
=
g_diag_ro_vector_width
/
32
;
constant
c_diag_rw_size
:
integer
:
=
g_diag_rw_vector_width
/
32
;
...
...
@@ -363,8 +367,8 @@ begin -- architecture struct
areset_n_i
=>
areset_n_i
,
areset_edge_n_i
=>
areset_edge_n_i
,
clk_20m_vcxo_i
=>
clk_20m_vcxo_i
,
clk_125m_gt
p_n_i
=>
clk_125m_gtp
_n_i
,
clk_125m_gt
p_p_i
=>
clk_125m_gtp
_p_i
,
clk_125m_gt
x_n_i
=>
clk_125m_gtx
_n_i
,
clk_125m_gt
x_p_i
=>
clk_125m_gtx
_p_i
,
clk_10m_ext_i
=>
clk_10m_ext_i
,
pps_ext_i
=>
pps_ext_i
,
clk_sys_62m5_o
=>
clk_sys_62m5_o
,
...
...
board/clbv2/xwrc_board_clbv2.vhd
View file @
5886ad1e
This diff is collapsed.
Click to expand it.
board/clbv4/wr_clbv4_pkg.vhd
View file @
5886ad1e
...
...
@@ -7,7 +7,7 @@
-- Author(s) : Pascal Bos
-- Company : Nikhef
-- Created : 2019-06-18
-- Last update: 20
19-06
-18
-- Last update: 20
2-05
-18
-- Standard : VHDL'93
-------------------------------------------------------------------------------
-- Copyright (c) 2017 Nikhef
...
...
@@ -163,8 +163,8 @@ package wr_CLBv4_pkg is
areset_edge_n_i
:
in
std_logic
:
=
'1'
;
clk_125m_dmtd_n_i
:
in
std_logic
;
clk_125m_dmtd_p_i
:
in
std_logic
;
clk_125m_gt
p_n_i
:
in
std_logic
;
clk_125m_gt
p_p_i
:
in
std_logic
;
clk_125m_gt
x_n_i
:
in
std_logic
;
clk_125m_gt
x_p_i
:
in
std_logic
;
clk_10m_ext_i
:
in
std_logic
:
=
'0'
;
pps_ext_i
:
in
std_logic
:
=
'0'
;
clk_sys_62m5_o
:
out
std_logic
;
...
...
board/clbv4/wrc_board_clbv4.vhd
View file @
5886ad1e
...
...
@@ -7,7 +7,7 @@
-- Author(s) : Pascal Bos <bosp@nikhef.nl>
-- Company : Nikhef
-- Created : 2019-05-22
-- Last update: 20
19-05-22
-- Last update: 20
22-05-18
-- Standard : VHDL'93
-------------------------------------------------------------------------------
-- Description: Top-level wrapper for WR PTP core including all the modules
...
...
@@ -89,8 +89,8 @@ entity wrc_board_clbv4 is
-- Clock inputs from the board
clk_125m_dmtd_p_i
:
in
std_logic
;
clk_125m_dmtd_n_i
:
in
std_logic
;
clk_125m_gt
p
_n_i
:
in
std_logic
;
clk_125m_gt
p
_p_i
:
in
std_logic
;
clk_125m_gt
x
_n_i
:
in
std_logic
;
clk_125m_gt
x
_p_i
:
in
std_logic
;
-- 10MHz ext ref clock input (g_with_external_clock_input = TRUE)
clk_10m_ext_i
:
in
std_logic
:
=
'0'
;
-- External PPS input (g_with_external_clock_input = TRUE)
...
...
board/clbv4/xwrc_board_clbv4.vhd
View file @
5886ad1e
This diff is collapsed.
Click to expand it.
top/clbv2_ref_design/clbv2_wr_ref_top.vhd
View file @
5886ad1e
...
...
@@ -7,8 +7,8 @@
-- File : clbv2_wr_ref_top.vhd
-- Author(s) : Peter Jansweijer <peterj@nikhef.nl>
-- Company : Nikhef
-- Created : 20
17-11
-08
-- Last update: 20
19-06-2
8
-- Created : 20
22-05
-08
-- Last update: 20
22-05-1
8
-- Standard : VHDL'93
-------------------------------------------------------------------------------
-- Description: Top-level file for the WRPC reference design on the CLBv2.
...
...
@@ -245,8 +245,8 @@ begin -- architecture top
port
map
(
areset_n_i
=>
reset_n
,
clk_20m_vcxo_i
=>
clk_20m_vcxo_i
,
clk_125m_gt
p
_n_i
=>
clk_125m_gtx_n_i
,
clk_125m_gt
p
_p_i
=>
clk_125m_gtx_p_i
,
clk_125m_gt
x
_n_i
=>
clk_125m_gtx_n_i
,
clk_125m_gt
x
_p_i
=>
clk_125m_gtx_p_i
,
clk_10m_ext_i
=>
clk_ext_10m
,
clk_sys_62m5_o
=>
clk_sys_62m5
,
clk_ref_62m5_o
=>
clk_ref_62m5
,
...
...
top/clbv2_ref_design/clbv2_wr_ref_top.xdc
View file @
5886ad1e
...
...
@@ -12,22 +12,22 @@ set_property PACKAGE_PIN D6 [get_ports clk_125m_gtx_p_i]
set_property PACKAGE_PIN D5 [get_ports clk_125m_gtx_n_i]
create_clock -period 50.000 -name clk_20m_vcxo_i -waveform {0.000 25.000} [get_ports clk_20m_vcxo_i]
create_clock -period 8.000 -name clk_125m_gtx
_p_i
-waveform {0.000 4.000} [get_ports clk_125m_gtx_p_i]
#create_clock -period 8.000 -name clk_125m_gtx
_n_i
-waveform {0.000 4.000} [get_ports clk_125m_gtx_n_i] # AR57109: "Only P side needs constraint"
create_clock -period 8.000 -name clk_125m_gtx -waveform {0.000 4.000} [get_ports clk_125m_gtx_p_i]
#create_clock -period 8.000 -name clk_125m_gtx -waveform {0.000 4.000} [get_ports clk_125m_gtx_n_i] # AR57109: "Only P side needs constraint"
create_clock -period 16.000 -name RXOUTCLK -waveform {0.000 8.000} [get_pins cmp_xwrc_board_clbv2/cmp_
xwrc_platform/gen_phy_kintex7.cmp_gtx
/U_GTX_INST/gtxe2_i/RXOUTCLK]
create_clock -period 16.000 -name TXOUTCLK -waveform {0.000 8.000} [get_pins cmp_xwrc_board_clbv2/cmp_
xwrc_platform/gen_phy_kintex7.cmp_gtx
/U_GTX_INST/gtxe2_i/TXOUTCLK]
create_clock -period 16.000 -name RXOUTCLK -waveform {0.000 8.000} [get_pins cmp_xwrc_board_clbv2/cmp_
gtx_lp
/U_GTX_INST/gtxe2_i/RXOUTCLK]
create_clock -period 16.000 -name TXOUTCLK -waveform {0.000 8.000} [get_pins cmp_xwrc_board_clbv2/cmp_
gtx_lp
/U_GTX_INST/gtxe2_i/TXOUTCLK]
create_clock -period 100.000 -name dio_clk_p_i -waveform {0.000 50.000} [get_ports dio_clk_p_i]
set_clock_groups -asynchronous \
-group
{clk_sys }
\
-group
{clk_dmtd }
\
-group
{clk_20m_vcxo_i }
\
-group
{clk_125m_gtx_p_i }
\
-group
{RXOUTCLK}
\
-group
{TXOUTCLK}
\
-group
{clk_ext_mul }
\
-group
{dio_clk_p_i}
-group
clk_20m_vcxo_i
\
-group
clk_dmtd_pll
\
-group
clk_125m_gtx
\
-group
clk_125m_gtx_odiv2
\
-group
RXOUTCLK
\
-group
TXOUTCLK
\
-group
clk_ext_mul
\
-group
dio_clk_p_i
# ---------------------------------------------------------------------------
# -- SPI interface to DACs
...
...
@@ -222,7 +222,6 @@ set_property IOSTANDARD LVDS_25 [get_ports {dio_p_i[0]}]
set_property PACKAGE_PIN P20 [get_ports {dio_n_i[0]}]
set_property IOSTANDARD LVDS_25 [get_ports {dio_n_i[0]}]
# -- Differential outputs. When the I/O (N+1) is configured as output (i.e. when
# -- dio_oe_n_o(N) = 0), the value of dio_p_o(N) determines the logic state
# -- of I/O (N+1) on the front panel of the mezzanine
...
...
top/clbv4_ref_design/clbv4_wr_ref_top.vhd
View file @
5886ad1e
...
...
@@ -7,8 +7,8 @@
-- File : clbv4_wr_ref_top.vhd
-- Author(s) : Pascal Bos <bosp@nikhef.nl>
-- Company : Nikhef
-- Created : 20
19-05-06
-- Last update: 20
19-05-06
-- Created : 20
22-05-18
-- Last update: 20
22-05-18
-- Standard : VHDL'93
-------------------------------------------------------------------------------
-- Description: Top-level file for the WRPC reference design on the clbv4.
...
...
@@ -128,7 +128,7 @@ entity clbv4_wr_ref_top is
---------------------------------------------------------------------------
---------------------------------------------------------------------------
-- Miscellanous clbv
3
pins
-- Miscellanous clbv
4
pins
---------------------------------------------------------------------------
-- Red LED next to the SFP: blinking indicates that packets are being
-- transferred.
...
...
@@ -183,8 +183,7 @@ entity clbv4_wr_ref_top is
dio_led_top_o
:
out
std_logic
;
dio_led_bot_o
:
out
std_logic
;
-- I2C interface for accessing FMC EEPROM. Deprecated, was used in
-- pre-v3.0 releases to store WRPC configuration. Now we use Flash for this.
-- I2C interface for accessing EEPROM.
eeprom_scl_b
:
inout
std_logic
;
eeprom_sda_b
:
inout
std_logic
;
...
...
top/clbv4_ref_design/clbv4_wr_ref_top.xdc
View file @
5886ad1e
...
...
@@ -11,7 +11,7 @@ set_property IOSTANDARD LVDS_25 [get_ports clk_125m_dmtd_n_i]
create_clock -period 8.000 -name clk_125m_dmtd_p_i -waveform {0.000 4.000} [get_ports clk_125m_dmtd_p_i]
#create_clock -period 8.000 -name clk_125m_dmtd_n_i -waveform {0.000 4.000} [get_ports clk_125m_dmtd_n_i] # AR57109: "Only P side needs constraint"
create_generated_clock -name clk_dmtd -source [get_ports clk_125m_dmtd_p_i] -divide_by 2 [get_pins cmp_xwrc_board_clbv4/c
mp_xwrc_platform/gen_default_plls.gen_kintex7_artix7_default_plls.gen_kintex7_artix7_direct_dmtd.c
lk_dmtd_reg/Q]
create_generated_clock -name clk_dmtd -source [get_ports clk_125m_dmtd_p_i] -divide_by 2 [get_pins cmp_xwrc_board_clbv4/clk_dmtd_reg/Q]
#Bank 116 -- 125.000 MHz GTP reference
set_property PACKAGE_PIN D6 [get_ports clk_125m_gtx_p_i]
...
...
@@ -20,12 +20,11 @@ set_property PACKAGE_PIN D5 [get_ports clk_125m_gtx_n_i]
create_clock -period 8.000 -name clk_125m_gtx_p_i -waveform {0.000 4.000} [get_ports clk_125m_gtx_p_i]
#create_clock -period 8.000 -name clk_125m_gtx_n_i -waveform {0.000 4.000} [get_ports clk_125m_gtx_n_i] # AR57109: "Only P side needs constraint"
create_clock -period 16.000 -name RXOUTCLK -waveform {0.000 8.000} [get_pins cmp_xwrc_board_clbv4/cmp_
xwrc_platform/gen_phy_kintex7.cmp_gtx
/U_GTX_INST/gtxe2_i/RXOUTCLK]
create_clock -period 16.000 -name TXOUTCLK -waveform {0.000 8.000} [get_pins cmp_xwrc_board_clbv4/cmp_
xwrc_platform/gen_phy_kintex7.cmp_gtx
/U_GTX_INST/gtxe2_i/TXOUTCLK]
create_clock -period 16.000 -name RXOUTCLK -waveform {0.000 8.000} [get_pins cmp_xwrc_board_clbv4/cmp_
gtx_lp
/U_GTX_INST/gtxe2_i/RXOUTCLK]
create_clock -period 16.000 -name TXOUTCLK -waveform {0.000 8.000} [get_pins cmp_xwrc_board_clbv4/cmp_
gtx_lp
/U_GTX_INST/gtxe2_i/TXOUTCLK]
create_clock -period 100.000 -name dio_clk_p_i -waveform {0.000 50.000} [get_ports dio_clk_p_i]
set_clock_groups -asynchronous \
-group {clk_sys } \
-group {clk_dmtd } \
-group {clk_125m_dmtd_p_i } \
-group {clk_125m_gtx_p_i } \
...
...
@@ -234,7 +233,6 @@ set_property IOSTANDARD LVDS_25 [get_ports {dio_n_i[0]}]
# -- Differential outputs. When the I/O (N+1) is configured as output (i.e. when
# -- dio_oe_n_o(N) = 0), the value of dio_p_o(N) determines the logic state
# -- of I/O (N+1) on the front panel of the mezzanine
#LA04_P
set_property PACKAGE_PIN N18 [get_ports {dio_p_o[4]}]
set_property IOSTANDARD LVDS_25 [get_ports {dio_p_o[4]}]
...
...
@@ -311,7 +309,7 @@ set_property IOSTANDARD LVCMOS25 [get_ports dio_led_top_o]
set_property PACKAGE_PIN P21 [get_ports dio_led_bot_o]
set_property IOSTANDARD LVCMOS25 [get_ports dio_led_bot_o]
# -- I2C interface for accessing EEPROM
# -- I2C interface for accessing EEPROM
.
#Bank 14 VCCO - 3.3 V
set_property PACKAGE_PIN D24 [get_ports eeprom_scl_b]
set_property IOSTANDARD LVCMOS33 [get_ports eeprom_scl_b]
...
...
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