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White Rabbit core collection
Commit 5886ad1e authored by Peter Jansweijer's avatar Peter Jansweijer
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clbv2, clbv4 use low phase drift phy

parent 9d6045b8
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    board/clbv2/wr_clbv2_pkg.vhd
    View file @ 5886ad1e
    ......@@ -7,7 +7,7 @@
    -- Author(s) : Peter Jansweijer <peterj@nikhef.nl>
    -- Company : Nikhef
    -- Created : 2017-11-08
    -- Last update: 2017-11-08
    -- Last update: 2022-05-18
    -- Standard : VHDL'93
    -------------------------------------------------------------------------------
    -- Copyright (c) 2017 Nikhef
    ......@@ -63,8 +63,8 @@ package wr_clbv2_pkg is
    areset_n_i : in std_logic;
    areset_edge_n_i : in std_logic := '1';
    clk_20m_vcxo_i : in std_logic;
    clk_125m_gtp_n_i : in std_logic;
    clk_125m_gtp_p_i : in std_logic;
    clk_125m_gtx_n_i : in std_logic;
    clk_125m_gtx_p_i : in std_logic;
    clk_aux_i : in std_logic_vector(g_aux_clks-1 downto 0) := (others => '0');
    clk_10m_ext_i : in std_logic := '0';
    pps_ext_i : in std_logic := '0';
    ......@@ -158,8 +158,8 @@ package wr_clbv2_pkg is
    areset_n_i : in std_logic;
    areset_edge_n_i : in std_logic := '1';
    clk_20m_vcxo_i : in std_logic;
    clk_125m_gtp_n_i : in std_logic;
    clk_125m_gtp_p_i : in std_logic;
    clk_125m_gtx_n_i : in std_logic;
    clk_125m_gtx_p_i : in std_logic;
    clk_10m_ext_i : in std_logic := '0';
    pps_ext_i : in std_logic := '0';
    clk_sys_62m5_o : out std_logic;
    ......
    board/clbv2/wrc_board_clbv2.vhd
    View file @ 5886ad1e
    ......@@ -7,7 +7,7 @@
    -- Author(s) : Peter Jansweijer <peterj@nikhef.nl>
    -- Company : Nikhef
    -- Created : 2017-11-08
    -- Last update: 2017-11-08
    -- Last update: 2022-05-18
    -- Standard : VHDL'93
    -------------------------------------------------------------------------------
    -- Description: Top-level wrapper for WR PTP core including all the modules
    ......@@ -88,8 +88,8 @@ entity wrc_board_clbv2 is
    areset_edge_n_i : in std_logic := '1';
    -- Clock inputs from the board
    clk_20m_vcxo_i : in std_logic;
    clk_125m_gtp_n_i : in std_logic;
    clk_125m_gtp_p_i : in std_logic;
    clk_125m_gtx_n_i : in std_logic;
    clk_125m_gtx_p_i : in std_logic;
    -- 10MHz ext ref clock input (g_with_external_clock_input = TRUE)
    clk_10m_ext_i : in std_logic := '0';
    -- External PPS input (g_with_external_clock_input = TRUE)
    ......@@ -287,6 +287,10 @@ architecture std_wrapper of wrc_board_clbv2 is
    signal wrf_snk_out : t_wrf_sink_out;
    signal wrf_snk_in : t_wrf_sink_in;
    -- External WB interface
    -- Etherbone interface
    -- Aux diagnostics
    constant c_diag_ro_size : integer := g_diag_ro_vector_width/32;
    constant c_diag_rw_size : integer := g_diag_rw_vector_width/32;
    ......@@ -363,8 +367,8 @@ begin -- architecture struct
    areset_n_i => areset_n_i,
    areset_edge_n_i => areset_edge_n_i,
    clk_20m_vcxo_i => clk_20m_vcxo_i,
    clk_125m_gtp_n_i => clk_125m_gtp_n_i,
    clk_125m_gtp_p_i => clk_125m_gtp_p_i,
    clk_125m_gtx_n_i => clk_125m_gtx_n_i,
    clk_125m_gtx_p_i => clk_125m_gtx_p_i,
    clk_10m_ext_i => clk_10m_ext_i,
    pps_ext_i => pps_ext_i,
    clk_sys_62m5_o => clk_sys_62m5_o,
    ......
    board/clbv2/xwrc_board_clbv2.vhd
    View file @ 5886ad1e
    ......@@ -88,8 +88,8 @@ entity xwrc_board_clbv2 is
    areset_edge_n_i : in std_logic := '1';
    -- Clock inputs from the board
    clk_20m_vcxo_i : in std_logic;
    clk_125m_gtp_n_i : in std_logic;
    clk_125m_gtp_p_i : in std_logic;
    clk_125m_gtx_n_i : in std_logic;
    clk_125m_gtx_p_i : in std_logic;
    -- Aux clocks, which can be disciplined by the WR Core
    clk_aux_i : in std_logic_vector(g_aux_clks-1 downto 0) := (others => '0');
    -- 10MHz ext ref clock input (g_with_external_clock_input = TRUE)
    ......@@ -241,21 +241,29 @@ entity xwrc_board_clbv2 is
    end entity xwrc_board_clbv2;
    architecture struct of xwrc_board_clbv2 is
    -----------------------------------------------------------------------------
    -- Signals
    -----------------------------------------------------------------------------
    -- IBUFDS
    signal clk_125m_gtx_buf : std_logic;
    signal clk_125m_gtx_odiv2 : std_logic;
    signal clk_20m_vcxo_buf : std_logic;
    signal clk_dmtd : std_logic;
    -- PLLs, clocks
    signal clk_pll_62m5 : std_logic;
    signal clk_ref_62m5 : std_logic;
    signal clk_pll_dmtd : std_logic;
    signal pll_locked : std_logic;
    signal clk_10m_ext : std_logic;
    signal clk_sys_62m5 : std_logic;
    signal clk_ref_62m5 : std_logic;
    signal clk_dmtd_fb : std_logic;
    signal clk_dmtd_pll : std_logic;
    signal pll_locked : std_logic;
    signal clk_ref_locked : std_logic;
    signal clk_10m_ext : std_logic;
    -- Reset logic
    signal pll_arst : std_logic;
    signal areset_edge_ppulse : std_logic;
    signal rst_62m5_n : std_logic;
    signal rstlogic_arst_n : std_logic;
    ......@@ -263,10 +271,10 @@ architecture struct of xwrc_board_clbv2 is
    signal rstlogic_rst_out : std_logic_vector(1 downto 0);
    -- PLL DACs
    signal dac_hpll_load_p1 : std_logic;
    signal dac_hpll_data : std_logic_vector(15 downto 0);
    signal dac_dpll_load_p1 : std_logic;
    signal dac_dpll_data : std_logic_vector(15 downto 0);
    signal dac_dmtd_load : std_logic;
    signal dac_dmtd_data : std_logic_vector(15 downto 0);
    signal dac_refclk_load : std_logic;
    signal dac_refclk_data : std_logic_vector(15 downto 0);
    -- OneWire
    signal onewire_in : std_logic_vector(1 downto 0);
    ......@@ -288,40 +296,224 @@ begin -- architecture struct
    -- Platform-dependent part (PHY, PLLs, buffers, etc)
    -----------------------------------------------------------------------------
    cmp_xwrc_platform : xwrc_platform_xilinx
    generic map (
    g_fpga_family => "kintex7",
    g_with_external_clock_input => g_with_external_clock_input,
    g_use_default_plls => TRUE,
    g_simulation => g_simulation)
    -- active high async reset for PLLs
    pll_arst <= not areset_n_i;
    -- DMTD PLL input clock buffer
    cmp_clk_dmtd_buf_i : BUFG
    port map (
    areset_n_i => areset_n_i,
    clk_10m_ext_i => clk_10m_ext_i,
    clk_20m_vcxo_i => clk_20m_vcxo_i,
    clk_125m_gtp_p_i => clk_125m_gtp_p_i,
    clk_125m_gtp_n_i => clk_125m_gtp_n_i,
    sfp_txn_o => sfp_txn_o,
    sfp_txp_o => sfp_txp_o,
    sfp_rxn_i => sfp_rxn_i,
    sfp_rxp_i => sfp_rxp_i,
    sfp_tx_fault_i => sfp_tx_fault_i,
    sfp_los_i => sfp_los_i,
    sfp_tx_disable_o => sfp_tx_disable_o,
    clk_62m5_sys_o => clk_pll_62m5,
    clk_125m_ref_o => clk_ref_62m5, -- Note: This is a 62m5 Clock for 16 bit PHYs!
    clk_62m5_dmtd_o => clk_pll_dmtd,
    pll_locked_o => pll_locked,
    clk_10m_ext_o => clk_10m_ext,
    phy16_o => phy16_to_wrc,
    phy16_i => phy16_from_wrc,
    ext_ref_mul_o => ext_ref_mul,
    ext_ref_mul_locked_o => ext_ref_mul_locked,
    ext_ref_mul_stopped_o => ext_ref_mul_stopped,
    ext_ref_rst_i => ext_ref_rst);
    clk_sys_62m5_o <= clk_pll_62m5;
    O => clk_20m_vcxo_buf,
    I => clk_20m_vcxo_i);
    -- DMTD PLL (20 MHz -> ~62,5 MHz)
    cmp_dmtd_clk_pll : MMCME2_ADV
    generic map (
    BANDWIDTH => "OPTIMIZED",
    CLKOUT4_CASCADE => false,
    COMPENSATION => "ZHOLD",
    STARTUP_WAIT => false,
    DIVCLK_DIVIDE => 1,
    CLKFBOUT_MULT_F => 50.000, -- 20 MHz -> 1 GHz
    CLKFBOUT_PHASE => 0.000,
    CLKFBOUT_USE_FINE_PS => false,
    CLKOUT0_DIVIDE_F => 16.000, -- 1GHz/16 -> 62.5 MHz
    CLKOUT0_PHASE => 0.000,
    CLKOUT0_DUTY_CYCLE => 0.500,
    CLKOUT0_USE_FINE_PS => false,
    CLKOUT1_DIVIDE => 16, -- 1GHz/16 -> 62.5 MHz
    CLKOUT1_PHASE => 0.000,
    CLKOUT1_DUTY_CYCLE => 0.500,
    CLKOUT1_USE_FINE_PS => false,
    CLKIN1_PERIOD => 50.000, -- 50ns for 20 MHz
    REF_JITTER1 => 0.010)
    port map (
    -- Output clocks
    CLKFBOUT => clk_dmtd_fb,
    CLKOUT0 => clk_dmtd_pll,
    -- Input clock control
    CLKFBIN => clk_dmtd_fb,
    CLKIN1 => clk_20m_vcxo_buf,
    CLKIN2 => '0',
    -- Tied to always select the primary input clock
    CLKINSEL => '1',
    -- Ports for dynamic reconfiguration
    DADDR => (others => '0'),
    DCLK => '0',
    DEN => '0',
    DI => (others => '0'),
    DO => open,
    DRDY => open,
    DWE => '0',
    -- Ports for dynamic phase shift
    PSCLK => '0',
    PSEN => '0',
    PSINCDEC => '0',
    PSDONE => open,
    -- Other control and status signals
    LOCKED => pll_locked,
    CLKINSTOPPED => open,
    CLKFBSTOPPED => open,
    PWRDWN => '0',
    RST => pll_arst);
    -- DMTD PLL output clock buffer
    cmp_clk_dmtd_buf_o : BUFG
    port map (
    O => clk_dmtd,
    I => clk_dmtd_pll);
    -----------------------------------------------------------------------------
    -- Dedicated GTX clock.
    -----------------------------------------------------------------------------
    cmp_gtx_dedicated_clk : IBUFDS_GTE2
    generic map(
    CLKCM_CFG => true,
    CLKRCV_TRST => true,
    CLKSWING_CFG => "11")
    port map (
    O => clk_125m_gtx_buf,
    ODIV2 => clk_125m_gtx_odiv2,
    CEB => '0',
    I => clk_125m_gtx_p_i,
    IB => clk_125m_gtx_n_i);
    cmp_clk_ref62m5_buf : BUFG
    port map (
    O => clk_ref_62m5,
    I => clk_125m_gtx_odiv2);
    clk_sys_62m5 <= clk_ref_62m5;
    clk_sys_62m5_o <= clk_ref_62m5;
    clk_ref_62m5_o <= clk_ref_62m5;
    ---------------------------------------------------------------------------
    -- Kintex7 low phase drift PHY
    ---------------------------------------------------------------------------
    cmp_gtx_lp: wr_gtx_phy_family7_lp
    generic map(
    g_simulation => g_simulation)
    port map(
    clk_gtx_i => clk_125m_gtx_buf,
    clk_dmtd_i => clk_dmtd,
    clk_ref_i => clk_ref_62m5,
    tx_data_i => phy16_from_wrc.tx_data,
    tx_k_i => phy16_from_wrc.tx_k,
    tx_disparity_o => phy16_to_wrc.tx_disparity,
    tx_enc_err_o => phy16_to_wrc.tx_enc_err,
    rx_rbclk_o => phy16_to_wrc.rx_clk,
    clk_sampled_o => phy16_to_wrc.rx_sampled_clk,
    rx_data_o => phy16_to_wrc.rx_data,
    rx_k_o => phy16_to_wrc.rx_k,
    rx_enc_err_o => phy16_to_wrc.rx_enc_err,
    rx_bitslide_o => phy16_to_wrc.rx_bitslide,
    rst_i => phy16_from_wrc.rst,
    lpc_ctrl_i => phy16_from_wrc.lpc_ctrl,
    lpc_stat_o => phy16_to_wrc.lpc_stat,
    loopen_i => phy16_from_wrc.loopen,
    tx_prbs_sel_i => phy16_from_wrc.tx_prbs_sel,
    rdy_o => phy16_to_wrc.rdy,
    pad_txn_o => sfp_txn_o,
    pad_txp_o => sfp_txp_o,
    pad_rxn_i => sfp_rxn_i,
    pad_rxp_i => sfp_rxp_i,
    tx_locked_o => clk_ref_locked
    );
    phy16_to_wrc.ref_clk <= clk_ref_62m5;
    phy16_to_wrc.sfp_tx_fault <= sfp_tx_fault_i;
    phy16_to_wrc.sfp_los <= sfp_los_i;
    sfp_tx_disable_o <= phy16_from_wrc.sfp_tx_disable;
    ---------------------------------------------------------------------------
    -- External 10MHz reference PLL for Kintex7
    ---------------------------------------------------------------------------
    gen_ext_ref_pll : if (g_with_external_clock_input = TRUE) generate
    signal clk_ext_fbi : std_logic;
    signal clk_ext_fbo : std_logic;
    signal clk_ext_mul : std_logic;
    signal pll_ext_rst : std_logic;
    begin
    mmcm_adv_inst : MMCME2_ADV
    generic map (
    BANDWIDTH => "OPTIMIZED",
    CLKOUT4_CASCADE => FALSE,
    COMPENSATION => "ZHOLD",
    STARTUP_WAIT => FALSE,
    DIVCLK_DIVIDE => 1,
    CLKFBOUT_MULT_F => 62.500,
    CLKFBOUT_PHASE => 0.000,
    CLKFBOUT_USE_FINE_PS => FALSE,
    CLKOUT0_DIVIDE_F => 10.000,
    CLKOUT0_PHASE => 0.000,
    CLKOUT0_DUTY_CYCLE => 0.500,
    CLKOUT0_USE_FINE_PS => FALSE,
    CLKIN1_PERIOD => 100.000,
    REF_JITTER1 => 0.005)
    port map (
    -- Output clocks
    CLKFBOUT => clk_ext_fbo,
    CLKOUT0 => clk_ext_mul,
    -- Input clock control
    CLKFBIN => clk_ext_fbi,
    CLKIN1 => clk_10m_ext,
    CLKIN2 => '0',
    -- Tied to always select the primary input clock
    CLKINSEL => '1',
    -- Ports for dynamic reconfiguration
    DADDR => (others => '0'),
    DCLK => '0',
    DEN => '0',
    DI => (others => '0'),
    DO => open,
    DRDY => open,
    DWE => '0',
    -- Ports for dynamic phase shift
    PSCLK => '0',
    PSEN => '0',
    PSINCDEC => '0',
    PSDONE => open, -- Other control and status signals
    LOCKED => ext_ref_mul_locked,
    CLKINSTOPPED => ext_ref_mul_stopped,
    CLKFBSTOPPED => open,
    PWRDWN => '0',
    RST => pll_ext_rst);
    -- External reference input buffer
    cmp_clk_ext_buf_i : BUFG
    port map (
    O => clk_10m_ext,
    I => clk_10m_ext_i);
    -- External reference feedback buffer
    cmp_clk_ext_buf_fb : BUFG
    port map (
    O => clk_ext_fbi,
    I => clk_ext_fbo);
    -- External reference output buffer
    cmp_clk_ext_buf_o : BUFG
    port map (
    O => ext_ref_mul,
    I => clk_ext_mul);
    cmp_extend_ext_reset : gc_extend_pulse
    generic map (
    g_width => 1000)
    port map (
    clk_i => clk_sys_62m5,
    rst_n_i => '1',
    pulse_i => ext_ref_rst,
    extended_o => pll_ext_rst);
    end generate gen_ext_ref_pll;
    -----------------------------------------------------------------------------
    -- Reset logic
    -----------------------------------------------------------------------------
    ......@@ -333,7 +525,7 @@ begin -- architecture struct
    generic map (
    g_sync_edge => "positive")
    port map (
    clk_i => clk_pll_62m5,
    clk_i => clk_sys_62m5,
    rst_n_i => '1',
    data_i => areset_edge_n_i,
    ppulse_o => areset_edge_ppulse);
    ......@@ -342,7 +534,7 @@ begin -- architecture struct
    rstlogic_arst_n <= pll_locked and areset_n_i and (not areset_edge_ppulse);
    -- concatenation of all clocks required to have synced resets
    rstlogic_clk_in(0) <= clk_pll_62m5;
    rstlogic_clk_in(0) <= clk_sys_62m5;
    rstlogic_clk_in(1) <= clk_ref_62m5;
    cmp_rstlogic_reset : gc_reset
    ......@@ -371,12 +563,12 @@ begin -- architecture struct
    g_invert_sclk => FALSE,
    g_num_extra_bits => 8)
    port map (
    clk_i => clk_pll_62m5,
    clk_i => clk_sys_62m5,
    rst_n_i => rst_62m5_n,
    val1_i => dac_dpll_data,
    load1_i => dac_dpll_load_p1,
    val2_i => dac_hpll_data,
    load2_i => dac_hpll_load_p1,
    val1_i => dac_refclk_data,
    load1_i => dac_refclk_load,
    val2_i => dac_dmtd_data,
    load2_i => dac_dmtd_load,
    dac_cs_n_o(0) => pll25dac_cs_n_o,
    dac_cs_n_o(1) => pll20dac_cs_n_o,
    dac_sclk_o => plldac_sclk_o,
    ......@@ -390,6 +582,7 @@ begin -- architecture struct
    generic map (
    g_simulation => g_simulation,
    g_with_external_clock_input => g_with_external_clock_input,
    g_ram_address_space_size_kb => 256,
    g_board_name => "CLB2",
    g_phys_uart => TRUE,
    g_virtual_uart => TRUE,
    ......@@ -402,6 +595,7 @@ begin -- architecture struct
    g_address_granularity => BYTE,
    g_aux_sdb => c_wrc_periph3_sdb,
    g_softpll_enable_debugger => FALSE,
    g_softpll_use_sampled_ref_clocks => TRUE,
    g_vuart_fifo_size => 1024,
    g_pcs_16bit => TRUE,
    g_diag_id => g_diag_id,
    ......@@ -414,8 +608,8 @@ begin -- architecture struct
    g_fabric_iface => g_fabric_iface
    )
    port map (
    clk_sys_i => clk_pll_62m5,
    clk_dmtd_i => clk_pll_dmtd,
    clk_sys_i => clk_sys_62m5,
    clk_dmtd_i => clk_dmtd,
    clk_ref_i => clk_ref_62m5,
    clk_aux_i => clk_aux_i,
    clk_10m_ext_i => clk_10m_ext,
    ......@@ -425,10 +619,10 @@ begin -- architecture struct
    clk_ext_rst_o => ext_ref_rst,
    pps_ext_i => pps_ext_i,
    rst_n_i => rst_62m5_n,
    dac_hpll_load_p1_o => dac_hpll_load_p1,
    dac_hpll_data_o => dac_hpll_data,
    dac_dpll_load_p1_o => dac_dpll_load_p1,
    dac_dpll_data_o => dac_dpll_data,
    dac_hpll_load_p1_o => dac_dmtd_load,
    dac_hpll_data_o => dac_dmtd_data,
    dac_dpll_load_p1_o => dac_refclk_load,
    dac_dpll_data_o => dac_refclk_data,
    phy16_o => phy16_from_wrc,
    phy16_i => phy16_to_wrc,
    scl_o => eeprom_scl_o,
    ......
    board/clbv4/wr_clbv4_pkg.vhd
    View file @ 5886ad1e
    ......@@ -7,7 +7,7 @@
    -- Author(s) : Pascal Bos
    -- Company : Nikhef
    -- Created : 2019-06-18
    -- Last update: 2019-06-18
    -- Last update: 202-05-18
    -- Standard : VHDL'93
    -------------------------------------------------------------------------------
    -- Copyright (c) 2017 Nikhef
    ......@@ -159,152 +159,152 @@ package wr_CLBv4_pkg is
    g_diag_ro_vector_width : integer := 0;
    g_diag_rw_vector_width : integer := 0);
    port (
    areset_n_i : in std_logic;
    areset_edge_n_i : in std_logic := '1';
    clk_125m_dmtd_n_i : in std_logic;
    clk_125m_dmtd_p_i : in std_logic;
    clk_125m_gtp_n_i : in std_logic;
    clk_125m_gtp_p_i : in std_logic;
    clk_10m_ext_i : in std_logic := '0';
    pps_ext_i : in std_logic := '0';
    clk_sys_62m5_o : out std_logic;
    clk_ref_62m5_o : out std_logic;
    rst_sys_62m5_n_o : out std_logic;
    rst_ref_62m5_n_o : out std_logic;
    dac_refclk_cs_n_o : out std_logic;
    dac_refclk_sclk_o : out std_logic;
    dac_refclk_din_o : out std_logic;
    dac_dmtd_cs_n_o : out std_logic;
    dac_dmtd_sclk_o : out std_logic;
    dac_dmtd_din_o : out std_logic;
    sfp_txp_o : out std_logic;
    sfp_txn_o : out std_logic;
    sfp_rxp_i : in std_logic;
    sfp_rxn_i : in std_logic;
    sfp_det_i : in std_logic := '1';
    sfp_sda_i : in std_logic;
    sfp_sda_o : out std_logic;
    sfp_scl_i : in std_logic;
    sfp_scl_o : out std_logic;
    sfp_rate_select_o : out std_logic;
    sfp_tx_fault_i : in std_logic := '0';
    sfp_tx_disable_o : out std_logic;
    sfp_los_i : in std_logic := '0';
    eeprom_sda_i : in std_logic;
    eeprom_sda_o : out std_logic;
    eeprom_scl_i : in std_logic;
    eeprom_scl_o : out std_logic;
    onewire_i : in std_logic;
    onewire_oen_o : out std_logic;
    uart_rxd_i : in std_logic;
    uart_txd_o : out std_logic;
    areset_n_i : in std_logic;
    areset_edge_n_i : in std_logic := '1';
    clk_125m_dmtd_n_i : in std_logic;
    clk_125m_dmtd_p_i : in std_logic;
    clk_125m_gtx_n_i : in std_logic;
    clk_125m_gtx_p_i : in std_logic;
    clk_10m_ext_i : in std_logic := '0';
    pps_ext_i : in std_logic := '0';
    clk_sys_62m5_o : out std_logic;
    clk_ref_62m5_o : out std_logic;
    rst_sys_62m5_n_o : out std_logic;
    rst_ref_62m5_n_o : out std_logic;
    dac_refclk_cs_n_o : out std_logic;
    dac_refclk_sclk_o : out std_logic;
    dac_refclk_din_o : out std_logic;
    dac_dmtd_cs_n_o : out std_logic;
    dac_dmtd_sclk_o : out std_logic;
    dac_dmtd_din_o : out std_logic;
    sfp_txp_o : out std_logic;
    sfp_txn_o : out std_logic;
    sfp_rxp_i : in std_logic;
    sfp_rxn_i : in std_logic;
    sfp_det_i : in std_logic := '1';
    sfp_sda_i : in std_logic;
    sfp_sda_o : out std_logic;
    sfp_scl_i : in std_logic;
    sfp_scl_o : out std_logic;
    sfp_rate_select_o : out std_logic;
    sfp_tx_fault_i : in std_logic := '0';
    sfp_tx_disable_o : out std_logic;
    sfp_los_i : in std_logic := '0';
    eeprom_sda_i : in std_logic;
    eeprom_sda_o : out std_logic;
    eeprom_scl_i : in std_logic;
    eeprom_scl_o : out std_logic;
    onewire_i : in std_logic;
    onewire_oen_o : out std_logic;
    uart_rxd_i : in std_logic;
    uart_txd_o : out std_logic;
    flash_sclk_o : out std_logic;
    flash_ncs_o : out std_logic;
    flash_mosi_o : out std_logic;
    flash_miso_i : in std_logic;
    wb_adr_i : in std_logic_vector(c_wishbone_address_width-1 downto 0) := (others => '0');
    wb_dat_i : in std_logic_vector(c_wishbone_data_width-1 downto 0) := (others => '0');
    wb_dat_o : out std_logic_vector(c_wishbone_data_width-1 downto 0);
    wb_sel_i : in std_logic_vector(c_wishbone_address_width/8-1 downto 0) := (others => '0');
    wb_we_i : in std_logic := '0';
    wb_cyc_i : in std_logic := '0';
    wb_stb_i : in std_logic := '0';
    wb_ack_o : out std_logic;
    wb_int_o : out std_logic;
    wb_err_o : out std_logic;
    wb_rty_o : out std_logic;
    wb_stall_o : out std_logic;
    aux_master_adr_o : out std_logic_vector(c_wishbone_address_width-1 downto 0);
    aux_master_dat_o : out std_logic_vector(c_wishbone_data_width-1 downto 0);
    aux_master_dat_i : in std_logic_vector(c_wishbone_data_width-1 downto 0) := (others => '0');
    aux_master_sel_o : out std_logic_vector(c_wishbone_address_width/8-1 downto 0);
    aux_master_we_o : out std_logic;
    aux_master_cyc_o : out std_logic;
    aux_master_stb_o : out std_logic;
    aux_master_ack_i : in std_logic := '0';
    aux_master_int_i : in std_logic := '0';
    aux_master_err_i : in std_logic := '0';
    aux_master_rty_i : in std_logic := '0';
    aux_master_stall_i : in std_logic := '0';
    wrf_src_adr_o : out std_logic_vector(1 downto 0);
    wrf_src_dat_o : out std_logic_vector(15 downto 0);
    wrf_src_cyc_o : out std_logic;
    wrf_src_stb_o : out std_logic;
    wrf_src_we_o : out std_logic;
    wrf_src_sel_o : out std_logic_vector(1 downto 0);
    wrf_src_ack_i : in std_logic;
    wrf_src_stall_i : in std_logic;
    wrf_src_err_i : in std_logic;
    wrf_src_rty_i : in std_logic;
    wrf_snk_adr_i : in std_logic_vector(1 downto 0);
    wrf_snk_dat_i : in std_logic_vector(15 downto 0);
    wrf_snk_cyc_i : in std_logic;
    wrf_snk_stb_i : in std_logic;
    wrf_snk_we_i : in std_logic;
    wrf_snk_sel_i : in std_logic_vector(1 downto 0);
    wrf_snk_ack_o : out std_logic;
    wrf_snk_stall_o : out std_logic;
    wrf_snk_err_o : out std_logic;
    wrf_snk_rty_o : out std_logic;
    wrs_tx_data_i : in std_logic_vector(g_tx_streamer_params.data_width-1 downto 0) := (others => '0');
    wrs_tx_valid_i : in std_logic := '0';
    wrs_tx_dreq_o : out std_logic;
    wrs_tx_last_i : in std_logic := '1';
    wrs_tx_flush_i : in std_logic := '0';
    wrs_tx_cfg_mac_l_i : in std_logic_vector(47 downto 0) := x"000000000000";
    wrs_tx_cfg_mac_t_i : in std_logic_vector(47 downto 0) := x"ffffffffffff";
    wrs_tx_cfg_etype_i : in std_logic_vector(15 downto 0) := x"dbff";
    wrs_rx_first_o : out std_logic;
    wrs_rx_last_o : out std_logic;
    wrs_rx_data_o : out std_logic_vector(g_rx_streamer_params.data_width-1 downto 0);
    wrs_rx_valid_o : out std_logic;
    wrs_rx_dreq_i : in std_logic := '0';
    wrs_rx_cfg_mac_l_i : in std_logic_vector(47 downto 0) := x"000000000000";
    wrs_rx_cfg_mac_r_i : in std_logic_vector(47 downto 0) := x"000000000000";
    wrs_rx_cfg_etype_i : in std_logic_vector(15 downto 0) := x"dbff";
    wrs_rx_cfg_acc_b_i : in std_logic := '1';
    wrs_rx_cfg_flt_r_i : in std_logic := '0';
    wrs_rx_cfg_fix_l_i : in std_logic_vector(27 downto 0) := x"0000000";
    wb_eth_adr_o : out std_logic_vector(c_wishbone_address_width-1 downto 0);
    wb_eth_dat_o : out std_logic_vector(c_wishbone_data_width-1 downto 0);
    wb_eth_dat_i : in std_logic_vector(c_wishbone_data_width-1 downto 0) := (others => '0');
    wb_eth_sel_o : out std_logic_vector(c_wishbone_address_width/8-1 downto 0);
    wb_eth_we_o : out std_logic;
    wb_eth_cyc_o : out std_logic;
    wb_eth_stb_o : out std_logic;
    wb_eth_ack_i : in std_logic := '0';
    wb_eth_int_i : in std_logic := '0';
    wb_eth_err_i : in std_logic := '0';
    wb_eth_rty_i : in std_logic := '0';
    wb_eth_stall_i : in std_logic := '0';
    aux_diag_i : in std_logic_vector(g_diag_ro_vector_width - 1 downto 0) := (others => '0');
    aux_diag_o : out std_logic_vector(g_diag_rw_vector_width - 1 downto 0) := (others => '0');
    wb_adr_i : in std_logic_vector(c_wishbone_address_width-1 downto 0) := (others => '0');
    wb_dat_i : in std_logic_vector(c_wishbone_data_width-1 downto 0) := (others => '0');
    wb_dat_o : out std_logic_vector(c_wishbone_data_width-1 downto 0);
    wb_sel_i : in std_logic_vector(c_wishbone_address_width/8-1 downto 0) := (others => '0');
    wb_we_i : in std_logic := '0';
    wb_cyc_i : in std_logic := '0';
    wb_stb_i : in std_logic := '0';
    wb_ack_o : out std_logic;
    wb_int_o : out std_logic;
    wb_err_o : out std_logic;
    wb_rty_o : out std_logic;
    wb_stall_o : out std_logic;
    aux_master_adr_o : out std_logic_vector(c_wishbone_address_width-1 downto 0);
    aux_master_dat_o : out std_logic_vector(c_wishbone_data_width-1 downto 0);
    aux_master_dat_i : in std_logic_vector(c_wishbone_data_width-1 downto 0) := (others => '0');
    aux_master_sel_o : out std_logic_vector(c_wishbone_address_width/8-1 downto 0);
    aux_master_we_o : out std_logic;
    aux_master_cyc_o : out std_logic;
    aux_master_stb_o : out std_logic;
    aux_master_ack_i : in std_logic := '0';
    aux_master_int_i : in std_logic := '0';
    aux_master_err_i : in std_logic := '0';
    aux_master_rty_i : in std_logic := '0';
    aux_master_stall_i : in std_logic := '0';
    wrf_src_adr_o : out std_logic_vector(1 downto 0);
    wrf_src_dat_o : out std_logic_vector(15 downto 0);
    wrf_src_cyc_o : out std_logic;
    wrf_src_stb_o : out std_logic;
    wrf_src_we_o : out std_logic;
    wrf_src_sel_o : out std_logic_vector(1 downto 0);
    wrf_src_ack_i : in std_logic;
    wrf_src_stall_i : in std_logic;
    wrf_src_err_i : in std_logic;
    wrf_src_rty_i : in std_logic;
    wrf_snk_adr_i : in std_logic_vector(1 downto 0);
    wrf_snk_dat_i : in std_logic_vector(15 downto 0);
    wrf_snk_cyc_i : in std_logic;
    wrf_snk_stb_i : in std_logic;
    wrf_snk_we_i : in std_logic;
    wrf_snk_sel_i : in std_logic_vector(1 downto 0);
    wrf_snk_ack_o : out std_logic;
    wrf_snk_stall_o : out std_logic;
    wrf_snk_err_o : out std_logic;
    wrf_snk_rty_o : out std_logic;
    wrs_tx_data_i : in std_logic_vector(g_tx_streamer_params.data_width-1 downto 0) := (others => '0');
    wrs_tx_valid_i : in std_logic := '0';
    wrs_tx_dreq_o : out std_logic;
    wrs_tx_last_i : in std_logic := '1';
    wrs_tx_flush_i : in std_logic := '0';
    wrs_tx_cfg_mac_l_i : in std_logic_vector(47 downto 0) := x"000000000000";
    wrs_tx_cfg_mac_t_i : in std_logic_vector(47 downto 0) := x"ffffffffffff";
    wrs_tx_cfg_etype_i : in std_logic_vector(15 downto 0) := x"dbff";
    wrs_rx_first_o : out std_logic;
    wrs_rx_last_o : out std_logic;
    wrs_rx_data_o : out std_logic_vector(g_rx_streamer_params.data_width-1 downto 0);
    wrs_rx_valid_o : out std_logic;
    wrs_rx_dreq_i : in std_logic := '0';
    wrs_rx_cfg_mac_l_i : in std_logic_vector(47 downto 0) := x"000000000000";
    wrs_rx_cfg_mac_r_i : in std_logic_vector(47 downto 0) := x"000000000000";
    wrs_rx_cfg_etype_i : in std_logic_vector(15 downto 0) := x"dbff";
    wrs_rx_cfg_acc_b_i : in std_logic := '1';
    wrs_rx_cfg_flt_r_i : in std_logic := '0';
    wrs_rx_cfg_fix_l_i : in std_logic_vector(27 downto 0) := x"0000000";
    wb_eth_adr_o : out std_logic_vector(c_wishbone_address_width-1 downto 0);
    wb_eth_dat_o : out std_logic_vector(c_wishbone_data_width-1 downto 0);
    wb_eth_dat_i : in std_logic_vector(c_wishbone_data_width-1 downto 0) := (others => '0');
    wb_eth_sel_o : out std_logic_vector(c_wishbone_address_width/8-1 downto 0);
    wb_eth_we_o : out std_logic;
    wb_eth_cyc_o : out std_logic;
    wb_eth_stb_o : out std_logic;
    wb_eth_ack_i : in std_logic := '0';
    wb_eth_int_i : in std_logic := '0';
    wb_eth_err_i : in std_logic := '0';
    wb_eth_rty_i : in std_logic := '0';
    wb_eth_stall_i : in std_logic := '0';
    aux_diag_i : in std_logic_vector(g_diag_ro_vector_width - 1 downto 0) := (others => '0');
    aux_diag_o : out std_logic_vector(g_diag_rw_vector_width - 1 downto 0) := (others => '0');
    tm_dac_value_o : out std_logic_vector(31 downto 0);
    tm_dac_wr_o : out std_logic_vector(g_aux_clks-1 downto 0);
    tm_clk_aux_lock_en_i : in std_logic_vector(g_aux_clks-1 downto 0) := (others => '0');
    tm_clk_aux_locked_o : out std_logic_vector(g_aux_clks-1 downto 0);
    tstamps_stb_o : out std_logic;
    tstamps_tsval_o : out std_logic_vector(31 downto 0);
    tstamps_port_id_o : out std_logic_vector(5 downto 0);
    tstamps_frame_id_o : out std_logic_vector(15 downto 0);
    tstamps_incorrect_o : out std_logic;
    tstamps_ack_i : in std_logic := '1';
    abscal_txts_o : out std_logic;
    abscal_rxts_o : out std_logic;
    fc_tx_pause_req_i : in std_logic := '0';
    fc_tx_pause_delay_i : in std_logic_vector(15 downto 0) := x"0000";
    fc_tx_pause_ready_o : out std_logic;
    tm_link_up_o : out std_logic;
    tm_time_valid_o : out std_logic;
    tm_tai_o : out std_logic_vector(39 downto 0);
    tm_cycles_o : out std_logic_vector(27 downto 0);
    led_act_o : out std_logic;
    led_link_o : out std_logic;
    btn1_i : in std_logic := '1';
    btn2_i : in std_logic := '1';
    pps_p_o : out std_logic;
    pps_led_o : out std_logic;
    link_ok_o : out std_logic);
    tstamps_stb_o : out std_logic;
    tstamps_tsval_o : out std_logic_vector(31 downto 0);
    tstamps_port_id_o : out std_logic_vector(5 downto 0);
    tstamps_frame_id_o : out std_logic_vector(15 downto 0);
    tstamps_incorrect_o : out std_logic;
    tstamps_ack_i : in std_logic := '1';
    abscal_txts_o : out std_logic;
    abscal_rxts_o : out std_logic;
    fc_tx_pause_req_i : in std_logic := '0';
    fc_tx_pause_delay_i : in std_logic_vector(15 downto 0) := x"0000";
    fc_tx_pause_ready_o : out std_logic;
    tm_link_up_o : out std_logic;
    tm_time_valid_o : out std_logic;
    tm_tai_o : out std_logic_vector(39 downto 0);
    tm_cycles_o : out std_logic_vector(27 downto 0);
    led_act_o : out std_logic;
    led_link_o : out std_logic;
    btn1_i : in std_logic := '1';
    btn2_i : in std_logic := '1';
    pps_p_o : out std_logic;
    pps_led_o : out std_logic;
    link_ok_o : out std_logic);
    end component wrc_board_clbv4;
    end wr_clbv4_pkg;
    board/clbv4/wrc_board_clbv4.vhd
    View file @ 5886ad1e
    ......@@ -7,7 +7,7 @@
    -- Author(s) : Pascal Bos <bosp@nikhef.nl>
    -- Company : Nikhef
    -- Created : 2019-05-22
    -- Last update: 2019-05-22
    -- Last update: 2022-05-18
    -- Standard : VHDL'93
    -------------------------------------------------------------------------------
    -- Description: Top-level wrapper for WR PTP core including all the modules
    ......@@ -87,10 +87,10 @@ entity wrc_board_clbv4 is
    -- reset PLLs.
    areset_edge_n_i : in std_logic := '1';
    -- Clock inputs from the board
    clk_125m_dmtd_p_i : in std_logic;
    clk_125m_dmtd_n_i : in std_logic;
    clk_125m_gtp_n_i : in std_logic;
    clk_125m_gtp_p_i : in std_logic;
    clk_125m_dmtd_p_i : in std_logic;
    clk_125m_dmtd_n_i : in std_logic;
    clk_125m_gtx_n_i : in std_logic;
    clk_125m_gtx_p_i : in std_logic;
    -- 10MHz ext ref clock input (g_with_external_clock_input = TRUE)
    clk_10m_ext_i : in std_logic := '0';
    -- External PPS input (g_with_external_clock_input = TRUE)
    ......
    board/clbv4/xwrc_board_clbv4.vhd
    View file @ 5886ad1e
    ......@@ -247,7 +247,6 @@ entity xwrc_board_clbv4 is
    end entity xwrc_board_clbv4;
    architecture struct of xwrc_board_clbv4 is
    -----------------------------------------------------------------------------
    ......@@ -255,35 +254,38 @@ architecture struct of xwrc_board_clbv4 is
    -----------------------------------------------------------------------------
    -- IBUFDS
    signal clk_125m_dmtd_buf : std_logic;
    signal clk_dmtd : std_logic;
    signal clk_125m_gtx_buf : std_logic;
    signal clk_125m_gtx_odiv2 : std_logic;
    signal clk_125m_dmtd_buf : std_logic;
    signal clk_dmtd_buf : std_logic;
    signal clk_dmtd : std_logic;
    -- PLLs, clocks
    signal clk_pll_62m5 : std_logic;
    signal clk_ref_62m5 : std_logic;
    signal pll_locked : std_logic;
    signal clk_10m_ext : std_logic;
    signal clk_sys_62m5 : std_logic;
    signal clk_ref_62m5 : std_logic;
    signal clk_ref_locked : std_logic;
    signal clk_10m_ext : std_logic;
    -- Reset logic
    signal areset_edge_ppulse : std_logic;
    signal rst_62m5_n : std_logic;
    signal rstlogic_arst_n : std_logic;
    signal rstlogic_clk_in : std_logic_vector(1 downto 0);
    signal rstlogic_rst_out : std_logic_vector(1 downto 0);
    signal areset_edge_ppulse : std_logic;
    signal rst_62m5_n : std_logic;
    signal rstlogic_arst_n : std_logic;
    signal rstlogic_clk_in : std_logic_vector(1 downto 0);
    signal rstlogic_rst_out : std_logic_vector(1 downto 0);
    -- PLL DACs
    signal dac_dmtd_load : std_logic;
    signal dac_dmtd_data : std_logic_vector(15 downto 0);
    signal dac_refclk_load : std_logic;
    signal dac_refclk_data : std_logic_vector(15 downto 0);
    signal dac_dmtd_load : std_logic;
    signal dac_dmtd_data : std_logic_vector(15 downto 0);
    signal dac_refclk_load : std_logic;
    signal dac_refclk_data : std_logic_vector(15 downto 0);
    -- OneWire
    signal onewire_in : std_logic_vector(1 downto 0);
    signal onewire_en : std_logic_vector(1 downto 0);
    signal onewire_in : std_logic_vector(1 downto 0);
    signal onewire_en : std_logic_vector(1 downto 0);
    -- PHY
    signal phy16_to_wrc : t_phy_16bits_to_wrc;
    signal phy16_from_wrc : t_phy_16bits_from_wrc;
    signal phy16_to_wrc : t_phy_16bits_to_wrc;
    signal phy16_from_wrc : t_phy_16bits_from_wrc;
    -- External reference
    signal ext_ref_mul : std_logic;
    ......@@ -305,43 +307,174 @@ begin -- architecture struct
    I => clk_125m_dmtd_p_i,
    IB => clk_125m_dmtd_n_i);
    -- DMTD Div2 (124.9920 MHz -> 62,496 MHz)
    process(clk_125m_dmtd_buf)
    begin
    if rising_edge(clk_125m_dmtd_buf) then
    clk_dmtd_buf <= not clk_dmtd_buf;
    end if;
    end process;
    -- DMTD clock buffer
    cmp_gtx_buf_i : BUFG
    port map (
    I => clk_dmtd_buf,
    O => clk_dmtd);
    clk_dmtd_62m5_o <= clk_dmtd;
    cmp_xwrc_platform : xwrc_platform_xilinx
    generic map (
    g_fpga_family => "kintex7",
    g_direct_dmtd => TRUE,
    g_with_external_clock_input => g_with_external_clock_input,
    g_use_default_plls => TRUE,
    g_simulation => g_simulation)
    -----------------------------------------------------------------------------
    -- Dedicated GTX clock.
    -----------------------------------------------------------------------------
    cmp_gtx_dedicated_clk : IBUFDS_GTE2
    generic map(
    CLKCM_CFG => true,
    CLKRCV_TRST => true,
    CLKSWING_CFG => "11")
    port map (
    areset_n_i => areset_n_i,
    clk_10m_ext_i => clk_10m_ext_i,
    clk_125m_dmtd_i => clk_125m_dmtd_buf,
    clk_125m_gtp_p_i => clk_125m_gtx_p_i, --Note clbv4 used GTX instead of GTPs
    clk_125m_gtp_n_i => clk_125m_gtx_n_i,
    sfp_txn_o => sfp_txn_o,
    sfp_txp_o => sfp_txp_o,
    sfp_rxn_i => sfp_rxn_i,
    sfp_rxp_i => sfp_rxp_i,
    sfp_tx_fault_i => sfp_tx_fault_i,
    sfp_los_i => sfp_los_i,
    sfp_tx_disable_o => sfp_tx_disable_o,
    clk_62m5_sys_o => clk_pll_62m5,
    clk_125m_ref_o => clk_ref_62m5, -- Note: This is a 62m5 Clock for 16 bit PHYs!
    clk_62m5_dmtd_o => clk_dmtd,
    pll_locked_o => pll_locked,
    clk_10m_ext_o => clk_10m_ext,
    phy16_o => phy16_to_wrc,
    phy16_i => phy16_from_wrc,
    ext_ref_mul_o => ext_ref_mul,
    ext_ref_mul_locked_o => ext_ref_mul_locked,
    ext_ref_mul_stopped_o => ext_ref_mul_stopped,
    ext_ref_rst_i => ext_ref_rst);
    clk_sys_62m5_o <= clk_pll_62m5;
    O => clk_125m_gtx_buf,
    ODIV2 => clk_125m_gtx_odiv2,
    CEB => '0',
    I => clk_125m_gtx_p_i,
    IB => clk_125m_gtx_n_i);
    cmp_clk_ref62m5_buf : BUFG
    port map (
    O => clk_ref_62m5,
    I => clk_125m_gtx_odiv2);
    clk_sys_62m5 <= clk_ref_62m5;
    clk_sys_62m5_o <= clk_ref_62m5;
    clk_ref_62m5_o <= clk_ref_62m5;
    ---------------------------------------------------------------------------
    -- Kintex7 low phase drift PHY
    ---------------------------------------------------------------------------
    cmp_gtx_lp: wr_gtx_phy_family7_lp
    generic map(
    g_simulation => g_simulation)
    port map(
    clk_gtx_i => clk_125m_gtx_buf,
    clk_dmtd_i => clk_dmtd,
    clk_ref_i => clk_ref_62m5,
    tx_data_i => phy16_from_wrc.tx_data,
    tx_k_i => phy16_from_wrc.tx_k,
    tx_disparity_o => phy16_to_wrc.tx_disparity,
    tx_enc_err_o => phy16_to_wrc.tx_enc_err,
    rx_rbclk_o => phy16_to_wrc.rx_clk,
    clk_sampled_o => phy16_to_wrc.rx_sampled_clk,
    rx_data_o => phy16_to_wrc.rx_data,
    rx_k_o => phy16_to_wrc.rx_k,
    rx_enc_err_o => phy16_to_wrc.rx_enc_err,
    rx_bitslide_o => phy16_to_wrc.rx_bitslide,
    rst_i => phy16_from_wrc.rst,
    lpc_ctrl_i => phy16_from_wrc.lpc_ctrl,
    lpc_stat_o => phy16_to_wrc.lpc_stat,
    loopen_i => phy16_from_wrc.loopen,
    tx_prbs_sel_i => phy16_from_wrc.tx_prbs_sel,
    rdy_o => phy16_to_wrc.rdy,
    pad_txn_o => sfp_txn_o,
    pad_txp_o => sfp_txp_o,
    pad_rxn_i => sfp_rxn_i,
    pad_rxp_i => sfp_rxp_i,
    tx_locked_o => clk_ref_locked
    );
    phy16_to_wrc.ref_clk <= clk_ref_62m5;
    phy16_to_wrc.sfp_tx_fault <= sfp_tx_fault_i;
    phy16_to_wrc.sfp_los <= sfp_los_i;
    sfp_tx_disable_o <= phy16_from_wrc.sfp_tx_disable;
    ---------------------------------------------------------------------------
    -- External 10MHz reference PLL for Kintex7
    ---------------------------------------------------------------------------
    gen_ext_ref_pll : if (g_with_external_clock_input = TRUE) generate
    signal clk_ext_fbi : std_logic;
    signal clk_ext_fbo : std_logic;
    signal clk_ext_mul : std_logic;
    signal pll_ext_rst : std_logic;
    begin
    mmcm_adv_inst : MMCME2_ADV
    generic map (
    BANDWIDTH => "OPTIMIZED",
    CLKOUT4_CASCADE => FALSE,
    COMPENSATION => "ZHOLD",
    STARTUP_WAIT => FALSE,
    DIVCLK_DIVIDE => 1,
    CLKFBOUT_MULT_F => 62.500,
    CLKFBOUT_PHASE => 0.000,
    CLKFBOUT_USE_FINE_PS => FALSE,
    CLKOUT0_DIVIDE_F => 10.000,
    CLKOUT0_PHASE => 0.000,
    CLKOUT0_DUTY_CYCLE => 0.500,
    CLKOUT0_USE_FINE_PS => FALSE,
    CLKIN1_PERIOD => 100.000,
    REF_JITTER1 => 0.005)
    port map (
    -- Output clocks
    CLKFBOUT => clk_ext_fbo,
    CLKOUT0 => clk_ext_mul,
    -- Input clock control
    CLKFBIN => clk_ext_fbi,
    CLKIN1 => clk_10m_ext,
    CLKIN2 => '0',
    -- Tied to always select the primary input clock
    CLKINSEL => '1',
    -- Ports for dynamic reconfiguration
    DADDR => (others => '0'),
    DCLK => '0',
    DEN => '0',
    DI => (others => '0'),
    DO => open,
    DRDY => open,
    DWE => '0',
    -- Ports for dynamic phase shift
    PSCLK => '0',
    PSEN => '0',
    PSINCDEC => '0',
    PSDONE => open, -- Other control and status signals
    LOCKED => ext_ref_mul_locked,
    CLKINSTOPPED => ext_ref_mul_stopped,
    CLKFBSTOPPED => open,
    PWRDWN => '0',
    RST => pll_ext_rst);
    -- External reference input buffer
    cmp_clk_ext_buf_i : BUFG
    port map (
    O => clk_10m_ext,
    I => clk_10m_ext_i);
    -- External reference feedback buffer
    cmp_clk_ext_buf_fb : BUFG
    port map (
    O => clk_ext_fbi,
    I => clk_ext_fbo);
    -- External reference output buffer
    cmp_clk_ext_buf_o : BUFG
    port map (
    O => ext_ref_mul,
    I => clk_ext_mul);
    cmp_extend_ext_reset : gc_extend_pulse
    generic map (
    g_width => 1000)
    port map (
    clk_i => clk_sys_62m5,
    rst_n_i => '1',
    pulse_i => ext_ref_rst,
    extended_o => pll_ext_rst);
    end generate gen_ext_ref_pll;
    -----------------------------------------------------------------------------
    -- Reset logic
    -----------------------------------------------------------------------------
    ......@@ -353,16 +486,16 @@ begin -- architecture struct
    generic map (
    g_sync_edge => "positive")
    port map (
    clk_i => clk_pll_62m5,
    clk_i => clk_sys_62m5,
    rst_n_i => '1',
    data_i => areset_edge_n_i,
    ppulse_o => areset_edge_ppulse);
    -- logic AND of all async reset sources (active low)
    rstlogic_arst_n <= pll_locked and areset_n_i and (not areset_edge_ppulse);
    rstlogic_arst_n <= areset_n_i and (not areset_edge_ppulse);
    -- concatenation of all clocks required to have synced resets
    rstlogic_clk_in(0) <= clk_pll_62m5;
    rstlogic_clk_in(0) <= clk_sys_62m5;
    rstlogic_clk_in(1) <= clk_ref_62m5;
    cmp_rstlogic_reset : gc_reset
    ......@@ -393,7 +526,7 @@ begin -- architecture struct
    g_num_cs_select => 1,
    g_sclk_polarity => 0)
    port map (
    clk_i => clk_pll_62m5,
    clk_i => clk_sys_62m5,
    rst_n_i => rst_62m5_n,
    value_i => dac_dmtd_data,
    cs_sel_i => "1",
    ......@@ -410,7 +543,7 @@ begin -- architecture struct
    g_num_cs_select => 1,
    g_sclk_polarity => 0)
    port map (
    clk_i => clk_pll_62m5,
    clk_i => clk_sys_62m5,
    rst_n_i => rst_62m5_n,
    value_i => dac_refclk_data,
    cs_sel_i => "1",
    ......@@ -428,6 +561,7 @@ begin -- architecture struct
    generic map (
    g_simulation => g_simulation,
    g_with_external_clock_input => g_with_external_clock_input,
    g_ram_address_space_size_kb => 256,
    g_board_name => "CLB4",
    g_phys_uart => TRUE,
    g_virtual_uart => TRUE,
    ......@@ -440,6 +574,7 @@ begin -- architecture struct
    g_address_granularity => BYTE,
    g_aux_sdb => c_wrc_periph3_sdb,
    g_softpll_enable_debugger => FALSE,
    g_softpll_use_sampled_ref_clocks => TRUE,
    g_vuart_fifo_size => 1024,
    g_pcs_16bit => TRUE,
    g_diag_id => g_diag_id,
    ......@@ -452,7 +587,7 @@ begin -- architecture struct
    g_fabric_iface => g_fabric_iface
    )
    port map (
    clk_sys_i => clk_pll_62m5,
    clk_sys_i => clk_sys_62m5,
    clk_dmtd_i => clk_dmtd,
    clk_ref_i => clk_ref_62m5,
    clk_aux_i => clk_aux_i,
    ......
    top/clbv2_ref_design/clbv2_wr_ref_top.vhd
    View file @ 5886ad1e
    ......@@ -7,8 +7,8 @@
    -- File : clbv2_wr_ref_top.vhd
    -- Author(s) : Peter Jansweijer <peterj@nikhef.nl>
    -- Company : Nikhef
    -- Created : 2017-11-08
    -- Last update: 2019-06-28
    -- Created : 2022-05-08
    -- Last update: 2022-05-18
    -- Standard : VHDL'93
    -------------------------------------------------------------------------------
    -- Description: Top-level file for the WRPC reference design on the CLBv2.
    ......@@ -245,8 +245,8 @@ begin -- architecture top
    port map (
    areset_n_i => reset_n,
    clk_20m_vcxo_i => clk_20m_vcxo_i,
    clk_125m_gtp_n_i => clk_125m_gtx_n_i,
    clk_125m_gtp_p_i => clk_125m_gtx_p_i,
    clk_125m_gtx_n_i => clk_125m_gtx_n_i,
    clk_125m_gtx_p_i => clk_125m_gtx_p_i,
    clk_10m_ext_i => clk_ext_10m,
    clk_sys_62m5_o => clk_sys_62m5,
    clk_ref_62m5_o => clk_ref_62m5,
    ......
    top/clbv2_ref_design/clbv2_wr_ref_top.xdc
    View file @ 5886ad1e
    ......@@ -12,22 +12,22 @@ set_property PACKAGE_PIN D6 [get_ports clk_125m_gtx_p_i]
    set_property PACKAGE_PIN D5 [get_ports clk_125m_gtx_n_i]
    create_clock -period 50.000 -name clk_20m_vcxo_i -waveform {0.000 25.000} [get_ports clk_20m_vcxo_i]
    create_clock -period 8.000 -name clk_125m_gtx_p_i -waveform {0.000 4.000} [get_ports clk_125m_gtx_p_i]
    #create_clock -period 8.000 -name clk_125m_gtx_n_i -waveform {0.000 4.000} [get_ports clk_125m_gtx_n_i] # AR57109: "Only P side needs constraint"
    create_clock -period 8.000 -name clk_125m_gtx -waveform {0.000 4.000} [get_ports clk_125m_gtx_p_i]
    #create_clock -period 8.000 -name clk_125m_gtx -waveform {0.000 4.000} [get_ports clk_125m_gtx_n_i] # AR57109: "Only P side needs constraint"
    create_clock -period 16.000 -name RXOUTCLK -waveform {0.000 8.000} [get_pins cmp_xwrc_board_clbv2/cmp_xwrc_platform/gen_phy_kintex7.cmp_gtx/U_GTX_INST/gtxe2_i/RXOUTCLK]
    create_clock -period 16.000 -name TXOUTCLK -waveform {0.000 8.000} [get_pins cmp_xwrc_board_clbv2/cmp_xwrc_platform/gen_phy_kintex7.cmp_gtx/U_GTX_INST/gtxe2_i/TXOUTCLK]
    create_clock -period 16.000 -name RXOUTCLK -waveform {0.000 8.000} [get_pins cmp_xwrc_board_clbv2/cmp_gtx_lp/U_GTX_INST/gtxe2_i/RXOUTCLK]
    create_clock -period 16.000 -name TXOUTCLK -waveform {0.000 8.000} [get_pins cmp_xwrc_board_clbv2/cmp_gtx_lp/U_GTX_INST/gtxe2_i/TXOUTCLK]
    create_clock -period 100.000 -name dio_clk_p_i -waveform {0.000 50.000} [get_ports dio_clk_p_i]
    set_clock_groups -asynchronous \
    -group {clk_sys } \
    -group {clk_dmtd } \
    -group {clk_20m_vcxo_i } \
    -group {clk_125m_gtx_p_i } \
    -group {RXOUTCLK} \
    -group {TXOUTCLK} \
    -group {clk_ext_mul } \
    -group {dio_clk_p_i}
    -group clk_20m_vcxo_i \
    -group clk_dmtd_pll \
    -group clk_125m_gtx \
    -group clk_125m_gtx_odiv2 \
    -group RXOUTCLK \
    -group TXOUTCLK \
    -group clk_ext_mul \
    -group dio_clk_p_i
    # ---------------------------------------------------------------------------
    # -- SPI interface to DACs
    ......@@ -222,7 +222,6 @@ set_property IOSTANDARD LVDS_25 [get_ports {dio_p_i[0]}]
    set_property PACKAGE_PIN P20 [get_ports {dio_n_i[0]}]
    set_property IOSTANDARD LVDS_25 [get_ports {dio_n_i[0]}]
    # -- Differential outputs. When the I/O (N+1) is configured as output (i.e. when
    # -- dio_oe_n_o(N) = 0), the value of dio_p_o(N) determines the logic state
    # -- of I/O (N+1) on the front panel of the mezzanine
    ......
    top/clbv4_ref_design/clbv4_wr_ref_top.vhd
    View file @ 5886ad1e
    ......@@ -7,8 +7,8 @@
    -- File : clbv4_wr_ref_top.vhd
    -- Author(s) : Pascal Bos <bosp@nikhef.nl>
    -- Company : Nikhef
    -- Created : 2019-05-06
    -- Last update: 2019-05-06
    -- Created : 2022-05-18
    -- Last update: 2022-05-18
    -- Standard : VHDL'93
    -------------------------------------------------------------------------------
    -- Description: Top-level file for the WRPC reference design on the clbv4.
    ......@@ -128,7 +128,7 @@ entity clbv4_wr_ref_top is
    ---------------------------------------------------------------------------
    ---------------------------------------------------------------------------
    -- Miscellanous clbv3 pins
    -- Miscellanous clbv4 pins
    ---------------------------------------------------------------------------
    -- Red LED next to the SFP: blinking indicates that packets are being
    -- transferred.
    ......@@ -183,8 +183,7 @@ entity clbv4_wr_ref_top is
    dio_led_top_o : out std_logic;
    dio_led_bot_o : out std_logic;
    -- I2C interface for accessing FMC EEPROM. Deprecated, was used in
    -- pre-v3.0 releases to store WRPC configuration. Now we use Flash for this.
    -- I2C interface for accessing EEPROM.
    eeprom_scl_b : inout std_logic;
    eeprom_sda_b : inout std_logic;
    ......
    top/clbv4_ref_design/clbv4_wr_ref_top.xdc
    View file @ 5886ad1e
    ......@@ -11,7 +11,7 @@ set_property IOSTANDARD LVDS_25 [get_ports clk_125m_dmtd_n_i]
    create_clock -period 8.000 -name clk_125m_dmtd_p_i -waveform {0.000 4.000} [get_ports clk_125m_dmtd_p_i]
    #create_clock -period 8.000 -name clk_125m_dmtd_n_i -waveform {0.000 4.000} [get_ports clk_125m_dmtd_n_i] # AR57109: "Only P side needs constraint"
    create_generated_clock -name clk_dmtd -source [get_ports clk_125m_dmtd_p_i] -divide_by 2 [get_pins cmp_xwrc_board_clbv4/cmp_xwrc_platform/gen_default_plls.gen_kintex7_artix7_default_plls.gen_kintex7_artix7_direct_dmtd.clk_dmtd_reg/Q]
    create_generated_clock -name clk_dmtd -source [get_ports clk_125m_dmtd_p_i] -divide_by 2 [get_pins cmp_xwrc_board_clbv4/clk_dmtd_reg/Q]
    #Bank 116 -- 125.000 MHz GTP reference
    set_property PACKAGE_PIN D6 [get_ports clk_125m_gtx_p_i]
    ......@@ -20,12 +20,11 @@ set_property PACKAGE_PIN D5 [get_ports clk_125m_gtx_n_i]
    create_clock -period 8.000 -name clk_125m_gtx_p_i -waveform {0.000 4.000} [get_ports clk_125m_gtx_p_i]
    #create_clock -period 8.000 -name clk_125m_gtx_n_i -waveform {0.000 4.000} [get_ports clk_125m_gtx_n_i] # AR57109: "Only P side needs constraint"
    create_clock -period 16.000 -name RXOUTCLK -waveform {0.000 8.000} [get_pins cmp_xwrc_board_clbv4/cmp_xwrc_platform/gen_phy_kintex7.cmp_gtx/U_GTX_INST/gtxe2_i/RXOUTCLK]
    create_clock -period 16.000 -name TXOUTCLK -waveform {0.000 8.000} [get_pins cmp_xwrc_board_clbv4/cmp_xwrc_platform/gen_phy_kintex7.cmp_gtx/U_GTX_INST/gtxe2_i/TXOUTCLK]
    create_clock -period 16.000 -name RXOUTCLK -waveform {0.000 8.000} [get_pins cmp_xwrc_board_clbv4/cmp_gtx_lp/U_GTX_INST/gtxe2_i/RXOUTCLK]
    create_clock -period 16.000 -name TXOUTCLK -waveform {0.000 8.000} [get_pins cmp_xwrc_board_clbv4/cmp_gtx_lp/U_GTX_INST/gtxe2_i/TXOUTCLK]
    create_clock -period 100.000 -name dio_clk_p_i -waveform {0.000 50.000} [get_ports dio_clk_p_i]
    set_clock_groups -asynchronous \
    -group {clk_sys } \
    -group {clk_dmtd } \
    -group {clk_125m_dmtd_p_i } \
    -group {clk_125m_gtx_p_i } \
    ......@@ -234,7 +233,6 @@ set_property IOSTANDARD LVDS_25 [get_ports {dio_n_i[0]}]
    # -- Differential outputs. When the I/O (N+1) is configured as output (i.e. when
    # -- dio_oe_n_o(N) = 0), the value of dio_p_o(N) determines the logic state
    # -- of I/O (N+1) on the front panel of the mezzanine
    #LA04_P
    set_property PACKAGE_PIN N18 [get_ports {dio_p_o[4]}]
    set_property IOSTANDARD LVDS_25 [get_ports {dio_p_o[4]}]
    ......@@ -311,7 +309,7 @@ set_property IOSTANDARD LVCMOS25 [get_ports dio_led_top_o]
    set_property PACKAGE_PIN P21 [get_ports dio_led_bot_o]
    set_property IOSTANDARD LVCMOS25 [get_ports dio_led_bot_o]
    # -- I2C interface for accessing EEPROM
    # -- I2C interface for accessing EEPROM.
    #Bank 14 VCCO - 3.3 V
    set_property PACKAGE_PIN D24 [get_ports eeprom_scl_b]
    set_property IOSTANDARD LVCMOS33 [get_ports eeprom_scl_b]
    ......
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