Skip to content
Projects
Groups
Snippets
Help
Loading...
Sign in
Toggle navigation
W
White Rabbit core collection
Project
Project
Details
Activity
Cycle Analytics
Repository
Repository
Files
Commits
Branches
Tags
Contributors
Graph
Compare
Charts
Issues
30
Issues
30
List
Board
Labels
Milestones
Merge Requests
1
Merge Requests
1
CI / CD
CI / CD
Pipelines
Schedules
Wiki
Wiki
image/svg+xml
Discourse
Discourse
Members
Members
Collapse sidebar
Close sidebar
Activity
Graph
Charts
Create a new issue
Commits
Issue Boards
Open sidebar
Projects
White Rabbit core collection
Commits
4e9a8a43
Commit
4e9a8a43
authored
May 22, 2019
by
Maciej Lipinski
Browse files
Options
Browse Files
Download
Email Patches
Plain Diff
wr_streamers: add default value of fixed_latency_timeout in WB file
parent
064df19b
Show whitespace changes
Inline
Side-by-side
Showing
3 changed files
with
797 additions
and
801 deletions
+797
-801
wr_streamers_wb.vhd
modules/wr_streamers/wr_streamers_wb.vhd
+673
-673
wr_streamers_wb.wb
modules/wr_streamers/wr_streamers_wb.wb
+2
-1
wr_streamers_wbgen2_pkg.vhd
modules/wr_streamers/wr_streamers_wbgen2_pkg.vhd
+122
-127
No files found.
modules/wr_streamers/wr_streamers_wb.vhd
View file @
4e9a8a43
...
...
@@ -3,7 +3,7 @@
---------------------------------------------------------------------------------------
-- File : wr_streamers_wb.vhd
-- Author : auto-generated by wbgen2 from wr_streamers_wb.wb
-- Created : Wed
Nov 14 18:57:24 2018
-- Created : Wed
May 22 18:20:08 2019
-- Version : 0x00000001
-- Standard : VHDL'87
---------------------------------------------------------------------------------------
...
...
@@ -19,7 +19,7 @@ use work.wr_streamers_wbgen2_pkg.all;
entity
wr_streamers_wb
is
port
(
port
(
rst_n_i
:
in
std_logic
;
clk_sys_i
:
in
std_logic
;
wb_adr_i
:
in
std_logic_vector
(
5
downto
0
);
...
...
@@ -35,7 +35,7 @@ port (
wb_stall_o
:
out
std_logic
;
regs_i
:
in
t_wr_streamers_in_registers
;
regs_o
:
out
t_wr_streamers_out_registers
);
);
end
wr_streamers_wb
;
architecture
syn
of
wr_streamers_wb
is
...
...
@@ -90,11 +90,11 @@ signal allzeros : std_logic_vector(31 downto 0);
begin
-- Some internal signals assignments
wrdata_reg
<=
wb_dat_i
;
wrdata_reg
<=
wb_dat_i
;
--
-- Main register bank access process.
process
(
clk_sys_i
,
rst_n_i
)
begin
process
(
clk_sys_i
,
rst_n_i
)
begin
if
(
rst_n_i
=
'0'
)
then
ack_sreg
<=
"0000000000"
;
ack_in_progress
<=
'0'
;
...
...
@@ -132,7 +132,7 @@ begin
wr_streamers_dbg_ctrl_mux_int
<=
'0'
;
wr_streamers_dbg_ctrl_start_byte_int
<=
"00000000"
;
wr_streamers_rstr_rst_sw_int
<=
'0'
;
wr_streamers_rx_cfg6_rx_fixed_latency_timeout_int
<=
"0000
000000000000000000000000"
;
wr_streamers_rx_cfg6_rx_fixed_latency_timeout_int
<=
"0001
000000000000000000000000"
;
elsif
rising_edge
(
clk_sys_i
)
then
-- advance the ACK generator shift register
ack_sreg
(
8
downto
0
)
<=
ack_sreg
(
9
downto
1
);
...
...
@@ -675,16 +675,16 @@ begin
end
if
;
end
if
;
end
if
;
end
process
;
end
process
;
-- Drive the data output bus
wb_dat_o
<=
rddata_reg
;
wb_dat_o
<=
rddata_reg
;
-- Version identifier
regs_o
.
ver_id_o
<=
wr_streamers_ver_id_int
;
regs_o
.
ver_id_o
<=
wr_streamers_ver_id_int
;
-- Reset statistics
process
(
clk_sys_i
,
rst_n_i
)
begin
process
(
clk_sys_i
,
rst_n_i
)
begin
if
(
rst_n_i
=
'0'
)
then
wr_streamers_sscr1_rst_stats_dly0
<=
'0'
;
regs_o
.
sscr1_rst_stats_o
<=
'0'
;
...
...
@@ -692,12 +692,12 @@ begin
wr_streamers_sscr1_rst_stats_dly0
<=
wr_streamers_sscr1_rst_stats_int
;
regs_o
.
sscr1_rst_stats_o
<=
wr_streamers_sscr1_rst_stats_int
and
(
not
wr_streamers_sscr1_rst_stats_dly0
);
end
if
;
end
process
;
end
process
;
-- Reset tx seq id
process
(
clk_sys_i
,
rst_n_i
)
begin
process
(
clk_sys_i
,
rst_n_i
)
begin
if
(
rst_n_i
=
'0'
)
then
wr_streamers_sscr1_rst_seq_id_dly0
<=
'0'
;
regs_o
.
sscr1_rst_seq_id_o
<=
'0'
;
...
...
@@ -705,11 +705,11 @@ begin
wr_streamers_sscr1_rst_seq_id_dly0
<=
wr_streamers_sscr1_rst_seq_id_int
;
regs_o
.
sscr1_rst_seq_id_o
<=
wr_streamers_sscr1_rst_seq_id_int
and
(
not
wr_streamers_sscr1_rst_seq_id_dly0
);
end
if
;
end
process
;
end
process
;
-- Snapshot statistics
regs_o
.
sscr1_snapshot_stats_o
<=
wr_streamers_sscr1_snapshot_stats_int
;
regs_o
.
sscr1_snapshot_stats_o
<=
wr_streamers_sscr1_snapshot_stats_int
;
-- Latency accumulator overflow
-- Reset timestamp cycles
-- Reset timestamp 32 LSB of TAI
...
...
@@ -729,66 +729,66 @@ regs_o.sscr1_snapshot_stats_o <= wr_streamers_sscr1_snapshot_stats_int;
-- WR Streamer frame latency counter (LSB)
-- WR Streamer frame latency counter (MSB)
-- Ethertype
regs_o
.
tx_cfg0_ethertype_o
<=
wr_streamers_tx_cfg0_ethertype_int
;
regs_o
.
tx_cfg0_ethertype_o
<=
wr_streamers_tx_cfg0_ethertype_int
;
-- MAC Local LSB
regs_o
.
tx_cfg1_mac_local_lsb_o
<=
wr_streamers_tx_cfg1_mac_local_lsb_int
;
regs_o
.
tx_cfg1_mac_local_lsb_o
<=
wr_streamers_tx_cfg1_mac_local_lsb_int
;
-- MAC Local MSB
regs_o
.
tx_cfg2_mac_local_msb_o
<=
wr_streamers_tx_cfg2_mac_local_msb_int
;
regs_o
.
tx_cfg2_mac_local_msb_o
<=
wr_streamers_tx_cfg2_mac_local_msb_int
;
-- MAC Target LSB
regs_o
.
tx_cfg3_mac_target_lsb_o
<=
wr_streamers_tx_cfg3_mac_target_lsb_int
;
regs_o
.
tx_cfg3_mac_target_lsb_o
<=
wr_streamers_tx_cfg3_mac_target_lsb_int
;
-- MAC Target MSB
regs_o
.
tx_cfg4_mac_target_msb_o
<=
wr_streamers_tx_cfg4_mac_target_msb_int
;
regs_o
.
tx_cfg4_mac_target_msb_o
<=
wr_streamers_tx_cfg4_mac_target_msb_int
;
-- Enable tagging with Qtags
regs_o
.
tx_cfg5_qtag_ena_o
<=
wr_streamers_tx_cfg5_qtag_ena_int
;
regs_o
.
tx_cfg5_qtag_ena_o
<=
wr_streamers_tx_cfg5_qtag_ena_int
;
-- VLAN ID
regs_o
.
tx_cfg5_qtag_vid_o
<=
wr_streamers_tx_cfg5_qtag_vid_int
;
regs_o
.
tx_cfg5_qtag_vid_o
<=
wr_streamers_tx_cfg5_qtag_vid_int
;
-- Priority
regs_o
.
tx_cfg5_qtag_prio_o
<=
wr_streamers_tx_cfg5_qtag_prio_int
;
regs_o
.
tx_cfg5_qtag_prio_o
<=
wr_streamers_tx_cfg5_qtag_prio_int
;
-- Ethertype
regs_o
.
rx_cfg0_ethertype_o
<=
wr_streamers_rx_cfg0_ethertype_int
;
regs_o
.
rx_cfg0_ethertype_o
<=
wr_streamers_rx_cfg0_ethertype_int
;
-- Accept Broadcast
regs_o
.
rx_cfg0_accept_broadcast_o
<=
wr_streamers_rx_cfg0_accept_broadcast_int
;
regs_o
.
rx_cfg0_accept_broadcast_o
<=
wr_streamers_rx_cfg0_accept_broadcast_int
;
-- Filter Remote
regs_o
.
rx_cfg0_filter_remote_o
<=
wr_streamers_rx_cfg0_filter_remote_int
;
regs_o
.
rx_cfg0_filter_remote_o
<=
wr_streamers_rx_cfg0_filter_remote_int
;
-- MAC Local LSB
regs_o
.
rx_cfg1_mac_local_lsb_o
<=
wr_streamers_rx_cfg1_mac_local_lsb_int
;
regs_o
.
rx_cfg1_mac_local_lsb_o
<=
wr_streamers_rx_cfg1_mac_local_lsb_int
;
-- MAC Local MSB
regs_o
.
rx_cfg2_mac_local_msb_o
<=
wr_streamers_rx_cfg2_mac_local_msb_int
;
regs_o
.
rx_cfg2_mac_local_msb_o
<=
wr_streamers_rx_cfg2_mac_local_msb_int
;
-- MAC Remote LSB
regs_o
.
rx_cfg3_mac_remote_lsb_o
<=
wr_streamers_rx_cfg3_mac_remote_lsb_int
;
regs_o
.
rx_cfg3_mac_remote_lsb_o
<=
wr_streamers_rx_cfg3_mac_remote_lsb_int
;
-- MAC Remote MSB
regs_o
.
rx_cfg4_mac_remote_msb_o
<=
wr_streamers_rx_cfg4_mac_remote_msb_int
;
regs_o
.
rx_cfg4_mac_remote_msb_o
<=
wr_streamers_rx_cfg4_mac_remote_msb_int
;
-- Fixed Latency
regs_o
.
rx_cfg5_fixed_latency_o
<=
wr_streamers_rx_cfg5_fixed_latency_int
;
regs_o
.
rx_cfg5_fixed_latency_o
<=
wr_streamers_rx_cfg5_fixed_latency_int
;
-- Tx Ethertype
regs_o
.
cfg_or_tx_ethtype_o
<=
wr_streamers_cfg_or_tx_ethtype_int
;
regs_o
.
cfg_or_tx_ethtype_o
<=
wr_streamers_cfg_or_tx_ethtype_int
;
-- Tx MAC Local
regs_o
.
cfg_or_tx_mac_loc_o
<=
wr_streamers_cfg_or_tx_mac_loc_int
;
regs_o
.
cfg_or_tx_mac_loc_o
<=
wr_streamers_cfg_or_tx_mac_loc_int
;
-- Tx MAC Target
regs_o
.
cfg_or_tx_mac_tar_o
<=
wr_streamers_cfg_or_tx_mac_tar_int
;
regs_o
.
cfg_or_tx_mac_tar_o
<=
wr_streamers_cfg_or_tx_mac_tar_int
;
-- QTAG
regs_o
.
cfg_or_tx_qtag_o
<=
wr_streamers_cfg_or_tx_qtag_int
;
regs_o
.
cfg_or_tx_qtag_o
<=
wr_streamers_cfg_or_tx_qtag_int
;
-- Rx Ethertype
regs_o
.
cfg_or_rx_ethertype_o
<=
wr_streamers_cfg_or_rx_ethertype_int
;
regs_o
.
cfg_or_rx_ethertype_o
<=
wr_streamers_cfg_or_rx_ethertype_int
;
-- Rx MAC Local
regs_o
.
cfg_or_rx_mac_loc_o
<=
wr_streamers_cfg_or_rx_mac_loc_int
;
regs_o
.
cfg_or_rx_mac_loc_o
<=
wr_streamers_cfg_or_rx_mac_loc_int
;
-- Rx MAC Remote
regs_o
.
cfg_or_rx_mac_rem_o
<=
wr_streamers_cfg_or_rx_mac_rem_int
;
regs_o
.
cfg_or_rx_mac_rem_o
<=
wr_streamers_cfg_or_rx_mac_rem_int
;
-- Rx Accept Broadcast
regs_o
.
cfg_or_rx_acc_broadcast_o
<=
wr_streamers_cfg_or_rx_acc_broadcast_int
;
regs_o
.
cfg_or_rx_acc_broadcast_o
<=
wr_streamers_cfg_or_rx_acc_broadcast_int
;
-- Rx Filter Remote
regs_o
.
cfg_or_rx_ftr_remote_o
<=
wr_streamers_cfg_or_rx_ftr_remote_int
;
regs_o
.
cfg_or_rx_ftr_remote_o
<=
wr_streamers_cfg_or_rx_ftr_remote_int
;
-- Rx Fixed Latency
regs_o
.
cfg_or_rx_fix_lat_o
<=
wr_streamers_cfg_or_rx_fix_lat_int
;
regs_o
.
cfg_or_rx_fix_lat_o
<=
wr_streamers_cfg_or_rx_fix_lat_int
;
-- Debug Tx (0) or Rx (1)
regs_o
.
dbg_ctrl_mux_o
<=
wr_streamers_dbg_ctrl_mux_int
;
regs_o
.
dbg_ctrl_mux_o
<=
wr_streamers_dbg_ctrl_mux_int
;
-- Debug Start byte
regs_o
.
dbg_ctrl_start_byte_o
<=
wr_streamers_dbg_ctrl_start_byte_int
;
regs_o
.
dbg_ctrl_start_byte_o
<=
wr_streamers_dbg_ctrl_start_byte_int
;
-- Debug content
-- DUMMY value to read
-- Software reset streamers
process
(
clk_sys_i
,
rst_n_i
)
begin
process
(
clk_sys_i
,
rst_n_i
)
begin
if
(
rst_n_i
=
'0'
)
then
wr_streamers_rstr_rst_sw_dly0
<=
'0'
;
regs_o
.
rstr_rst_sw_o
<=
'0'
;
...
...
@@ -796,19 +796,19 @@ begin
wr_streamers_rstr_rst_sw_dly0
<=
wr_streamers_rstr_rst_sw_int
;
regs_o
.
rstr_rst_sw_o
<=
wr_streamers_rstr_rst_sw_int
and
(
not
wr_streamers_rstr_rst_sw_dly0
);
end
if
;
end
process
;
end
process
;
-- WR Streamer RX Buffer Overflow Count
-- WR Streamer RX Late Frames Count
-- WR Streamer RX Timed-out Frames Count
-- WR Streamer RX OK Frames Count
-- RX Fixed Latency Timeout
regs_o
.
rx_cfg6_rx_fixed_latency_timeout_o
<=
wr_streamers_rx_cfg6_rx_fixed_latency_timeout_int
;
rwaddr_reg
<=
wb_adr_i
;
wb_stall_o
<=
(
not
ack_sreg
(
0
))
and
(
wb_stb_i
and
wb_cyc_i
);
wb_err_o
<=
'0'
;
wb_rty_o
<=
'0'
;
-- RX Fixed Latency Timeout
(Default: 0x1000000=~134ms)
regs_o
.
rx_cfg6_rx_fixed_latency_timeout_o
<=
wr_streamers_rx_cfg6_rx_fixed_latency_timeout_int
;
rwaddr_reg
<=
wb_adr_i
;
wb_stall_o
<=
(
not
ack_sreg
(
0
))
and
(
wb_stb_i
and
wb_cyc_i
);
wb_err_o
<=
'0'
;
wb_rty_o
<=
'0'
;
-- ACK signal generation. Just pass the LSB of ACK counter.
wb_ack_o
<=
ack_sreg
(
0
);
wb_ack_o
<=
ack_sreg
(
0
);
end
syn
;
modules/wr_streamers/wr_streamers_wb.wb
View file @
4e9a8a43
...
...
@@ -706,10 +706,11 @@ peripheral {
name = "Rx Config Reg 6";
prefix = "RX_CFG6";
field {
name = "RX Fixed Latency Timeout";
name = "RX Fixed Latency Timeout
(Default: 0x1000000=~134ms)
";
prefix = "RX_FIXED_LATENCY_TIMEOUT";
type = SLV;
size = 28;
reset_value = 0x1000000;
access_bus = READ_WRITE;
access_dev = READ_ONLY;
};
...
...
modules/wr_streamers/wr_streamers_wbgen2_pkg.vhd
View file @
4e9a8a43
...
...
@@ -3,7 +3,7 @@
---------------------------------------------------------------------------------------
-- File : wr_streamers_wbgen2_pkg.vhd
-- Author : auto-generated by wbgen2 from wr_streamers_wb.wb
-- Created : Wed
Nov 14 18:57:24 2018
-- Created : Wed
May 22 18:20:08 2019
-- Version : 0x00000001
-- Standard : VHDL'87
---------------------------------------------------------------------------------------
...
...
@@ -149,10 +149,9 @@ package wr_streamers_wbgen2_pkg is
rstr_rst_sw_o
=>
'0'
,
rx_cfg6_rx_fixed_latency_timeout_o
=>
(
others
=>
'0'
)
);
function
"or"
(
left
,
right
:
t_wr_streamers_in_registers
)
return
t_wr_streamers_in_registers
;
function
f_x_to_zero
(
x
:
std_logic
)
return
std_logic
;
function
f_x_to_zero
(
x
:
std_logic_vector
)
return
std_logic_vector
;
function
"or"
(
left
,
right
:
t_wr_streamers_in_registers
)
return
t_wr_streamers_in_registers
;
function
f_x_to_zero
(
x
:
std_logic
)
return
std_logic
;
function
f_x_to_zero
(
x
:
std_logic_vector
)
return
std_logic_vector
;
component
wr_streamers_wb
is
port
(
...
...
@@ -173,60 +172,56 @@ component wr_streamers_wb is
regs_o
:
out
t_wr_streamers_out_registers
);
end
component
;
end
package
;
package
body
wr_streamers_wbgen2_pkg
is
function
f_x_to_zero
(
x
:
std_logic
)
return
std_logic
is
begin
if
x
=
'1'
then
return
'1'
;
else
return
'0'
;
end
if
;
if
x
=
'1'
then
return
'1'
;
else
return
'0'
;
end
if
;
end
function
;
function
f_x_to_zero
(
x
:
std_logic_vector
)
return
std_logic_vector
is
variable
tmp
:
std_logic_vector
(
x
'length
-1
downto
0
);
variable
tmp
:
std_logic_vector
(
x
'length
-1
downto
0
);
begin
for
i
in
0
to
x
'length
-1
loop
if
(
x
(
i
)
=
'X'
or
x
(
i
)
=
'U
'
)
then
tmp
(
i
):
=
'0
'
;
else
tmp
(
i
):
=
x
(
i
)
;
end
if
;
end
loop
;
return
tmp
;
for
i
in
0
to
x
'length
-1
loop
if
(
x
(
i
)
=
'1
'
)
then
tmp
(
i
):
=
'1
'
;
else
tmp
(
i
):
=
'0'
;
end
if
;
end
loop
;
return
tmp
;
end
function
;
function
"or"
(
left
,
right
:
t_wr_streamers_in_registers
)
return
t_wr_streamers_in_registers
is
variable
tmp
:
t_wr_streamers_in_registers
;
variable
tmp
:
t_wr_streamers_in_registers
;
begin
tmp
.
sscr1_rx_latency_acc_overflow_i
:
=
f_x_to_zero
(
left
.
sscr1_rx_latency_acc_overflow_i
)
or
f_x_to_zero
(
right
.
sscr1_rx_latency_acc_overflow_i
);
tmp
.
sscr1_rst_ts_cyc_i
:
=
f_x_to_zero
(
left
.
sscr1_rst_ts_cyc_i
)
or
f_x_to_zero
(
right
.
sscr1_rst_ts_cyc_i
);
tmp
.
sscr2_rst_ts_tai_lsb_i
:
=
f_x_to_zero
(
left
.
sscr2_rst_ts_tai_lsb_i
)
or
f_x_to_zero
(
right
.
sscr2_rst_ts_tai_lsb_i
);
tmp
.
sscr3_rst_ts_tai_msb_i
:
=
f_x_to_zero
(
left
.
sscr3_rst_ts_tai_msb_i
)
or
f_x_to_zero
(
right
.
sscr3_rst_ts_tai_msb_i
);
tmp
.
rx_stat0_rx_latency_max_i
:
=
f_x_to_zero
(
left
.
rx_stat0_rx_latency_max_i
)
or
f_x_to_zero
(
right
.
rx_stat0_rx_latency_max_i
);
tmp
.
rx_stat1_rx_latency_min_i
:
=
f_x_to_zero
(
left
.
rx_stat1_rx_latency_min_i
)
or
f_x_to_zero
(
right
.
rx_stat1_rx_latency_min_i
);
tmp
.
tx_stat2_tx_sent_cnt_lsb_i
:
=
f_x_to_zero
(
left
.
tx_stat2_tx_sent_cnt_lsb_i
)
or
f_x_to_zero
(
right
.
tx_stat2_tx_sent_cnt_lsb_i
);
tmp
.
tx_stat3_tx_sent_cnt_msb_i
:
=
f_x_to_zero
(
left
.
tx_stat3_tx_sent_cnt_msb_i
)
or
f_x_to_zero
(
right
.
tx_stat3_tx_sent_cnt_msb_i
);
tmp
.
rx_stat4_rx_rcvd_cnt_lsb_i
:
=
f_x_to_zero
(
left
.
rx_stat4_rx_rcvd_cnt_lsb_i
)
or
f_x_to_zero
(
right
.
rx_stat4_rx_rcvd_cnt_lsb_i
);
tmp
.
rx_stat5_rx_rcvd_cnt_msb_i
:
=
f_x_to_zero
(
left
.
rx_stat5_rx_rcvd_cnt_msb_i
)
or
f_x_to_zero
(
right
.
rx_stat5_rx_rcvd_cnt_msb_i
);
tmp
.
rx_stat6_rx_loss_cnt_lsb_i
:
=
f_x_to_zero
(
left
.
rx_stat6_rx_loss_cnt_lsb_i
)
or
f_x_to_zero
(
right
.
rx_stat6_rx_loss_cnt_lsb_i
);
tmp
.
rx_stat7_rx_loss_cnt_msb_i
:
=
f_x_to_zero
(
left
.
rx_stat7_rx_loss_cnt_msb_i
)
or
f_x_to_zero
(
right
.
rx_stat7_rx_loss_cnt_msb_i
);
tmp
.
rx_stat8_rx_lost_block_cnt_lsb_i
:
=
f_x_to_zero
(
left
.
rx_stat8_rx_lost_block_cnt_lsb_i
)
or
f_x_to_zero
(
right
.
rx_stat8_rx_lost_block_cnt_lsb_i
);
tmp
.
rx_stat9_rx_lost_block_cnt_msb_i
:
=
f_x_to_zero
(
left
.
rx_stat9_rx_lost_block_cnt_msb_i
)
or
f_x_to_zero
(
right
.
rx_stat9_rx_lost_block_cnt_msb_i
);
tmp
.
rx_stat10_rx_latency_acc_lsb_i
:
=
f_x_to_zero
(
left
.
rx_stat10_rx_latency_acc_lsb_i
)
or
f_x_to_zero
(
right
.
rx_stat10_rx_latency_acc_lsb_i
);
tmp
.
rx_stat11_rx_latency_acc_msb_i
:
=
f_x_to_zero
(
left
.
rx_stat11_rx_latency_acc_msb_i
)
or
f_x_to_zero
(
right
.
rx_stat11_rx_latency_acc_msb_i
);
tmp
.
rx_stat12_rx_latency_acc_cnt_lsb_i
:
=
f_x_to_zero
(
left
.
rx_stat12_rx_latency_acc_cnt_lsb_i
)
or
f_x_to_zero
(
right
.
rx_stat12_rx_latency_acc_cnt_lsb_i
);
tmp
.
rx_stat13_rx_latency_acc_cnt_msb_i
:
=
f_x_to_zero
(
left
.
rx_stat13_rx_latency_acc_cnt_msb_i
)
or
f_x_to_zero
(
right
.
rx_stat13_rx_latency_acc_cnt_msb_i
);
tmp
.
dbg_data_i
:
=
f_x_to_zero
(
left
.
dbg_data_i
)
or
f_x_to_zero
(
right
.
dbg_data_i
);
tmp
.
dummy_dummy_i
:
=
f_x_to_zero
(
left
.
dummy_dummy_i
)
or
f_x_to_zero
(
right
.
dummy_dummy_i
);
tmp
.
rx_stat14_rx_buf_overflow_cnt_i
:
=
f_x_to_zero
(
left
.
rx_stat14_rx_buf_overflow_cnt_i
)
or
f_x_to_zero
(
right
.
rx_stat14_rx_buf_overflow_cnt_i
);
tmp
.
rx_stat15_rx_late_frames_cnt_i
:
=
f_x_to_zero
(
left
.
rx_stat15_rx_late_frames_cnt_i
)
or
f_x_to_zero
(
right
.
rx_stat15_rx_late_frames_cnt_i
);
tmp
.
rx_stat16_rx_timeout_frames_cnt_i
:
=
f_x_to_zero
(
left
.
rx_stat16_rx_timeout_frames_cnt_i
)
or
f_x_to_zero
(
right
.
rx_stat16_rx_timeout_frames_cnt_i
);
tmp
.
rx_stat17_rx_match_frames_cnt_i
:
=
f_x_to_zero
(
left
.
rx_stat17_rx_match_frames_cnt_i
)
or
f_x_to_zero
(
right
.
rx_stat17_rx_match_frames_cnt_i
);
return
tmp
;
tmp
.
sscr1_rx_latency_acc_overflow_i
:
=
f_x_to_zero
(
left
.
sscr1_rx_latency_acc_overflow_i
)
or
f_x_to_zero
(
right
.
sscr1_rx_latency_acc_overflow_i
);
tmp
.
sscr1_rst_ts_cyc_i
:
=
f_x_to_zero
(
left
.
sscr1_rst_ts_cyc_i
)
or
f_x_to_zero
(
right
.
sscr1_rst_ts_cyc_i
);
tmp
.
sscr2_rst_ts_tai_lsb_i
:
=
f_x_to_zero
(
left
.
sscr2_rst_ts_tai_lsb_i
)
or
f_x_to_zero
(
right
.
sscr2_rst_ts_tai_lsb_i
);
tmp
.
sscr3_rst_ts_tai_msb_i
:
=
f_x_to_zero
(
left
.
sscr3_rst_ts_tai_msb_i
)
or
f_x_to_zero
(
right
.
sscr3_rst_ts_tai_msb_i
);
tmp
.
rx_stat0_rx_latency_max_i
:
=
f_x_to_zero
(
left
.
rx_stat0_rx_latency_max_i
)
or
f_x_to_zero
(
right
.
rx_stat0_rx_latency_max_i
);
tmp
.
rx_stat1_rx_latency_min_i
:
=
f_x_to_zero
(
left
.
rx_stat1_rx_latency_min_i
)
or
f_x_to_zero
(
right
.
rx_stat1_rx_latency_min_i
);
tmp
.
tx_stat2_tx_sent_cnt_lsb_i
:
=
f_x_to_zero
(
left
.
tx_stat2_tx_sent_cnt_lsb_i
)
or
f_x_to_zero
(
right
.
tx_stat2_tx_sent_cnt_lsb_i
);
tmp
.
tx_stat3_tx_sent_cnt_msb_i
:
=
f_x_to_zero
(
left
.
tx_stat3_tx_sent_cnt_msb_i
)
or
f_x_to_zero
(
right
.
tx_stat3_tx_sent_cnt_msb_i
);
tmp
.
rx_stat4_rx_rcvd_cnt_lsb_i
:
=
f_x_to_zero
(
left
.
rx_stat4_rx_rcvd_cnt_lsb_i
)
or
f_x_to_zero
(
right
.
rx_stat4_rx_rcvd_cnt_lsb_i
);
tmp
.
rx_stat5_rx_rcvd_cnt_msb_i
:
=
f_x_to_zero
(
left
.
rx_stat5_rx_rcvd_cnt_msb_i
)
or
f_x_to_zero
(
right
.
rx_stat5_rx_rcvd_cnt_msb_i
);
tmp
.
rx_stat6_rx_loss_cnt_lsb_i
:
=
f_x_to_zero
(
left
.
rx_stat6_rx_loss_cnt_lsb_i
)
or
f_x_to_zero
(
right
.
rx_stat6_rx_loss_cnt_lsb_i
);
tmp
.
rx_stat7_rx_loss_cnt_msb_i
:
=
f_x_to_zero
(
left
.
rx_stat7_rx_loss_cnt_msb_i
)
or
f_x_to_zero
(
right
.
rx_stat7_rx_loss_cnt_msb_i
);
tmp
.
rx_stat8_rx_lost_block_cnt_lsb_i
:
=
f_x_to_zero
(
left
.
rx_stat8_rx_lost_block_cnt_lsb_i
)
or
f_x_to_zero
(
right
.
rx_stat8_rx_lost_block_cnt_lsb_i
);
tmp
.
rx_stat9_rx_lost_block_cnt_msb_i
:
=
f_x_to_zero
(
left
.
rx_stat9_rx_lost_block_cnt_msb_i
)
or
f_x_to_zero
(
right
.
rx_stat9_rx_lost_block_cnt_msb_i
);
tmp
.
rx_stat10_rx_latency_acc_lsb_i
:
=
f_x_to_zero
(
left
.
rx_stat10_rx_latency_acc_lsb_i
)
or
f_x_to_zero
(
right
.
rx_stat10_rx_latency_acc_lsb_i
);
tmp
.
rx_stat11_rx_latency_acc_msb_i
:
=
f_x_to_zero
(
left
.
rx_stat11_rx_latency_acc_msb_i
)
or
f_x_to_zero
(
right
.
rx_stat11_rx_latency_acc_msb_i
);
tmp
.
rx_stat12_rx_latency_acc_cnt_lsb_i
:
=
f_x_to_zero
(
left
.
rx_stat12_rx_latency_acc_cnt_lsb_i
)
or
f_x_to_zero
(
right
.
rx_stat12_rx_latency_acc_cnt_lsb_i
);
tmp
.
rx_stat13_rx_latency_acc_cnt_msb_i
:
=
f_x_to_zero
(
left
.
rx_stat13_rx_latency_acc_cnt_msb_i
)
or
f_x_to_zero
(
right
.
rx_stat13_rx_latency_acc_cnt_msb_i
);
tmp
.
dbg_data_i
:
=
f_x_to_zero
(
left
.
dbg_data_i
)
or
f_x_to_zero
(
right
.
dbg_data_i
);
tmp
.
dummy_dummy_i
:
=
f_x_to_zero
(
left
.
dummy_dummy_i
)
or
f_x_to_zero
(
right
.
dummy_dummy_i
);
tmp
.
rx_stat14_rx_buf_overflow_cnt_i
:
=
f_x_to_zero
(
left
.
rx_stat14_rx_buf_overflow_cnt_i
)
or
f_x_to_zero
(
right
.
rx_stat14_rx_buf_overflow_cnt_i
);
tmp
.
rx_stat15_rx_late_frames_cnt_i
:
=
f_x_to_zero
(
left
.
rx_stat15_rx_late_frames_cnt_i
)
or
f_x_to_zero
(
right
.
rx_stat15_rx_late_frames_cnt_i
);
tmp
.
rx_stat16_rx_timeout_frames_cnt_i
:
=
f_x_to_zero
(
left
.
rx_stat16_rx_timeout_frames_cnt_i
)
or
f_x_to_zero
(
right
.
rx_stat16_rx_timeout_frames_cnt_i
);
tmp
.
rx_stat17_rx_match_frames_cnt_i
:
=
f_x_to_zero
(
left
.
rx_stat17_rx_match_frames_cnt_i
)
or
f_x_to_zero
(
right
.
rx_stat17_rx_match_frames_cnt_i
);
return
tmp
;
end
function
;
end
package
body
;
Write
Preview
Markdown
is supported
0%
Try again
or
attach a new file
Attach a file
Cancel
You are about to add
0
people
to the discussion. Proceed with caution.
Finish editing this message first!
Cancel
Please
register
or
sign in
to comment