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White Rabbit core collection
Commits
4e9a8a43
Commit
4e9a8a43
authored
May 22, 2019
by
Maciej Lipinski
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Plain Diff
wr_streamers: add default value of fixed_latency_timeout in WB file
parent
064df19b
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Showing
3 changed files
with
797 additions
and
801 deletions
+797
-801
wr_streamers_wb.vhd
modules/wr_streamers/wr_streamers_wb.vhd
+673
-673
wr_streamers_wb.wb
modules/wr_streamers/wr_streamers_wb.wb
+2
-1
wr_streamers_wbgen2_pkg.vhd
modules/wr_streamers/wr_streamers_wbgen2_pkg.vhd
+122
-127
No files found.
modules/wr_streamers/wr_streamers_wb.vhd
View file @
4e9a8a43
...
@@ -3,7 +3,7 @@
...
@@ -3,7 +3,7 @@
---------------------------------------------------------------------------------------
---------------------------------------------------------------------------------------
-- File : wr_streamers_wb.vhd
-- File : wr_streamers_wb.vhd
-- Author : auto-generated by wbgen2 from wr_streamers_wb.wb
-- Author : auto-generated by wbgen2 from wr_streamers_wb.wb
-- Created : Wed
Nov 14 18:57:24 2018
-- Created : Wed
May 22 18:20:08 2019
-- Version : 0x00000001
-- Version : 0x00000001
-- Standard : VHDL'87
-- Standard : VHDL'87
---------------------------------------------------------------------------------------
---------------------------------------------------------------------------------------
...
@@ -19,23 +19,23 @@ use work.wr_streamers_wbgen2_pkg.all;
...
@@ -19,23 +19,23 @@ use work.wr_streamers_wbgen2_pkg.all;
entity
wr_streamers_wb
is
entity
wr_streamers_wb
is
port
(
port
(
rst_n_i
:
in
std_logic
;
rst_n_i
:
in
std_logic
;
clk_sys_i
:
in
std_logic
;
clk_sys_i
:
in
std_logic
;
wb_adr_i
:
in
std_logic_vector
(
5
downto
0
);
wb_adr_i
:
in
std_logic_vector
(
5
downto
0
);
wb_dat_i
:
in
std_logic_vector
(
31
downto
0
);
wb_dat_i
:
in
std_logic_vector
(
31
downto
0
);
wb_dat_o
:
out
std_logic_vector
(
31
downto
0
);
wb_dat_o
:
out
std_logic_vector
(
31
downto
0
);
wb_cyc_i
:
in
std_logic
;
wb_cyc_i
:
in
std_logic
;
wb_sel_i
:
in
std_logic_vector
(
3
downto
0
);
wb_sel_i
:
in
std_logic_vector
(
3
downto
0
);
wb_stb_i
:
in
std_logic
;
wb_stb_i
:
in
std_logic
;
wb_we_i
:
in
std_logic
;
wb_we_i
:
in
std_logic
;
wb_ack_o
:
out
std_logic
;
wb_ack_o
:
out
std_logic
;
wb_err_o
:
out
std_logic
;
wb_err_o
:
out
std_logic
;
wb_rty_o
:
out
std_logic
;
wb_rty_o
:
out
std_logic
;
wb_stall_o
:
out
std_logic
;
wb_stall_o
:
out
std_logic
;
regs_i
:
in
t_wr_streamers_in_registers
;
regs_i
:
in
t_wr_streamers_in_registers
;
regs_o
:
out
t_wr_streamers_out_registers
regs_o
:
out
t_wr_streamers_out_registers
);
);
end
wr_streamers_wb
;
end
wr_streamers_wb
;
architecture
syn
of
wr_streamers_wb
is
architecture
syn
of
wr_streamers_wb
is
...
@@ -90,626 +90,626 @@ signal allzeros : std_logic_vector(31 downto 0);
...
@@ -90,626 +90,626 @@ signal allzeros : std_logic_vector(31 downto 0);
begin
begin
-- Some internal signals assignments
-- Some internal signals assignments
wrdata_reg
<=
wb_dat_i
;
wrdata_reg
<=
wb_dat_i
;
--
--
-- Main register bank access process.
-- Main register bank access process.
process
(
clk_sys_i
,
rst_n_i
)
process
(
clk_sys_i
,
rst_n_i
)
begin
begin
if
(
rst_n_i
=
'0'
)
then
if
(
rst_n_i
=
'0'
)
then
ack_sreg
<=
"0000000000"
;
ack_sreg
<=
"0000000000"
;
ack_in_progress
<=
'0'
;
ack_in_progress
<=
'0'
;
rddata_reg
<=
"00000000000000000000000000000000"
;
rddata_reg
<=
"00000000000000000000000000000000"
;
wr_streamers_ver_id_int
<=
"00000000000000000000000000000001"
;
wr_streamers_ver_id_int
<=
"00000000000000000000000000000001"
;
wr_streamers_sscr1_rst_stats_int
<=
'0'
;
wr_streamers_sscr1_rst_stats_int
<=
'0'
;
wr_streamers_sscr1_rst_seq_id_int
<=
'0'
;
wr_streamers_sscr1_rst_seq_id_int
<=
'0'
;
wr_streamers_sscr1_snapshot_stats_int
<=
'0'
;
wr_streamers_sscr1_snapshot_stats_int
<=
'0'
;
wr_streamers_tx_cfg0_ethertype_int
<=
"0000000000000000"
;
wr_streamers_tx_cfg0_ethertype_int
<=
"0000000000000000"
;
wr_streamers_tx_cfg1_mac_local_lsb_int
<=
"00000000000000000000000000000000"
;
wr_streamers_tx_cfg1_mac_local_lsb_int
<=
"00000000000000000000000000000000"
;
wr_streamers_tx_cfg2_mac_local_msb_int
<=
"0000000000000000"
;
wr_streamers_tx_cfg2_mac_local_msb_int
<=
"0000000000000000"
;
wr_streamers_tx_cfg3_mac_target_lsb_int
<=
"00000000000000000000000000000000"
;
wr_streamers_tx_cfg3_mac_target_lsb_int
<=
"00000000000000000000000000000000"
;
wr_streamers_tx_cfg4_mac_target_msb_int
<=
"0000000000000000"
;
wr_streamers_tx_cfg4_mac_target_msb_int
<=
"0000000000000000"
;
wr_streamers_tx_cfg5_qtag_ena_int
<=
'0'
;
wr_streamers_tx_cfg5_qtag_ena_int
<=
'0'
;
wr_streamers_tx_cfg5_qtag_vid_int
<=
"000000000000"
;
wr_streamers_tx_cfg5_qtag_vid_int
<=
"000000000000"
;
wr_streamers_tx_cfg5_qtag_prio_int
<=
"000"
;
wr_streamers_tx_cfg5_qtag_prio_int
<=
"000"
;
wr_streamers_rx_cfg0_ethertype_int
<=
"0000000000000000"
;
wr_streamers_rx_cfg0_ethertype_int
<=
"0000000000000000"
;
wr_streamers_rx_cfg0_accept_broadcast_int
<=
'0'
;
wr_streamers_rx_cfg0_accept_broadcast_int
<=
'0'
;
wr_streamers_rx_cfg0_filter_remote_int
<=
'0'
;
wr_streamers_rx_cfg0_filter_remote_int
<=
'0'
;
wr_streamers_rx_cfg1_mac_local_lsb_int
<=
"00000000000000000000000000000000"
;
wr_streamers_rx_cfg1_mac_local_lsb_int
<=
"00000000000000000000000000000000"
;
wr_streamers_rx_cfg2_mac_local_msb_int
<=
"0000000000000000"
;
wr_streamers_rx_cfg2_mac_local_msb_int
<=
"0000000000000000"
;
wr_streamers_rx_cfg3_mac_remote_lsb_int
<=
"00000000000000000000000000000000"
;
wr_streamers_rx_cfg3_mac_remote_lsb_int
<=
"00000000000000000000000000000000"
;
wr_streamers_rx_cfg4_mac_remote_msb_int
<=
"0000000000000000"
;
wr_streamers_rx_cfg4_mac_remote_msb_int
<=
"0000000000000000"
;
wr_streamers_rx_cfg5_fixed_latency_int
<=
"0000000000000000000000000000"
;
wr_streamers_rx_cfg5_fixed_latency_int
<=
"0000000000000000000000000000"
;
wr_streamers_cfg_or_tx_ethtype_int
<=
'0'
;
wr_streamers_cfg_or_tx_ethtype_int
<=
'0'
;
wr_streamers_cfg_or_tx_mac_loc_int
<=
'0'
;
wr_streamers_cfg_or_tx_mac_loc_int
<=
'0'
;
wr_streamers_cfg_or_tx_mac_tar_int
<=
'0'
;
wr_streamers_cfg_or_tx_mac_tar_int
<=
'0'
;
wr_streamers_cfg_or_tx_qtag_int
<=
'0'
;
wr_streamers_cfg_or_tx_qtag_int
<=
'0'
;
wr_streamers_cfg_or_rx_ethertype_int
<=
'0'
;
wr_streamers_cfg_or_rx_ethertype_int
<=
'0'
;
wr_streamers_cfg_or_rx_mac_loc_int
<=
'0'
;
wr_streamers_cfg_or_rx_mac_loc_int
<=
'0'
;
wr_streamers_cfg_or_rx_mac_rem_int
<=
'0'
;
wr_streamers_cfg_or_rx_mac_rem_int
<=
'0'
;
wr_streamers_cfg_or_rx_acc_broadcast_int
<=
'0'
;
wr_streamers_cfg_or_rx_acc_broadcast_int
<=
'0'
;
wr_streamers_cfg_or_rx_ftr_remote_int
<=
'0'
;
wr_streamers_cfg_or_rx_ftr_remote_int
<=
'0'
;
wr_streamers_cfg_or_rx_fix_lat_int
<=
'0'
;
wr_streamers_cfg_or_rx_fix_lat_int
<=
'0'
;
wr_streamers_dbg_ctrl_mux_int
<=
'0'
;
wr_streamers_dbg_ctrl_mux_int
<=
'0'
;
wr_streamers_dbg_ctrl_start_byte_int
<=
"00000000"
;
wr_streamers_dbg_ctrl_start_byte_int
<=
"00000000"
;
wr_streamers_rstr_rst_sw_int
<=
'0'
;
wr_streamers_rstr_rst_sw_int
<=
'0'
;
wr_streamers_rx_cfg6_rx_fixed_latency_timeout_int
<=
"0000
000000000000000000000000"
;
wr_streamers_rx_cfg6_rx_fixed_latency_timeout_int
<=
"0001
000000000000000000000000"
;
elsif
rising_edge
(
clk_sys_i
)
then
elsif
rising_edge
(
clk_sys_i
)
then
-- advance the ACK generator shift register
-- advance the ACK generator shift register
ack_sreg
(
8
downto
0
)
<=
ack_sreg
(
9
downto
1
);
ack_sreg
(
8
downto
0
)
<=
ack_sreg
(
9
downto
1
);
ack_sreg
(
9
)
<=
'0'
;
ack_sreg
(
9
)
<=
'0'
;
if
(
ack_in_progress
=
'1'
)
then
if
(
ack_in_progress
=
'1'
)
then
if
(
ack_sreg
(
0
)
=
'1'
)
then
if
(
ack_sreg
(
0
)
=
'1'
)
then
wr_streamers_sscr1_rst_stats_int
<=
'0'
;
wr_streamers_sscr1_rst_stats_int
<=
'0'
;
wr_streamers_sscr1_rst_seq_id_int
<=
'0'
;
wr_streamers_sscr1_rst_seq_id_int
<=
'0'
;
wr_streamers_rstr_rst_sw_int
<=
'0'
;
wr_streamers_rstr_rst_sw_int
<=
'0'
;
ack_in_progress
<=
'0'
;
ack_in_progress
<=
'0'
;
else
end
if
;
else
else
end
if
;
if
((
wb_cyc_i
=
'1'
)
and
(
wb_stb_i
=
'1'
))
then
else
case
rwaddr_reg
(
5
downto
0
)
is
if
((
wb_cyc_i
=
'1'
)
and
(
wb_stb_i
=
'1'
))
then
when
"000000"
=>
case
rwaddr_reg
(
5
downto
0
)
is
if
(
wb_we_i
=
'1'
)
then
when
"000000"
=>
wr_streamers_ver_id_int
<=
wrdata_reg
(
31
downto
0
);
if
(
wb_we_i
=
'1'
)
then
end
if
;
wr_streamers_ver_id_int
<=
wrdata_reg
(
31
downto
0
);
rddata_reg
(
31
downto
0
)
<=
wr_streamers_ver_id_int
;
end
if
;
ack_sreg
(
0
)
<=
'1'
;
rddata_reg
(
31
downto
0
)
<=
wr_streamers_ver_id_int
;
ack_in_progress
<=
'1'
;
ack_sreg
(
0
)
<=
'1'
;
when
"000001"
=>
ack_in_progress
<=
'1'
;
if
(
wb_we_i
=
'1'
)
then
when
"000001"
=>
wr_streamers_sscr1_rst_stats_int
<=
wrdata_reg
(
0
);
if
(
wb_we_i
=
'1'
)
then
wr_streamers_sscr1_rst_seq_id_int
<=
wrdata_reg
(
1
);
wr_streamers_sscr1_rst_stats_int
<=
wrdata_reg
(
0
);
wr_streamers_sscr1_snapshot_stats_int
<=
wrdata_reg
(
2
);
wr_streamers_sscr1_rst_seq_id_int
<=
wrdata_reg
(
1
);
end
if
;
wr_streamers_sscr1_snapshot_stats_int
<=
wrdata_reg
(
2
);
rddata_reg
(
0
)
<=
'0'
;
end
if
;
rddata_reg
(
1
)
<=
'0'
;
rddata_reg
(
0
)
<=
'0'
;
rddata_reg
(
2
)
<=
wr_streamers_sscr1_snapshot_stats_int
;
rddata_reg
(
1
)
<=
'0'
;
rddata_reg
(
3
)
<=
regs_i
.
sscr1_rx_latency_acc_overflow_i
;
rddata_reg
(
2
)
<=
wr_streamers_sscr1_snapshot_stats_int
;
rddata_reg
(
31
downto
4
)
<=
regs_i
.
sscr1_rst_ts_cyc_i
;
rddata_reg
(
3
)
<=
regs_i
.
sscr1_rx_latency_acc_overflow_i
;
ack_sreg
(
2
)
<=
'1'
;
rddata_reg
(
31
downto
4
)
<=
regs_i
.
sscr1_rst_ts_cyc_i
;
ack_in_progress
<=
'1'
;
ack_sreg
(
2
)
<=
'1'
;
when
"000010"
=>
ack_in_progress
<=
'1'
;
if
(
wb_we_i
=
'1'
)
then
when
"000010"
=>
end
if
;
if
(
wb_we_i
=
'1'
)
then
rddata_reg
(
31
downto
0
)
<=
regs_i
.
sscr2_rst_ts_tai_lsb_i
;
end
if
;
ack_sreg
(
0
)
<=
'1'
;
rddata_reg
(
31
downto
0
)
<=
regs_i
.
sscr2_rst_ts_tai_lsb_i
;
ack_in_progress
<=
'1'
;
ack_sreg
(
0
)
<=
'1'
;
when
"000011"
=>
ack_in_progress
<=
'1'
;
if
(
wb_we_i
=
'1'
)
then
when
"000011"
=>
end
if
;
if
(
wb_we_i
=
'1'
)
then
rddata_reg
(
7
downto
0
)
<=
regs_i
.
sscr3_rst_ts_tai_msb_i
;
end
if
;
rddata_reg
(
8
)
<=
'X'
;
rddata_reg
(
7
downto
0
)
<=
regs_i
.
sscr3_rst_ts_tai_msb_i
;
rddata_reg
(
9
)
<=
'X'
;
rddata_reg
(
8
)
<=
'X'
;
rddata_reg
(
10
)
<=
'X'
;
rddata_reg
(
9
)
<=
'X'
;
rddata_reg
(
11
)
<=
'X'
;
rddata_reg
(
10
)
<=
'X'
;
rddata_reg
(
12
)
<=
'X'
;
rddata_reg
(
11
)
<=
'X'
;
rddata_reg
(
13
)
<=
'X'
;
rddata_reg
(
12
)
<=
'X'
;
rddata_reg
(
14
)
<=
'X'
;
rddata_reg
(
13
)
<=
'X'
;
rddata_reg
(
15
)
<=
'X'
;
rddata_reg
(
14
)
<=
'X'
;
rddata_reg
(
16
)
<=
'X'
;
rddata_reg
(
15
)
<=
'X'
;
rddata_reg
(
17
)
<=
'X'
;
rddata_reg
(
16
)
<=
'X'
;
rddata_reg
(
18
)
<=
'X'
;
rddata_reg
(
17
)
<=
'X'
;
rddata_reg
(
19
)
<=
'X'
;
rddata_reg
(
18
)
<=
'X'
;
rddata_reg
(
20
)
<=
'X'
;
rddata_reg
(
19
)
<=
'X'
;
rddata_reg
(
21
)
<=
'X'
;
rddata_reg
(
20
)
<=
'X'
;
rddata_reg
(
22
)
<=
'X'
;
rddata_reg
(
21
)
<=
'X'
;
rddata_reg
(
23
)
<=
'X'
;
rddata_reg
(
22
)
<=
'X'
;
rddata_reg
(
24
)
<=
'X'
;
rddata_reg
(
23
)
<=
'X'
;
rddata_reg
(
25
)
<=
'X'
;
rddata_reg
(
24
)
<=
'X'
;
rddata_reg
(
26
)
<=
'X'
;
rddata_reg
(
25
)
<=
'X'
;
rddata_reg
(
27
)
<=
'X'
;
rddata_reg
(
26
)
<=
'X'
;
rddata_reg
(
28
)
<=
'X'
;
rddata_reg
(
27
)
<=
'X'
;
rddata_reg
(
29
)
<=
'X'
;
rddata_reg
(
28
)
<=
'X'
;
rddata_reg
(
30
)
<=
'X'
;
rddata_reg
(
29
)
<=
'X'
;
rddata_reg
(
31
)
<=
'X'
;
rddata_reg
(
30
)
<=
'X'
;
ack_sreg
(
0
)
<=
'1'
;
rddata_reg
(
31
)
<=
'X'
;
ack_in_progress
<=
'1'
;
ack_sreg
(
0
)
<=
'1'
;
when
"000100"
=>
ack_in_progress
<=
'1'
;
if
(
wb_we_i
=
'1'
)
then
when
"000100"
=>
end
if
;
if
(
wb_we_i
=
'1'
)
then
rddata_reg
(
27
downto
0
)
<=
regs_i
.
rx_stat0_rx_latency_max_i
;
end
if
;
rddata_reg
(
28
)
<=
'X'
;
rddata_reg
(
27
downto
0
)
<=
regs_i
.
rx_stat0_rx_latency_max_i
;
rddata_reg
(
29
)
<=
'X'
;
rddata_reg
(
28
)
<=
'X'
;
rddata_reg
(
30
)
<=
'X'
;
rddata_reg
(
29
)
<=
'X'
;
rddata_reg
(
31
)
<=
'X'
;
rddata_reg
(
30
)
<=
'X'
;
ack_sreg
(
0
)
<=
'1'
;
rddata_reg
(
31
)
<=
'X'
;
ack_in_progress
<=
'1'
;
ack_sreg
(
0
)
<=
'1'
;
when
"000101"
=>
ack_in_progress
<=
'1'
;
if
(
wb_we_i
=
'1'
)
then
when
"000101"
=>
end
if
;
if
(
wb_we_i
=
'1'
)
then
rddata_reg
(
27
downto
0
)
<=
regs_i
.
rx_stat1_rx_latency_min_i
;
end
if
;
rddata_reg
(
28
)
<=
'X'
;
rddata_reg
(
27
downto
0
)
<=
regs_i
.
rx_stat1_rx_latency_min_i
;
rddata_reg
(
29
)
<=
'X'
;
rddata_reg
(
28
)
<=
'X'
;
rddata_reg
(
30
)
<=
'X'
;
rddata_reg
(
29
)
<=
'X'
;
rddata_reg
(
31
)
<=
'X'
;
rddata_reg
(
30
)
<=
'X'
;
ack_sreg
(
0
)
<=
'1'
;
rddata_reg
(
31
)
<=
'X'
;
ack_in_progress
<=
'1'
;
ack_sreg
(
0
)
<=
'1'
;
when
"000110"
=>
ack_in_progress
<=
'1'
;
if
(
wb_we_i
=
'1'
)
then
when
"000110"
=>
end
if
;
if
(
wb_we_i
=
'1'
)
then
rddata_reg
(
31
downto
0
)
<=
regs_i
.
tx_stat2_tx_sent_cnt_lsb_i
;
end
if
;
ack_sreg
(
0
)
<=
'1'
;
rddata_reg
(
31
downto
0
)
<=
regs_i
.
tx_stat2_tx_sent_cnt_lsb_i
;
ack_in_progress
<=
'1'
;
ack_sreg
(
0
)
<=
'1'
;
when
"000111"
=>
ack_in_progress
<=
'1'
;
if
(
wb_we_i
=
'1'
)
then
when
"000111"
=>
end
if
;
if
(
wb_we_i
=
'1'
)
then
rddata_reg
(
31
downto
0
)
<=
regs_i
.
tx_stat3_tx_sent_cnt_msb_i
;
end
if
;
ack_sreg
(
0
)
<=
'1'
;
rddata_reg
(
31
downto
0
)
<=
regs_i
.
tx_stat3_tx_sent_cnt_msb_i
;
ack_in_progress
<=
'1'
;
ack_sreg
(
0
)
<=
'1'
;
when
"001000"
=>
ack_in_progress
<=
'1'
;
if
(
wb_we_i
=
'1'
)
then
when
"001000"
=>
end
if
;
if
(
wb_we_i
=
'1'
)
then
rddata_reg
(
31
downto
0
)
<=
regs_i
.
rx_stat4_rx_rcvd_cnt_lsb_i
;
end
if
;
ack_sreg
(
0
)
<=
'1'
;
rddata_reg
(
31
downto
0
)
<=
regs_i
.
rx_stat4_rx_rcvd_cnt_lsb_i
;
ack_in_progress
<=
'1'
;
ack_sreg
(
0
)
<=
'1'
;
when
"001001"
=>
ack_in_progress
<=
'1'
;
if
(
wb_we_i
=
'1'
)
then
when
"001001"
=>
end
if
;
if
(
wb_we_i
=
'1'
)
then
rddata_reg
(
31
downto
0
)
<=
regs_i
.
rx_stat5_rx_rcvd_cnt_msb_i
;
end
if
;
ack_sreg
(
0
)
<=
'1'
;
rddata_reg
(
31
downto
0
)
<=
regs_i
.
rx_stat5_rx_rcvd_cnt_msb_i
;
ack_in_progress
<=
'1'
;
ack_sreg
(
0
)
<=
'1'
;
when
"001010"
=>
ack_in_progress
<=
'1'
;
if
(
wb_we_i
=
'1'
)
then
when
"001010"
=>
end
if
;
if
(
wb_we_i
=
'1'
)
then
rddata_reg
(
31
downto
0
)
<=
regs_i
.
rx_stat6_rx_loss_cnt_lsb_i
;
end
if
;
ack_sreg
(
0
)
<=
'1'
;
rddata_reg
(
31
downto
0
)
<=
regs_i
.
rx_stat6_rx_loss_cnt_lsb_i
;
ack_in_progress
<=
'1'
;
ack_sreg
(
0
)
<=
'1'
;
when
"001011"
=>
ack_in_progress
<=
'1'
;
if
(
wb_we_i
=
'1'
)
then
when
"001011"
=>
end
if
;
if
(
wb_we_i
=
'1'
)
then
rddata_reg
(
31
downto
0
)
<=
regs_i
.
rx_stat7_rx_loss_cnt_msb_i
;
end
if
;
ack_sreg
(
0
)
<=
'1'
;
rddata_reg
(
31
downto
0
)
<=
regs_i
.
rx_stat7_rx_loss_cnt_msb_i
;
ack_in_progress
<=
'1'
;
ack_sreg
(
0
)
<=
'1'
;
when
"001100"
=>
ack_in_progress
<=
'1'
;
if
(
wb_we_i
=
'1'
)
then
when
"001100"
=>
end
if
;
if
(
wb_we_i
=
'1'
)
then
rddata_reg
(
31
downto
0
)
<=
regs_i
.
rx_stat8_rx_lost_block_cnt_lsb_i
;
end
if
;
ack_sreg
(
0
)
<=
'1'
;
rddata_reg
(
31
downto
0
)
<=
regs_i
.
rx_stat8_rx_lost_block_cnt_lsb_i
;
ack_in_progress
<=
'1'
;
ack_sreg
(
0
)
<=
'1'
;
when
"001101"
=>
ack_in_progress
<=
'1'
;
if
(
wb_we_i
=
'1'
)
then
when
"001101"
=>
end
if
;
if
(
wb_we_i
=
'1'
)
then
rddata_reg
(
31
downto
0
)
<=
regs_i
.
rx_stat9_rx_lost_block_cnt_msb_i
;
end
if
;
ack_sreg
(
0
)
<=
'1'
;
rddata_reg
(
31
downto
0
)
<=
regs_i
.
rx_stat9_rx_lost_block_cnt_msb_i
;
ack_in_progress
<=
'1'
;
ack_sreg
(
0
)
<=
'1'
;
when
"001110"
=>
ack_in_progress
<=
'1'
;
if
(
wb_we_i
=
'1'
)
then
when
"001110"
=>
end
if
;
if
(
wb_we_i
=
'1'
)
then
rddata_reg
(
31
downto
0
)
<=
regs_i
.
rx_stat10_rx_latency_acc_lsb_i
;
end
if
;
ack_sreg
(
0
)
<=
'1'
;
rddata_reg
(
31
downto
0
)
<=
regs_i
.
rx_stat10_rx_latency_acc_lsb_i
;
ack_in_progress
<=
'1'
;
ack_sreg
(
0
)
<=
'1'
;
when
"001111"
=>
ack_in_progress
<=
'1'
;
if
(
wb_we_i
=
'1'
)
then
when
"001111"
=>
end
if
;
if
(
wb_we_i
=
'1'
)
then
rddata_reg
(
31
downto
0
)
<=
regs_i
.
rx_stat11_rx_latency_acc_msb_i
;
end
if
;
ack_sreg
(
0
)
<=
'1'
;
rddata_reg
(
31
downto
0
)
<=
regs_i
.
rx_stat11_rx_latency_acc_msb_i
;
ack_in_progress
<=
'1'
;
ack_sreg
(
0
)
<=
'1'
;
when
"010000"
=>
ack_in_progress
<=
'1'
;
if
(
wb_we_i
=
'1'
)
then
when
"010000"
=>
end
if
;
if
(
wb_we_i
=
'1'
)
then
rddata_reg
(
31
downto
0
)
<=
regs_i
.
rx_stat12_rx_latency_acc_cnt_lsb_i
;
end
if
;
ack_sreg
(
0
)
<=
'1'
;
rddata_reg
(
31
downto
0
)
<=
regs_i
.
rx_stat12_rx_latency_acc_cnt_lsb_i
;
ack_in_progress
<=
'1'
;
ack_sreg
(
0
)
<=
'1'
;
when
"010001"
=>
ack_in_progress
<=
'1'
;
if
(
wb_we_i
=
'1'
)
then
when
"010001"
=>
end
if
;
if
(
wb_we_i
=
'1'
)
then
rddata_reg
(
31
downto
0
)
<=
regs_i
.
rx_stat13_rx_latency_acc_cnt_msb_i
;
end
if
;
ack_sreg
(
0
)
<=
'1'
;
rddata_reg
(
31
downto
0
)
<=
regs_i
.
rx_stat13_rx_latency_acc_cnt_msb_i
;
ack_in_progress
<=
'1'
;
ack_sreg
(
0
)
<=
'1'
;
when
"010010"
=>
ack_in_progress
<=
'1'
;
if
(
wb_we_i
=
'1'
)
then
when
"010010"
=>
wr_streamers_tx_cfg0_ethertype_int
<=
wrdata_reg
(
15
downto
0
);
if
(
wb_we_i
=
'1'
)
then
end
if
;
wr_streamers_tx_cfg0_ethertype_int
<=
wrdata_reg
(
15
downto
0
);
rddata_reg
(
15
downto
0
)
<=
wr_streamers_tx_cfg0_ethertype_int
;
end
if
;
rddata_reg
(
16
)
<=
'X'
;
rddata_reg
(
15
downto
0
)
<=
wr_streamers_tx_cfg0_ethertype_int
;
rddata_reg
(
17
)
<=
'X'
;
rddata_reg
(
16
)
<=
'X'
;
rddata_reg
(
18
)
<=
'X'
;
rddata_reg
(
17
)
<=
'X'
;
rddata_reg
(
19
)
<=
'X'
;
rddata_reg
(
18
)
<=
'X'
;
rddata_reg
(
20
)
<=
'X'
;
rddata_reg
(
19
)
<=
'X'
;
rddata_reg
(
21
)
<=
'X'
;
rddata_reg
(
20
)
<=
'X'
;
rddata_reg
(
22
)
<=
'X'
;
rddata_reg
(
21
)
<=
'X'
;
rddata_reg
(
23
)
<=
'X'
;
rddata_reg
(
22
)
<=
'X'
;
rddata_reg
(
24
)
<=
'X'
;
rddata_reg
(
23
)
<=
'X'
;
rddata_reg
(
25
)
<=
'X'
;
rddata_reg
(
24
)
<=
'X'
;
rddata_reg
(
26
)
<=
'X'
;
rddata_reg
(
25
)
<=
'X'
;
rddata_reg
(
27
)
<=
'X'
;
rddata_reg
(
26
)
<=
'X'
;
rddata_reg
(
28
)
<=
'X'
;
rddata_reg
(
27
)
<=
'X'
;
rddata_reg
(
29
)
<=
'X'
;
rddata_reg
(
28
)
<=
'X'
;
rddata_reg
(
30
)
<=
'X'
;
rddata_reg
(
29
)
<=
'X'
;
rddata_reg
(
31
)
<=
'X'
;
rddata_reg
(
30
)
<=
'X'
;
ack_sreg
(
0
)
<=
'1'
;
rddata_reg
(
31
)
<=
'X'
;
ack_in_progress
<=
'1'
;
ack_sreg
(
0
)
<=
'1'
;
when
"010011"
=>
ack_in_progress
<=
'1'
;
if
(
wb_we_i
=
'1'
)
then
when
"010011"
=>
wr_streamers_tx_cfg1_mac_local_lsb_int
<=
wrdata_reg
(
31
downto
0
);
if
(
wb_we_i
=
'1'
)
then
end
if
;
wr_streamers_tx_cfg1_mac_local_lsb_int
<=
wrdata_reg
(
31
downto
0
);
rddata_reg
(
31
downto
0
)
<=
wr_streamers_tx_cfg1_mac_local_lsb_int
;
end
if
;
ack_sreg
(
0
)
<=
'1'
;
rddata_reg
(
31
downto
0
)
<=
wr_streamers_tx_cfg1_mac_local_lsb_int
;
ack_in_progress
<=
'1'
;
ack_sreg
(
0
)
<=
'1'
;
when
"010100"
=>
ack_in_progress
<=
'1'
;
if
(
wb_we_i
=
'1'
)
then
when
"010100"
=>
wr_streamers_tx_cfg2_mac_local_msb_int
<=
wrdata_reg
(
15
downto
0
);
if
(
wb_we_i
=
'1'
)
then
end
if
;
wr_streamers_tx_cfg2_mac_local_msb_int
<=
wrdata_reg
(
15
downto
0
);
rddata_reg
(
15
downto
0
)
<=
wr_streamers_tx_cfg2_mac_local_msb_int
;
end
if
;
rddata_reg
(
16
)
<=
'X'
;
rddata_reg
(
15
downto
0
)
<=
wr_streamers_tx_cfg2_mac_local_msb_int
;
rddata_reg
(
17
)
<=
'X'
;
rddata_reg
(
16
)
<=
'X'
;
rddata_reg
(
18
)
<=
'X'
;
rddata_reg
(
17
)
<=
'X'
;
rddata_reg
(
19
)
<=
'X'
;
rddata_reg
(
18
)
<=
'X'
;
rddata_reg
(
20
)
<=
'X'
;
rddata_reg
(
19
)
<=
'X'
;
rddata_reg
(
21
)
<=
'X'
;
rddata_reg
(
20
)
<=
'X'
;
rddata_reg
(
22
)
<=
'X'
;
rddata_reg
(
21
)
<=
'X'
;
rddata_reg
(
23
)
<=
'X'
;
rddata_reg
(
22
)
<=
'X'
;
rddata_reg
(
24
)
<=
'X'
;
rddata_reg
(
23
)
<=
'X'
;
rddata_reg
(
25
)
<=
'X'
;
rddata_reg
(
24
)
<=
'X'
;
rddata_reg
(
26
)
<=
'X'
;
rddata_reg
(
25
)
<=
'X'
;
rddata_reg
(
27
)
<=
'X'
;
rddata_reg
(
26
)
<=
'X'
;
rddata_reg
(
28
)
<=
'X'
;
rddata_reg
(
27
)
<=
'X'
;
rddata_reg
(
29
)
<=
'X'
;
rddata_reg
(
28
)
<=
'X'
;
rddata_reg
(
30
)
<=
'X'
;
rddata_reg
(
29
)
<=
'X'
;
rddata_reg
(
31
)
<=
'X'
;
rddata_reg
(
30
)
<=
'X'
;
ack_sreg
(
0
)
<=
'1'
;
rddata_reg
(
31
)
<=
'X'
;
ack_in_progress
<=
'1'
;
ack_sreg
(
0
)
<=
'1'
;
when
"010101"
=>
ack_in_progress
<=
'1'
;
if
(
wb_we_i
=
'1'
)
then
when
"010101"
=>
wr_streamers_tx_cfg3_mac_target_lsb_int
<=
wrdata_reg
(
31
downto
0
);
if
(
wb_we_i
=
'1'
)
then
end
if
;
wr_streamers_tx_cfg3_mac_target_lsb_int
<=
wrdata_reg
(
31
downto
0
);
rddata_reg
(
31
downto
0
)
<=
wr_streamers_tx_cfg3_mac_target_lsb_int
;
end
if
;
ack_sreg
(
0
)
<=
'1'
;
rddata_reg
(
31
downto
0
)
<=
wr_streamers_tx_cfg3_mac_target_lsb_int
;
ack_in_progress
<=
'1'
;
ack_sreg
(
0
)
<=
'1'
;
when
"010110"
=>
ack_in_progress
<=
'1'
;
if
(
wb_we_i
=
'1'
)
then
when
"010110"
=>
wr_streamers_tx_cfg4_mac_target_msb_int
<=
wrdata_reg
(
15
downto
0
);
if
(
wb_we_i
=
'1'
)
then
end
if
;
wr_streamers_tx_cfg4_mac_target_msb_int
<=
wrdata_reg
(
15
downto
0
);
rddata_reg
(
15
downto
0
)
<=
wr_streamers_tx_cfg4_mac_target_msb_int
;
end
if
;
rddata_reg
(
16
)
<=
'X'
;
rddata_reg
(
15
downto
0
)
<=
wr_streamers_tx_cfg4_mac_target_msb_int
;
rddata_reg
(
17
)
<=
'X'
;
rddata_reg
(
16
)
<=
'X'
;
rddata_reg
(
18
)
<=
'X'
;
rddata_reg
(
17
)
<=
'X'
;
rddata_reg
(
19
)
<=
'X'
;
rddata_reg
(
18
)
<=
'X'
;
rddata_reg
(
20
)
<=
'X'
;
rddata_reg
(
19
)
<=
'X'
;
rddata_reg
(
21
)
<=
'X'
;
rddata_reg
(
20
)
<=
'X'
;
rddata_reg
(
22
)
<=
'X'
;
rddata_reg
(
21
)
<=
'X'
;
rddata_reg
(
23
)
<=
'X'
;
rddata_reg
(
22
)
<=
'X'
;
rddata_reg
(
24
)
<=
'X'
;
rddata_reg
(
23
)
<=
'X'
;
rddata_reg
(
25
)
<=
'X'
;
rddata_reg
(
24
)
<=
'X'
;
rddata_reg
(
26
)
<=
'X'
;
rddata_reg
(
25
)
<=
'X'
;
rddata_reg
(
27
)
<=
'X'
;
rddata_reg
(
26
)
<=
'X'
;
rddata_reg
(
28
)
<=
'X'
;
rddata_reg
(
27
)
<=
'X'
;
rddata_reg
(
29
)
<=
'X'
;
rddata_reg
(
28
)
<=
'X'
;
rddata_reg
(
30
)
<=
'X'
;
rddata_reg
(
29
)
<=
'X'
;
rddata_reg
(
31
)
<=
'X'
;
rddata_reg
(
30
)
<=
'X'
;
ack_sreg
(
0
)
<=
'1'
;
rddata_reg
(
31
)
<=
'X'
;
ack_in_progress
<=
'1'
;
ack_sreg
(
0
)
<=
'1'
;
when
"010111"
=>
ack_in_progress
<=
'1'
;
if
(
wb_we_i
=
'1'
)
then
when
"010111"
=>
wr_streamers_tx_cfg5_qtag_ena_int
<=
wrdata_reg
(
0
);
if
(
wb_we_i
=
'1'
)
then
wr_streamers_tx_cfg5_qtag_vid_int
<=
wrdata_reg
(
19
downto
8
);
wr_streamers_tx_cfg5_qtag_ena_int
<=
wrdata_reg
(
0
);
wr_streamers_tx_cfg5_qtag_prio_int
<=
wrdata_reg
(
26
downto
24
);
wr_streamers_tx_cfg5_qtag_vid_int
<=
wrdata_reg
(
19
downto
8
);
end
if
;
wr_streamers_tx_cfg5_qtag_prio_int
<=
wrdata_reg
(
26
downto
24
);
rddata_reg
(
0
)
<=
wr_streamers_tx_cfg5_qtag_ena_int
;
end
if
;
rddata_reg
(
19
downto
8
)
<=
wr_streamers_tx_cfg5_qtag_vid_int
;
rddata_reg
(
0
)
<=
wr_streamers_tx_cfg5_qtag_ena_int
;
rddata_reg
(
26
downto
24
)
<=
wr_streamers_tx_cfg5_qtag_prio_int
;
rddata_reg
(
19
downto
8
)
<=
wr_streamers_tx_cfg5_qtag_vid_int
;
rddata_reg
(
1
)
<=
'X'
;
rddata_reg
(
26
downto
24
)
<=
wr_streamers_tx_cfg5_qtag_prio_int
;
rddata_reg
(
2
)
<=
'X'
;
rddata_reg
(
1
)
<=
'X'
;
rddata_reg
(
3
)
<=
'X'
;
rddata_reg
(
2
)
<=
'X'
;
rddata_reg
(
4
)
<=
'X'
;
rddata_reg
(
3
)
<=
'X'
;
rddata_reg
(
5
)
<=
'X'
;
rddata_reg
(
4
)
<=
'X'
;
rddata_reg
(
6
)
<=
'X'
;
rddata_reg
(
5
)
<=
'X'
;
rddata_reg
(
7
)
<=
'X'
;
rddata_reg
(
6
)
<=
'X'
;
rddata_reg
(
20
)
<=
'X'
;
rddata_reg
(
7
)
<=
'X'
;
rddata_reg
(
21
)
<=
'X'
;
rddata_reg
(
20
)
<=
'X'
;
rddata_reg
(
22
)
<=
'X'
;
rddata_reg
(
21
)
<=
'X'
;
rddata_reg
(
23
)
<=
'X'
;
rddata_reg
(
22
)
<=
'X'
;
rddata_reg
(
27
)
<=
'X'
;
rddata_reg
(
23
)
<=
'X'
;
rddata_reg
(
28
)
<=
'X'
;
rddata_reg
(
27
)
<=
'X'
;
rddata_reg
(
29
)
<=
'X'
;
rddata_reg
(
28
)
<=
'X'
;
rddata_reg
(
30
)
<=
'X'
;
rddata_reg
(
29
)
<=
'X'
;
rddata_reg
(
31
)
<=
'X'
;
rddata_reg
(
30
)
<=
'X'
;
ack_sreg
(
0
)
<=
'1'
;
rddata_reg
(
31
)
<=
'X'
;
ack_in_progress
<=
'1'
;
ack_sreg
(
0
)
<=
'1'
;
when
"011000"
=>
ack_in_progress
<=
'1'
;
if
(
wb_we_i
=
'1'
)
then
when
"011000"
=>
wr_streamers_rx_cfg0_ethertype_int
<=
wrdata_reg
(
15
downto
0
);
if
(
wb_we_i
=
'1'
)
then
wr_streamers_rx_cfg0_accept_broadcast_int
<=
wrdata_reg
(
16
);
wr_streamers_rx_cfg0_ethertype_int
<=
wrdata_reg
(
15
downto
0
);
wr_streamers_rx_cfg0_filter_remote_int
<=
wrdata_reg
(
17
);
wr_streamers_rx_cfg0_accept_broadcast_int
<=
wrdata_reg
(
16
);
end
if
;
wr_streamers_rx_cfg0_filter_remote_int
<=
wrdata_reg
(
17
);
rddata_reg
(
15
downto
0
)
<=
wr_streamers_rx_cfg0_ethertype_int
;
end
if
;
rddata_reg
(
16
)
<=
wr_streamers_rx_cfg0_accept_broadcast_int
;
rddata_reg
(
15
downto
0
)
<=
wr_streamers_rx_cfg0_ethertype_int
;
rddata_reg
(
17
)
<=
wr_streamers_rx_cfg0_filter_remote_int
;
rddata_reg
(
16
)
<=
wr_streamers_rx_cfg0_accept_broadcast_int
;
rddata_reg
(
18
)
<=
'X'
;
rddata_reg
(
17
)
<=
wr_streamers_rx_cfg0_filter_remote_int
;
rddata_reg
(
19
)
<=
'X'
;
rddata_reg
(
18
)
<=
'X'
;
rddata_reg
(
20
)
<=
'X'
;
rddata_reg
(
19
)
<=
'X'
;
rddata_reg
(
21
)
<=
'X'
;
rddata_reg
(
20
)
<=
'X'
;
rddata_reg
(
22
)
<=
'X'
;
rddata_reg
(
21
)
<=
'X'
;
rddata_reg
(
23
)
<=
'X'
;
rddata_reg
(
22
)
<=
'X'
;
rddata_reg
(
24
)
<=
'X'
;
rddata_reg
(
23
)
<=
'X'
;
rddata_reg
(
25
)
<=
'X'
;
rddata_reg
(
24
)
<=
'X'
;
rddata_reg
(
26
)
<=
'X'
;
rddata_reg
(
25
)
<=
'X'
;
rddata_reg
(
27
)
<=
'X'
;
rddata_reg
(
26
)
<=
'X'
;
rddata_reg
(
28
)
<=
'X'
;
rddata_reg
(
27
)
<=
'X'
;
rddata_reg
(
29
)
<=
'X'
;
rddata_reg
(
28
)
<=
'X'
;
rddata_reg
(
30
)
<=
'X'
;
rddata_reg
(
29
)
<=
'X'
;
rddata_reg
(
31
)
<=
'X'
;
rddata_reg
(
30
)
<=
'X'
;
ack_sreg
(
0
)
<=
'1'
;
rddata_reg
(
31
)
<=
'X'
;
ack_in_progress
<=
'1'
;
ack_sreg
(
0
)
<=
'1'
;
when
"011001"
=>
ack_in_progress
<=
'1'
;
if
(
wb_we_i
=
'1'
)
then
when
"011001"
=>
wr_streamers_rx_cfg1_mac_local_lsb_int
<=
wrdata_reg
(
31
downto
0
);
if
(
wb_we_i
=
'1'
)
then
end
if
;
wr_streamers_rx_cfg1_mac_local_lsb_int
<=
wrdata_reg
(
31
downto
0
);
rddata_reg
(
31
downto
0
)
<=
wr_streamers_rx_cfg1_mac_local_lsb_int
;
end
if
;
ack_sreg
(
0
)
<=
'1'
;
rddata_reg
(
31
downto
0
)
<=
wr_streamers_rx_cfg1_mac_local_lsb_int
;
ack_in_progress
<=
'1'
;
ack_sreg
(
0
)
<=
'1'
;
when
"011010"
=>
ack_in_progress
<=
'1'
;
if
(
wb_we_i
=
'1'
)
then
when
"011010"
=>
wr_streamers_rx_cfg2_mac_local_msb_int
<=
wrdata_reg
(
15
downto
0
);
if
(
wb_we_i
=
'1'
)
then
end
if
;
wr_streamers_rx_cfg2_mac_local_msb_int
<=
wrdata_reg
(
15
downto
0
);
rddata_reg
(
15
downto
0
)
<=
wr_streamers_rx_cfg2_mac_local_msb_int
;
end
if
;
rddata_reg
(
16
)
<=
'X'
;
rddata_reg
(
15
downto
0
)
<=
wr_streamers_rx_cfg2_mac_local_msb_int
;
rddata_reg
(
17
)
<=
'X'
;
rddata_reg
(
16
)
<=
'X'
;
rddata_reg
(
18
)
<=
'X'
;
rddata_reg
(
17
)
<=
'X'
;
rddata_reg
(
19
)
<=
'X'
;
rddata_reg
(
18
)
<=
'X'
;
rddata_reg
(
20
)
<=
'X'
;
rddata_reg
(
19
)
<=
'X'
;
rddata_reg
(
21
)
<=
'X'
;
rddata_reg
(
20
)
<=
'X'
;
rddata_reg
(
22
)
<=
'X'
;
rddata_reg
(
21
)
<=
'X'
;
rddata_reg
(
23
)
<=
'X'
;
rddata_reg
(
22
)
<=
'X'
;
rddata_reg
(
24
)
<=
'X'
;
rddata_reg
(
23
)
<=
'X'
;
rddata_reg
(
25
)
<=
'X'
;
rddata_reg
(
24
)
<=
'X'
;
rddata_reg
(
26
)
<=
'X'
;
rddata_reg
(
25
)
<=
'X'
;
rddata_reg
(
27
)
<=
'X'
;
rddata_reg
(
26
)
<=
'X'
;
rddata_reg
(
28
)
<=
'X'
;
rddata_reg
(
27
)
<=
'X'
;
rddata_reg
(
29
)
<=
'X'
;
rddata_reg
(
28
)
<=
'X'
;
rddata_reg
(
30
)
<=
'X'
;
rddata_reg
(
29
)
<=
'X'
;
rddata_reg
(
31
)
<=
'X'
;
rddata_reg
(
30
)
<=
'X'
;
ack_sreg
(
0
)
<=
'1'
;
rddata_reg
(
31
)
<=
'X'
;
ack_in_progress
<=
'1'
;
ack_sreg
(
0
)
<=
'1'
;
when
"011011"
=>
ack_in_progress
<=
'1'
;
if
(
wb_we_i
=
'1'
)
then
when
"011011"
=>
wr_streamers_rx_cfg3_mac_remote_lsb_int
<=
wrdata_reg
(
31
downto
0
);
if
(
wb_we_i
=
'1'
)
then
end
if
;
wr_streamers_rx_cfg3_mac_remote_lsb_int
<=
wrdata_reg
(
31
downto
0
);
rddata_reg
(
31
downto
0
)
<=
wr_streamers_rx_cfg3_mac_remote_lsb_int
;
end
if
;
ack_sreg
(
0
)
<=
'1'
;
rddata_reg
(
31
downto
0
)
<=
wr_streamers_rx_cfg3_mac_remote_lsb_int
;
ack_in_progress
<=
'1'
;
ack_sreg
(
0
)
<=
'1'
;
when
"011100"
=>
ack_in_progress
<=
'1'
;
if
(
wb_we_i
=
'1'
)
then
when
"011100"
=>
wr_streamers_rx_cfg4_mac_remote_msb_int
<=
wrdata_reg
(
15
downto
0
);
if
(
wb_we_i
=
'1'
)
then
end
if
;
wr_streamers_rx_cfg4_mac_remote_msb_int
<=
wrdata_reg
(
15
downto
0
);
rddata_reg
(
15
downto
0
)
<=
wr_streamers_rx_cfg4_mac_remote_msb_int
;
end
if
;
rddata_reg
(
16
)
<=
'X'
;
rddata_reg
(
15
downto
0
)
<=
wr_streamers_rx_cfg4_mac_remote_msb_int
;
rddata_reg
(
17
)
<=
'X'
;
rddata_reg
(
16
)
<=
'X'
;
rddata_reg
(
18
)
<=
'X'
;
rddata_reg
(
17
)
<=
'X'
;
rddata_reg
(
19
)
<=
'X'
;
rddata_reg
(
18
)
<=
'X'
;
rddata_reg
(
20
)
<=
'X'
;
rddata_reg
(
19
)
<=
'X'
;
rddata_reg
(
21
)
<=
'X'
;
rddata_reg
(
20
)
<=
'X'
;
rddata_reg
(
22
)
<=
'X'
;
rddata_reg
(
21
)
<=
'X'
;
rddata_reg
(
23
)
<=
'X'
;
rddata_reg
(
22
)
<=
'X'
;
rddata_reg
(
24
)
<=
'X'
;
rddata_reg
(
23
)
<=
'X'
;
rddata_reg
(
25
)
<=
'X'
;
rddata_reg
(
24
)
<=
'X'
;
rddata_reg
(
26
)
<=
'X'
;
rddata_reg
(
25
)
<=
'X'
;
rddata_reg
(
27
)
<=
'X'
;
rddata_reg
(
26
)
<=
'X'
;
rddata_reg
(
28
)
<=
'X'
;
rddata_reg
(
27
)
<=
'X'
;
rddata_reg
(
29
)
<=
'X'
;
rddata_reg
(
28
)
<=
'X'
;
rddata_reg
(
30
)
<=
'X'
;
rddata_reg
(
29
)
<=
'X'
;
rddata_reg
(
31
)
<=
'X'
;
rddata_reg
(
30
)
<=
'X'
;
ack_sreg
(
0
)
<=
'1'
;
rddata_reg
(
31
)
<=
'X'
;
ack_in_progress
<=
'1'
;
ack_sreg
(
0
)
<=
'1'
;
when
"011101"
=>
ack_in_progress
<=
'1'
;
if
(
wb_we_i
=
'1'
)
then
when
"011101"
=>
wr_streamers_rx_cfg5_fixed_latency_int
<=
wrdata_reg
(
27
downto
0
);
if
(
wb_we_i
=
'1'
)
then
end
if
;
wr_streamers_rx_cfg5_fixed_latency_int
<=
wrdata_reg
(
27
downto
0
);
rddata_reg
(
27
downto
0
)
<=
wr_streamers_rx_cfg5_fixed_latency_int
;
end
if
;
rddata_reg
(
28
)
<=
'X'
;
rddata_reg
(
27
downto
0
)
<=
wr_streamers_rx_cfg5_fixed_latency_int
;
rddata_reg
(
29
)
<=
'X'
;
rddata_reg
(
28
)
<=
'X'
;
rddata_reg
(
30
)
<=
'X'
;
rddata_reg
(
29
)
<=
'X'
;
rddata_reg
(
31
)
<=
'X'
;
rddata_reg
(
30
)
<=
'X'
;
ack_sreg
(
0
)
<=
'1'
;
rddata_reg
(
31
)
<=
'X'
;
ack_in_progress
<=
'1'
;
ack_sreg
(
0
)
<=
'1'
;
when
"011110"
=>
ack_in_progress
<=
'1'
;
if
(
wb_we_i
=
'1'
)
then
when
"011110"
=>
wr_streamers_cfg_or_tx_ethtype_int
<=
wrdata_reg
(
0
);
if
(
wb_we_i
=
'1'
)
then
wr_streamers_cfg_or_tx_mac_loc_int
<=
wrdata_reg
(
1
);
wr_streamers_cfg_or_tx_ethtype_int
<=
wrdata_reg
(
0
);
wr_streamers_cfg_or_tx_mac_tar_int
<=
wrdata_reg
(
2
);
wr_streamers_cfg_or_tx_mac_loc_int
<=
wrdata_reg
(
1
);
wr_streamers_cfg_or_tx_qtag_int
<=
wrdata_reg
(
3
);
wr_streamers_cfg_or_tx_mac_tar_int
<=
wrdata_reg
(
2
);
wr_streamers_cfg_or_rx_ethertype_int
<=
wrdata_reg
(
16
);
wr_streamers_cfg_or_tx_qtag_int
<=
wrdata_reg
(
3
);
wr_streamers_cfg_or_rx_mac_loc_int
<=
wrdata_reg
(
17
);
wr_streamers_cfg_or_rx_ethertype_int
<=
wrdata_reg
(
16
);
wr_streamers_cfg_or_rx_mac_rem_int
<=
wrdata_reg
(
18
);
wr_streamers_cfg_or_rx_mac_loc_int
<=
wrdata_reg
(
17
);
wr_streamers_cfg_or_rx_acc_broadcast_int
<=
wrdata_reg
(
19
);
wr_streamers_cfg_or_rx_mac_rem_int
<=
wrdata_reg
(
18
);
wr_streamers_cfg_or_rx_ftr_remote_int
<=
wrdata_reg
(
20
);
wr_streamers_cfg_or_rx_acc_broadcast_int
<=
wrdata_reg
(
19
);
wr_streamers_cfg_or_rx_fix_lat_int
<=
wrdata_reg
(
21
);
wr_streamers_cfg_or_rx_ftr_remote_int
<=
wrdata_reg
(
20
);
end
if
;
wr_streamers_cfg_or_rx_fix_lat_int
<=
wrdata_reg
(
21
);
rddata_reg
(
0
)
<=
wr_streamers_cfg_or_tx_ethtype_int
;
end
if
;
rddata_reg
(
1
)
<=
wr_streamers_cfg_or_tx_mac_loc_int
;
rddata_reg
(
0
)
<=
wr_streamers_cfg_or_tx_ethtype_int
;
rddata_reg
(
2
)
<=
wr_streamers_cfg_or_tx_mac_tar_int
;
rddata_reg
(
1
)
<=
wr_streamers_cfg_or_tx_mac_loc_int
;
rddata_reg
(
3
)
<=
wr_streamers_cfg_or_tx_qtag_int
;
rddata_reg
(
2
)
<=
wr_streamers_cfg_or_tx_mac_tar_int
;
rddata_reg
(
16
)
<=
wr_streamers_cfg_or_rx_ethertype_int
;
rddata_reg
(
3
)
<=
wr_streamers_cfg_or_tx_qtag_int
;
rddata_reg
(
17
)
<=
wr_streamers_cfg_or_rx_mac_loc_int
;
rddata_reg
(
16
)
<=
wr_streamers_cfg_or_rx_ethertype_int
;
rddata_reg
(
18
)
<=
wr_streamers_cfg_or_rx_mac_rem_int
;
rddata_reg
(
17
)
<=
wr_streamers_cfg_or_rx_mac_loc_int
;
rddata_reg
(
19
)
<=
wr_streamers_cfg_or_rx_acc_broadcast_int
;
rddata_reg
(
18
)
<=
wr_streamers_cfg_or_rx_mac_rem_int
;
rddata_reg
(
20
)
<=
wr_streamers_cfg_or_rx_ftr_remote_int
;
rddata_reg
(
19
)
<=
wr_streamers_cfg_or_rx_acc_broadcast_int
;
rddata_reg
(
21
)
<=
wr_streamers_cfg_or_rx_fix_lat_int
;
rddata_reg
(
20
)
<=
wr_streamers_cfg_or_rx_ftr_remote_int
;
rddata_reg
(
4
)
<=
'X'
;
rddata_reg
(
21
)
<=
wr_streamers_cfg_or_rx_fix_lat_int
;
rddata_reg
(
5
)
<=
'X'
;
rddata_reg
(
4
)
<=
'X'
;
rddata_reg
(
6
)
<=
'X'
;
rddata_reg
(
5
)
<=
'X'
;
rddata_reg
(
7
)
<=
'X'
;
rddata_reg
(
6
)
<=
'X'
;
rddata_reg
(
8
)
<=
'X'
;
rddata_reg
(
7
)
<=
'X'
;
rddata_reg
(
9
)
<=
'X'
;
rddata_reg
(
8
)
<=
'X'
;
rddata_reg
(
10
)
<=
'X'
;
rddata_reg
(
9
)
<=
'X'
;
rddata_reg
(
11
)
<=
'X'
;
rddata_reg
(
10
)
<=
'X'
;
rddata_reg
(
12
)
<=
'X'
;
rddata_reg
(
11
)
<=
'X'
;
rddata_reg
(
13
)
<=
'X'
;
rddata_reg
(
12
)
<=
'X'
;
rddata_reg
(
14
)
<=
'X'
;
rddata_reg
(
13
)
<=
'X'
;
rddata_reg
(
15
)
<=
'X'
;
rddata_reg
(
14
)
<=
'X'
;
rddata_reg
(
22
)
<=
'X'
;
rddata_reg
(
15
)
<=
'X'
;
rddata_reg
(
23
)
<=
'X'
;
rddata_reg
(
22
)
<=
'X'
;
rddata_reg
(
24
)
<=
'X'
;
rddata_reg
(
23
)
<=
'X'
;
rddata_reg
(
25
)
<=
'X'
;
rddata_reg
(
24
)
<=
'X'
;
rddata_reg
(
26
)
<=
'X'
;
rddata_reg
(
25
)
<=
'X'
;
rddata_reg
(
27
)
<=
'X'
;
rddata_reg
(
26
)
<=
'X'
;
rddata_reg
(
28
)
<=
'X'
;
rddata_reg
(
27
)
<=
'X'
;
rddata_reg
(
29
)
<=
'X'
;
rddata_reg
(
28
)
<=
'X'
;
rddata_reg
(
30
)
<=
'X'
;
rddata_reg
(
29
)
<=
'X'
;
rddata_reg
(
31
)
<=
'X'
;
rddata_reg
(
30
)
<=
'X'
;
ack_sreg
(
0
)
<=
'1'
;
rddata_reg
(
31
)
<=
'X'
;
ack_in_progress
<=
'1'
;
ack_sreg
(
0
)
<=
'1'
;
when
"011111"
=>
ack_in_progress
<=
'1'
;
if
(
wb_we_i
=
'1'
)
then
when
"011111"
=>
wr_streamers_dbg_ctrl_mux_int
<=
wrdata_reg
(
0
);
if
(
wb_we_i
=
'1'
)
then
wr_streamers_dbg_ctrl_start_byte_int
<=
wrdata_reg
(
15
downto
8
);
wr_streamers_dbg_ctrl_mux_int
<=
wrdata_reg
(
0
);
end
if
;
wr_streamers_dbg_ctrl_start_byte_int
<=
wrdata_reg
(
15
downto
8
);
rddata_reg
(
0
)
<=
wr_streamers_dbg_ctrl_mux_int
;
end
if
;
rddata_reg
(
15
downto
8
)
<=
wr_streamers_dbg_ctrl_start_byte_int
;
rddata_reg
(
0
)
<=
wr_streamers_dbg_ctrl_mux_int
;
rddata_reg
(
1
)
<=
'X'
;
rddata_reg
(
15
downto
8
)
<=
wr_streamers_dbg_ctrl_start_byte_int
;
rddata_reg
(
2
)
<=
'X'
;
rddata_reg
(
1
)
<=
'X'
;
rddata_reg
(
3
)
<=
'X'
;
rddata_reg
(
2
)
<=
'X'
;
rddata_reg
(
4
)
<=
'X'
;
rddata_reg
(
3
)
<=
'X'
;
rddata_reg
(
5
)
<=
'X'
;
rddata_reg
(
4
)
<=
'X'
;
rddata_reg
(
6
)
<=
'X'
;
rddata_reg
(
5
)
<=
'X'
;
rddata_reg
(
7
)
<=
'X'
;
rddata_reg
(
6
)
<=
'X'
;
rddata_reg
(
16
)
<=
'X'
;
rddata_reg
(
7
)
<=
'X'
;
rddata_reg
(
17
)
<=
'X'
;
rddata_reg
(
16
)
<=
'X'
;
rddata_reg
(
18
)
<=
'X'
;
rddata_reg
(
17
)
<=
'X'
;
rddata_reg
(
19
)
<=
'X'
;
rddata_reg
(
18
)
<=
'X'
;
rddata_reg
(
20
)
<=
'X'
;
rddata_reg
(
19
)
<=
'X'
;
rddata_reg
(
21
)
<=
'X'
;
rddata_reg
(
20
)
<=
'X'
;
rddata_reg
(
22
)
<=
'X'
;
rddata_reg
(
21
)
<=
'X'
;
rddata_reg
(
23
)
<=
'X'
;
rddata_reg
(
22
)
<=
'X'
;
rddata_reg
(
24
)
<=
'X'
;
rddata_reg
(
23
)
<=
'X'
;
rddata_reg
(
25
)
<=
'X'
;
rddata_reg
(
24
)
<=
'X'
;
rddata_reg
(
26
)
<=
'X'
;
rddata_reg
(
25
)
<=
'X'
;
rddata_reg
(
27
)
<=
'X'
;
rddata_reg
(
26
)
<=
'X'
;
rddata_reg
(
28
)
<=
'X'
;
rddata_reg
(
27
)
<=
'X'
;
rddata_reg
(
29
)
<=
'X'
;
rddata_reg
(
28
)
<=
'X'
;
rddata_reg
(
30
)
<=
'X'
;
rddata_reg
(
29
)
<=
'X'
;
rddata_reg
(
31
)
<=
'X'
;
rddata_reg
(
30
)
<=
'X'
;
ack_sreg
(
0
)
<=
'1'
;
rddata_reg
(
31
)
<=
'X'
;
ack_in_progress
<=
'1'
;
ack_sreg
(
0
)
<=
'1'
;
when
"100000"
=>
ack_in_progress
<=
'1'
;
if
(
wb_we_i
=
'1'
)
then
when
"100000"
=>
end
if
;
if
(
wb_we_i
=
'1'
)
then
rddata_reg
(
31
downto
0
)
<=
regs_i
.
dbg_data_i
;
end
if
;
ack_sreg
(
0
)
<=
'1'
;
rddata_reg
(
31
downto
0
)
<=
regs_i
.
dbg_data_i
;
ack_in_progress
<=
'1'
;
ack_sreg
(
0
)
<=
'1'
;
when
"100001"
=>
ack_in_progress
<=
'1'
;
if
(
wb_we_i
=
'1'
)
then
when
"100001"
=>
end
if
;
if
(
wb_we_i
=
'1'
)
then
rddata_reg
(
31
downto
0
)
<=
regs_i
.
dummy_dummy_i
;
end
if
;
ack_sreg
(
0
)
<=
'1'
;
rddata_reg
(
31
downto
0
)
<=
regs_i
.
dummy_dummy_i
;
ack_in_progress
<=
'1'
;
ack_sreg
(
0
)
<=
'1'
;
when
"100010"
=>
ack_in_progress
<=
'1'
;
if
(
wb_we_i
=
'1'
)
then
when
"100010"
=>
wr_streamers_rstr_rst_sw_int
<=
wrdata_reg
(
0
);
if
(
wb_we_i
=
'1'
)
then
end
if
;
wr_streamers_rstr_rst_sw_int
<=
wrdata_reg
(
0
);
rddata_reg
(
0
)
<=
'0'
;
end
if
;
rddata_reg
(
0
)
<=
'X'
;
rddata_reg
(
0
)
<=
'0'
;
rddata_reg
(
1
)
<=
'X'
;
rddata_reg
(
0
)
<=
'X'
;
rddata_reg
(
2
)
<=
'X'
;
rddata_reg
(
1
)
<=
'X'
;
rddata_reg
(
3
)
<=
'X'
;
rddata_reg
(
2
)
<=
'X'
;
rddata_reg
(
4
)
<=
'X'
;
rddata_reg
(
3
)
<=
'X'
;
rddata_reg
(
5
)
<=
'X'
;
rddata_reg
(
4
)
<=
'X'
;
rddata_reg
(
6
)
<=
'X'
;
rddata_reg
(
5
)
<=
'X'
;
rddata_reg
(
7
)
<=
'X'
;
rddata_reg
(
6
)
<=
'X'
;
rddata_reg
(
8
)
<=
'X'
;
rddata_reg
(
7
)
<=
'X'
;
rddata_reg
(
9
)
<=
'X'
;
rddata_reg
(
8
)
<=
'X'
;
rddata_reg
(
10
)
<=
'X'
;
rddata_reg
(
9
)
<=
'X'
;
rddata_reg
(
11
)
<=
'X'
;
rddata_reg
(
10
)
<=
'X'
;
rddata_reg
(
12
)
<=
'X'
;
rddata_reg
(
11
)
<=
'X'
;
rddata_reg
(
13
)
<=
'X'
;
rddata_reg
(
12
)
<=
'X'
;
rddata_reg
(
14
)
<=
'X'
;
rddata_reg
(
13
)
<=
'X'
;
rddata_reg
(
15
)
<=
'X'
;
rddata_reg
(
14
)
<=
'X'
;
rddata_reg
(
16
)
<=
'X'
;
rddata_reg
(
15
)
<=
'X'
;
rddata_reg
(
17
)
<=
'X'
;
rddata_reg
(
16
)
<=
'X'
;
rddata_reg
(
18
)
<=
'X'
;
rddata_reg
(
17
)
<=
'X'
;
rddata_reg
(
19
)
<=
'X'
;
rddata_reg
(
18
)
<=
'X'
;
rddata_reg
(
20
)
<=
'X'
;
rddata_reg
(
19
)
<=
'X'
;
rddata_reg
(
21
)
<=
'X'
;
rddata_reg
(
20
)
<=
'X'
;
rddata_reg
(
22
)
<=
'X'
;
rddata_reg
(
21
)
<=
'X'
;
rddata_reg
(
23
)
<=
'X'
;
rddata_reg
(
22
)
<=
'X'
;
rddata_reg
(
24
)
<=
'X'
;
rddata_reg
(
23
)
<=
'X'
;
rddata_reg
(
25
)
<=
'X'
;
rddata_reg
(
24
)
<=
'X'
;
rddata_reg
(
26
)
<=
'X'
;
rddata_reg
(
25
)
<=
'X'
;
rddata_reg
(
27
)
<=
'X'
;
rddata_reg
(
26
)
<=
'X'
;
rddata_reg
(
28
)
<=
'X'
;
rddata_reg
(
27
)
<=
'X'
;
rddata_reg
(
29
)
<=
'X'
;
rddata_reg
(
28
)
<=
'X'
;
rddata_reg
(
30
)
<=
'X'
;
rddata_reg
(
29
)
<=
'X'
;
rddata_reg
(
31
)
<=
'X'
;
rddata_reg
(
30
)
<=
'X'
;
ack_sreg
(
2
)
<=
'1'
;
rddata_reg
(
31
)
<=
'X'
;
ack_in_progress
<=
'1'
;
ack_sreg
(
2
)
<=
'1'
;
when
"100011"
=>
ack_in_progress
<=
'1'
;
if
(
wb_we_i
=
'1'
)
then
when
"100011"
=>
end
if
;
if
(
wb_we_i
=
'1'
)
then
rddata_reg
(
31
downto
0
)
<=
regs_i
.
rx_stat14_rx_buf_overflow_cnt_i
;
end
if
;
ack_sreg
(
0
)
<=
'1'
;
rddata_reg
(
31
downto
0
)
<=
regs_i
.
rx_stat14_rx_buf_overflow_cnt_i
;
ack_in_progress
<=
'1'
;
ack_sreg
(
0
)
<=
'1'
;
when
"100100"
=>
ack_in_progress
<=
'1'
;
if
(
wb_we_i
=
'1'
)
then
when
"100100"
=>
end
if
;
if
(
wb_we_i
=
'1'
)
then
rddata_reg
(
31
downto
0
)
<=
regs_i
.
rx_stat15_rx_late_frames_cnt_i
;
end
if
;
ack_sreg
(
0
)
<=
'1'
;
rddata_reg
(
31
downto
0
)
<=
regs_i
.
rx_stat15_rx_late_frames_cnt_i
;
ack_in_progress
<=
'1'
;
ack_sreg
(
0
)
<=
'1'
;
when
"100101"
=>
ack_in_progress
<=
'1'
;
if
(
wb_we_i
=
'1'
)
then
when
"100101"
=>
end
if
;
if
(
wb_we_i
=
'1'
)
then
rddata_reg
(
31
downto
0
)
<=
regs_i
.
rx_stat16_rx_timeout_frames_cnt_i
;
end
if
;
ack_sreg
(
0
)
<=
'1'
;
rddata_reg
(
31
downto
0
)
<=
regs_i
.
rx_stat16_rx_timeout_frames_cnt_i
;
ack_in_progress
<=
'1'
;
ack_sreg
(
0
)
<=
'1'
;
when
"100110"
=>
ack_in_progress
<=
'1'
;
if
(
wb_we_i
=
'1'
)
then
when
"100110"
=>
end
if
;
if
(
wb_we_i
=
'1'
)
then
rddata_reg
(
31
downto
0
)
<=
regs_i
.
rx_stat17_rx_match_frames_cnt_i
;
end
if
;
ack_sreg
(
0
)
<=
'1'
;
rddata_reg
(
31
downto
0
)
<=
regs_i
.
rx_stat17_rx_match_frames_cnt_i
;
ack_in_progress
<=
'1'
;
ack_sreg
(
0
)
<=
'1'
;
when
"100111"
=>
ack_in_progress
<=
'1'
;
if
(
wb_we_i
=
'1'
)
then
when
"100111"
=>
wr_streamers_rx_cfg6_rx_fixed_latency_timeout_int
<=
wrdata_reg
(
27
downto
0
);
if
(
wb_we_i
=
'1'
)
then
end
if
;
wr_streamers_rx_cfg6_rx_fixed_latency_timeout_int
<=
wrdata_reg
(
27
downto
0
);
rddata_reg
(
27
downto
0
)
<=
wr_streamers_rx_cfg6_rx_fixed_latency_timeout_int
;
end
if
;
rddata_reg
(
28
)
<=
'X'
;
rddata_reg
(
27
downto
0
)
<=
wr_streamers_rx_cfg6_rx_fixed_latency_timeout_int
;
rddata_reg
(
29
)
<=
'X'
;
rddata_reg
(
28
)
<=
'X'
;
rddata_reg
(
30
)
<=
'X'
;
rddata_reg
(
29
)
<=
'X'
;
rddata_reg
(
31
)
<=
'X'
;
rddata_reg
(
30
)
<=
'X'
;
ack_sreg
(
0
)
<=
'1'
;
rddata_reg
(
31
)
<=
'X'
;
ack_in_progress
<=
'1'
;
ack_sreg
(
0
)
<=
'1'
;
when
others
=>
ack_in_progress
<=
'1'
;
when
others
=>
-- prevent the slave from hanging the bus on invalid address
-- prevent the slave from hanging the bus on invalid address
ack_in_progress
<=
'1'
;
ack_in_progress
<=
'1'
;
ack_sreg
(
0
)
<=
'1'
;
ack_sreg
(
0
)
<=
'1'
;
end
case
;
end
case
;
end
if
;
end
if
;
end
if
;
end
if
;
end
if
;
end
if
;
end
process
;
end
process
;
-- Drive the data output bus
-- Drive the data output bus
wb_dat_o
<=
rddata_reg
;
wb_dat_o
<=
rddata_reg
;
-- Version identifier
-- Version identifier
regs_o
.
ver_id_o
<=
wr_streamers_ver_id_int
;
regs_o
.
ver_id_o
<=
wr_streamers_ver_id_int
;
-- Reset statistics
-- Reset statistics
process
(
clk_sys_i
,
rst_n_i
)
process
(
clk_sys_i
,
rst_n_i
)
begin
begin
if
(
rst_n_i
=
'0'
)
then
if
(
rst_n_i
=
'0'
)
then
wr_streamers_sscr1_rst_stats_dly0
<=
'0'
;
wr_streamers_sscr1_rst_stats_dly0
<=
'0'
;
regs_o
.
sscr1_rst_stats_o
<=
'0'
;
regs_o
.
sscr1_rst_stats_o
<=
'0'
;
elsif
rising_edge
(
clk_sys_i
)
then
elsif
rising_edge
(
clk_sys_i
)
then
wr_streamers_sscr1_rst_stats_dly0
<=
wr_streamers_sscr1_rst_stats_int
;
wr_streamers_sscr1_rst_stats_dly0
<=
wr_streamers_sscr1_rst_stats_int
;
regs_o
.
sscr1_rst_stats_o
<=
wr_streamers_sscr1_rst_stats_int
and
(
not
wr_streamers_sscr1_rst_stats_dly0
);
regs_o
.
sscr1_rst_stats_o
<=
wr_streamers_sscr1_rst_stats_int
and
(
not
wr_streamers_sscr1_rst_stats_dly0
);
end
if
;
end
if
;
end
process
;
end
process
;
-- Reset tx seq id
-- Reset tx seq id
process
(
clk_sys_i
,
rst_n_i
)
process
(
clk_sys_i
,
rst_n_i
)
begin
begin
if
(
rst_n_i
=
'0'
)
then
if
(
rst_n_i
=
'0'
)
then
wr_streamers_sscr1_rst_seq_id_dly0
<=
'0'
;
wr_streamers_sscr1_rst_seq_id_dly0
<=
'0'
;
regs_o
.
sscr1_rst_seq_id_o
<=
'0'
;
regs_o
.
sscr1_rst_seq_id_o
<=
'0'
;
elsif
rising_edge
(
clk_sys_i
)
then
elsif
rising_edge
(
clk_sys_i
)
then
wr_streamers_sscr1_rst_seq_id_dly0
<=
wr_streamers_sscr1_rst_seq_id_int
;
wr_streamers_sscr1_rst_seq_id_dly0
<=
wr_streamers_sscr1_rst_seq_id_int
;
regs_o
.
sscr1_rst_seq_id_o
<=
wr_streamers_sscr1_rst_seq_id_int
and
(
not
wr_streamers_sscr1_rst_seq_id_dly0
);
regs_o
.
sscr1_rst_seq_id_o
<=
wr_streamers_sscr1_rst_seq_id_int
and
(
not
wr_streamers_sscr1_rst_seq_id_dly0
);
end
if
;
end
if
;
end
process
;
end
process
;
-- Snapshot statistics
-- Snapshot statistics
regs_o
.
sscr1_snapshot_stats_o
<=
wr_streamers_sscr1_snapshot_stats_int
;
regs_o
.
sscr1_snapshot_stats_o
<=
wr_streamers_sscr1_snapshot_stats_int
;
-- Latency accumulator overflow
-- Latency accumulator overflow
-- Reset timestamp cycles
-- Reset timestamp cycles
-- Reset timestamp 32 LSB of TAI
-- Reset timestamp 32 LSB of TAI
...
@@ -729,86 +729,86 @@ regs_o.sscr1_snapshot_stats_o <= wr_streamers_sscr1_snapshot_stats_int;
...
@@ -729,86 +729,86 @@ regs_o.sscr1_snapshot_stats_o <= wr_streamers_sscr1_snapshot_stats_int;
-- WR Streamer frame latency counter (LSB)
-- WR Streamer frame latency counter (LSB)
-- WR Streamer frame latency counter (MSB)
-- WR Streamer frame latency counter (MSB)
-- Ethertype
-- Ethertype
regs_o
.
tx_cfg0_ethertype_o
<=
wr_streamers_tx_cfg0_ethertype_int
;
regs_o
.
tx_cfg0_ethertype_o
<=
wr_streamers_tx_cfg0_ethertype_int
;
-- MAC Local LSB
-- MAC Local LSB
regs_o
.
tx_cfg1_mac_local_lsb_o
<=
wr_streamers_tx_cfg1_mac_local_lsb_int
;
regs_o
.
tx_cfg1_mac_local_lsb_o
<=
wr_streamers_tx_cfg1_mac_local_lsb_int
;
-- MAC Local MSB
-- MAC Local MSB
regs_o
.
tx_cfg2_mac_local_msb_o
<=
wr_streamers_tx_cfg2_mac_local_msb_int
;
regs_o
.
tx_cfg2_mac_local_msb_o
<=
wr_streamers_tx_cfg2_mac_local_msb_int
;
-- MAC Target LSB
-- MAC Target LSB
regs_o
.
tx_cfg3_mac_target_lsb_o
<=
wr_streamers_tx_cfg3_mac_target_lsb_int
;
regs_o
.
tx_cfg3_mac_target_lsb_o
<=
wr_streamers_tx_cfg3_mac_target_lsb_int
;
-- MAC Target MSB
-- MAC Target MSB
regs_o
.
tx_cfg4_mac_target_msb_o
<=
wr_streamers_tx_cfg4_mac_target_msb_int
;
regs_o
.
tx_cfg4_mac_target_msb_o
<=
wr_streamers_tx_cfg4_mac_target_msb_int
;
-- Enable tagging with Qtags
-- Enable tagging with Qtags
regs_o
.
tx_cfg5_qtag_ena_o
<=
wr_streamers_tx_cfg5_qtag_ena_int
;
regs_o
.
tx_cfg5_qtag_ena_o
<=
wr_streamers_tx_cfg5_qtag_ena_int
;
-- VLAN ID
-- VLAN ID
regs_o
.
tx_cfg5_qtag_vid_o
<=
wr_streamers_tx_cfg5_qtag_vid_int
;
regs_o
.
tx_cfg5_qtag_vid_o
<=
wr_streamers_tx_cfg5_qtag_vid_int
;
-- Priority
-- Priority
regs_o
.
tx_cfg5_qtag_prio_o
<=
wr_streamers_tx_cfg5_qtag_prio_int
;
regs_o
.
tx_cfg5_qtag_prio_o
<=
wr_streamers_tx_cfg5_qtag_prio_int
;
-- Ethertype
-- Ethertype
regs_o
.
rx_cfg0_ethertype_o
<=
wr_streamers_rx_cfg0_ethertype_int
;
regs_o
.
rx_cfg0_ethertype_o
<=
wr_streamers_rx_cfg0_ethertype_int
;
-- Accept Broadcast
-- Accept Broadcast
regs_o
.
rx_cfg0_accept_broadcast_o
<=
wr_streamers_rx_cfg0_accept_broadcast_int
;
regs_o
.
rx_cfg0_accept_broadcast_o
<=
wr_streamers_rx_cfg0_accept_broadcast_int
;
-- Filter Remote
-- Filter Remote
regs_o
.
rx_cfg0_filter_remote_o
<=
wr_streamers_rx_cfg0_filter_remote_int
;
regs_o
.
rx_cfg0_filter_remote_o
<=
wr_streamers_rx_cfg0_filter_remote_int
;
-- MAC Local LSB
-- MAC Local LSB
regs_o
.
rx_cfg1_mac_local_lsb_o
<=
wr_streamers_rx_cfg1_mac_local_lsb_int
;
regs_o
.
rx_cfg1_mac_local_lsb_o
<=
wr_streamers_rx_cfg1_mac_local_lsb_int
;
-- MAC Local MSB
-- MAC Local MSB
regs_o
.
rx_cfg2_mac_local_msb_o
<=
wr_streamers_rx_cfg2_mac_local_msb_int
;
regs_o
.
rx_cfg2_mac_local_msb_o
<=
wr_streamers_rx_cfg2_mac_local_msb_int
;
-- MAC Remote LSB
-- MAC Remote LSB
regs_o
.
rx_cfg3_mac_remote_lsb_o
<=
wr_streamers_rx_cfg3_mac_remote_lsb_int
;
regs_o
.
rx_cfg3_mac_remote_lsb_o
<=
wr_streamers_rx_cfg3_mac_remote_lsb_int
;
-- MAC Remote MSB
-- MAC Remote MSB
regs_o
.
rx_cfg4_mac_remote_msb_o
<=
wr_streamers_rx_cfg4_mac_remote_msb_int
;
regs_o
.
rx_cfg4_mac_remote_msb_o
<=
wr_streamers_rx_cfg4_mac_remote_msb_int
;
-- Fixed Latency
-- Fixed Latency
regs_o
.
rx_cfg5_fixed_latency_o
<=
wr_streamers_rx_cfg5_fixed_latency_int
;
regs_o
.
rx_cfg5_fixed_latency_o
<=
wr_streamers_rx_cfg5_fixed_latency_int
;
-- Tx Ethertype
-- Tx Ethertype
regs_o
.
cfg_or_tx_ethtype_o
<=
wr_streamers_cfg_or_tx_ethtype_int
;
regs_o
.
cfg_or_tx_ethtype_o
<=
wr_streamers_cfg_or_tx_ethtype_int
;
-- Tx MAC Local
-- Tx MAC Local
regs_o
.
cfg_or_tx_mac_loc_o
<=
wr_streamers_cfg_or_tx_mac_loc_int
;
regs_o
.
cfg_or_tx_mac_loc_o
<=
wr_streamers_cfg_or_tx_mac_loc_int
;
-- Tx MAC Target
-- Tx MAC Target
regs_o
.
cfg_or_tx_mac_tar_o
<=
wr_streamers_cfg_or_tx_mac_tar_int
;
regs_o
.
cfg_or_tx_mac_tar_o
<=
wr_streamers_cfg_or_tx_mac_tar_int
;
-- QTAG
-- QTAG
regs_o
.
cfg_or_tx_qtag_o
<=
wr_streamers_cfg_or_tx_qtag_int
;
regs_o
.
cfg_or_tx_qtag_o
<=
wr_streamers_cfg_or_tx_qtag_int
;
-- Rx Ethertype
-- Rx Ethertype
regs_o
.
cfg_or_rx_ethertype_o
<=
wr_streamers_cfg_or_rx_ethertype_int
;
regs_o
.
cfg_or_rx_ethertype_o
<=
wr_streamers_cfg_or_rx_ethertype_int
;
-- Rx MAC Local
-- Rx MAC Local
regs_o
.
cfg_or_rx_mac_loc_o
<=
wr_streamers_cfg_or_rx_mac_loc_int
;
regs_o
.
cfg_or_rx_mac_loc_o
<=
wr_streamers_cfg_or_rx_mac_loc_int
;
-- Rx MAC Remote
-- Rx MAC Remote
regs_o
.
cfg_or_rx_mac_rem_o
<=
wr_streamers_cfg_or_rx_mac_rem_int
;
regs_o
.
cfg_or_rx_mac_rem_o
<=
wr_streamers_cfg_or_rx_mac_rem_int
;
-- Rx Accept Broadcast
-- Rx Accept Broadcast
regs_o
.
cfg_or_rx_acc_broadcast_o
<=
wr_streamers_cfg_or_rx_acc_broadcast_int
;
regs_o
.
cfg_or_rx_acc_broadcast_o
<=
wr_streamers_cfg_or_rx_acc_broadcast_int
;
-- Rx Filter Remote
-- Rx Filter Remote
regs_o
.
cfg_or_rx_ftr_remote_o
<=
wr_streamers_cfg_or_rx_ftr_remote_int
;
regs_o
.
cfg_or_rx_ftr_remote_o
<=
wr_streamers_cfg_or_rx_ftr_remote_int
;
-- Rx Fixed Latency
-- Rx Fixed Latency
regs_o
.
cfg_or_rx_fix_lat_o
<=
wr_streamers_cfg_or_rx_fix_lat_int
;
regs_o
.
cfg_or_rx_fix_lat_o
<=
wr_streamers_cfg_or_rx_fix_lat_int
;
-- Debug Tx (0) or Rx (1)
-- Debug Tx (0) or Rx (1)
regs_o
.
dbg_ctrl_mux_o
<=
wr_streamers_dbg_ctrl_mux_int
;
regs_o
.
dbg_ctrl_mux_o
<=
wr_streamers_dbg_ctrl_mux_int
;
-- Debug Start byte
-- Debug Start byte
regs_o
.
dbg_ctrl_start_byte_o
<=
wr_streamers_dbg_ctrl_start_byte_int
;
regs_o
.
dbg_ctrl_start_byte_o
<=
wr_streamers_dbg_ctrl_start_byte_int
;
-- Debug content
-- Debug content
-- DUMMY value to read
-- DUMMY value to read
-- Software reset streamers
-- Software reset streamers
process
(
clk_sys_i
,
rst_n_i
)
process
(
clk_sys_i
,
rst_n_i
)
begin
begin
if
(
rst_n_i
=
'0'
)
then
if
(
rst_n_i
=
'0'
)
then
wr_streamers_rstr_rst_sw_dly0
<=
'0'
;
wr_streamers_rstr_rst_sw_dly0
<=
'0'
;
regs_o
.
rstr_rst_sw_o
<=
'0'
;
regs_o
.
rstr_rst_sw_o
<=
'0'
;
elsif
rising_edge
(
clk_sys_i
)
then
elsif
rising_edge
(
clk_sys_i
)
then
wr_streamers_rstr_rst_sw_dly0
<=
wr_streamers_rstr_rst_sw_int
;
wr_streamers_rstr_rst_sw_dly0
<=
wr_streamers_rstr_rst_sw_int
;
regs_o
.
rstr_rst_sw_o
<=
wr_streamers_rstr_rst_sw_int
and
(
not
wr_streamers_rstr_rst_sw_dly0
);
regs_o
.
rstr_rst_sw_o
<=
wr_streamers_rstr_rst_sw_int
and
(
not
wr_streamers_rstr_rst_sw_dly0
);
end
if
;
end
if
;
end
process
;
end
process
;
-- WR Streamer RX Buffer Overflow Count
-- WR Streamer RX Buffer Overflow Count
-- WR Streamer RX Late Frames Count
-- WR Streamer RX Late Frames Count
-- WR Streamer RX Timed-out Frames Count
-- WR Streamer RX Timed-out Frames Count
-- WR Streamer RX OK Frames Count
-- WR Streamer RX OK Frames Count
-- RX Fixed Latency Timeout
-- RX Fixed Latency Timeout
(Default: 0x1000000=~134ms)
regs_o
.
rx_cfg6_rx_fixed_latency_timeout_o
<=
wr_streamers_rx_cfg6_rx_fixed_latency_timeout_int
;
regs_o
.
rx_cfg6_rx_fixed_latency_timeout_o
<=
wr_streamers_rx_cfg6_rx_fixed_latency_timeout_int
;
rwaddr_reg
<=
wb_adr_i
;
rwaddr_reg
<=
wb_adr_i
;
wb_stall_o
<=
(
not
ack_sreg
(
0
))
and
(
wb_stb_i
and
wb_cyc_i
);
wb_stall_o
<=
(
not
ack_sreg
(
0
))
and
(
wb_stb_i
and
wb_cyc_i
);
wb_err_o
<=
'0'
;
wb_err_o
<=
'0'
;
wb_rty_o
<=
'0'
;
wb_rty_o
<=
'0'
;
-- ACK signal generation. Just pass the LSB of ACK counter.
-- ACK signal generation. Just pass the LSB of ACK counter.
wb_ack_o
<=
ack_sreg
(
0
);
wb_ack_o
<=
ack_sreg
(
0
);
end
syn
;
end
syn
;
modules/wr_streamers/wr_streamers_wb.wb
View file @
4e9a8a43
...
@@ -706,10 +706,11 @@ peripheral {
...
@@ -706,10 +706,11 @@ peripheral {
name = "Rx Config Reg 6";
name = "Rx Config Reg 6";
prefix = "RX_CFG6";
prefix = "RX_CFG6";
field {
field {
name = "RX Fixed Latency Timeout";
name = "RX Fixed Latency Timeout
(Default: 0x1000000=~134ms)
";
prefix = "RX_FIXED_LATENCY_TIMEOUT";
prefix = "RX_FIXED_LATENCY_TIMEOUT";
type = SLV;
type = SLV;
size = 28;
size = 28;
reset_value = 0x1000000;
access_bus = READ_WRITE;
access_bus = READ_WRITE;
access_dev = READ_ONLY;
access_dev = READ_ONLY;
};
};
...
...
modules/wr_streamers/wr_streamers_wbgen2_pkg.vhd
View file @
4e9a8a43
...
@@ -3,7 +3,7 @@
...
@@ -3,7 +3,7 @@
---------------------------------------------------------------------------------------
---------------------------------------------------------------------------------------
-- File : wr_streamers_wbgen2_pkg.vhd
-- File : wr_streamers_wbgen2_pkg.vhd
-- Author : auto-generated by wbgen2 from wr_streamers_wb.wb
-- Author : auto-generated by wbgen2 from wr_streamers_wb.wb
-- Created : Wed
Nov 14 18:57:24 2018
-- Created : Wed
May 22 18:20:08 2019
-- Version : 0x00000001
-- Version : 0x00000001
-- Standard : VHDL'87
-- Standard : VHDL'87
---------------------------------------------------------------------------------------
---------------------------------------------------------------------------------------
...
@@ -45,7 +45,7 @@ package wr_streamers_wbgen2_pkg is
...
@@ -45,7 +45,7 @@ package wr_streamers_wbgen2_pkg is
rx_stat15_rx_late_frames_cnt_i
:
std_logic_vector
(
31
downto
0
);
rx_stat15_rx_late_frames_cnt_i
:
std_logic_vector
(
31
downto
0
);
rx_stat16_rx_timeout_frames_cnt_i
:
std_logic_vector
(
31
downto
0
);
rx_stat16_rx_timeout_frames_cnt_i
:
std_logic_vector
(
31
downto
0
);
rx_stat17_rx_match_frames_cnt_i
:
std_logic_vector
(
31
downto
0
);
rx_stat17_rx_match_frames_cnt_i
:
std_logic_vector
(
31
downto
0
);
end
record
;
end
record
;
constant
c_wr_streamers_in_registers_init_value
:
t_wr_streamers_in_registers
:
=
(
constant
c_wr_streamers_in_registers_init_value
:
t_wr_streamers_in_registers
:
=
(
sscr1_rx_latency_acc_overflow_i
=>
'0'
,
sscr1_rx_latency_acc_overflow_i
=>
'0'
,
...
@@ -72,87 +72,86 @@ package wr_streamers_wbgen2_pkg is
...
@@ -72,87 +72,86 @@ package wr_streamers_wbgen2_pkg is
rx_stat15_rx_late_frames_cnt_i
=>
(
others
=>
'0'
),
rx_stat15_rx_late_frames_cnt_i
=>
(
others
=>
'0'
),
rx_stat16_rx_timeout_frames_cnt_i
=>
(
others
=>
'0'
),
rx_stat16_rx_timeout_frames_cnt_i
=>
(
others
=>
'0'
),
rx_stat17_rx_match_frames_cnt_i
=>
(
others
=>
'0'
)
rx_stat17_rx_match_frames_cnt_i
=>
(
others
=>
'0'
)
);
);
-- Output registers (WB slave -> user design)
-- Output registers (WB slave -> user design)
type
t_wr_streamers_out_registers
is
record
type
t_wr_streamers_out_registers
is
record
ver_id_o
:
std_logic_vector
(
31
downto
0
);
ver_id_o
:
std_logic_vector
(
31
downto
0
);
sscr1_rst_stats_o
:
std_logic
;
sscr1_rst_stats_o
:
std_logic
;
sscr1_rst_seq_id_o
:
std_logic
;
sscr1_rst_seq_id_o
:
std_logic
;
sscr1_snapshot_stats_o
:
std_logic
;
sscr1_snapshot_stats_o
:
std_logic
;
tx_cfg0_ethertype_o
:
std_logic_vector
(
15
downto
0
);
tx_cfg0_ethertype_o
:
std_logic_vector
(
15
downto
0
);
tx_cfg1_mac_local_lsb_o
:
std_logic_vector
(
31
downto
0
);
tx_cfg1_mac_local_lsb_o
:
std_logic_vector
(
31
downto
0
);
tx_cfg2_mac_local_msb_o
:
std_logic_vector
(
15
downto
0
);
tx_cfg2_mac_local_msb_o
:
std_logic_vector
(
15
downto
0
);
tx_cfg3_mac_target_lsb_o
:
std_logic_vector
(
31
downto
0
);
tx_cfg3_mac_target_lsb_o
:
std_logic_vector
(
31
downto
0
);
tx_cfg4_mac_target_msb_o
:
std_logic_vector
(
15
downto
0
);
tx_cfg4_mac_target_msb_o
:
std_logic_vector
(
15
downto
0
);
tx_cfg5_qtag_ena_o
:
std_logic
;
tx_cfg5_qtag_ena_o
:
std_logic
;
tx_cfg5_qtag_vid_o
:
std_logic_vector
(
11
downto
0
);
tx_cfg5_qtag_vid_o
:
std_logic_vector
(
11
downto
0
);
tx_cfg5_qtag_prio_o
:
std_logic_vector
(
2
downto
0
);
tx_cfg5_qtag_prio_o
:
std_logic_vector
(
2
downto
0
);
rx_cfg0_ethertype_o
:
std_logic_vector
(
15
downto
0
);
rx_cfg0_ethertype_o
:
std_logic_vector
(
15
downto
0
);
rx_cfg0_accept_broadcast_o
:
std_logic
;
rx_cfg0_accept_broadcast_o
:
std_logic
;
rx_cfg0_filter_remote_o
:
std_logic
;
rx_cfg0_filter_remote_o
:
std_logic
;
rx_cfg1_mac_local_lsb_o
:
std_logic_vector
(
31
downto
0
);
rx_cfg1_mac_local_lsb_o
:
std_logic_vector
(
31
downto
0
);
rx_cfg2_mac_local_msb_o
:
std_logic_vector
(
15
downto
0
);
rx_cfg2_mac_local_msb_o
:
std_logic_vector
(
15
downto
0
);
rx_cfg3_mac_remote_lsb_o
:
std_logic_vector
(
31
downto
0
);
rx_cfg3_mac_remote_lsb_o
:
std_logic_vector
(
31
downto
0
);
rx_cfg4_mac_remote_msb_o
:
std_logic_vector
(
15
downto
0
);
rx_cfg4_mac_remote_msb_o
:
std_logic_vector
(
15
downto
0
);
rx_cfg5_fixed_latency_o
:
std_logic_vector
(
27
downto
0
);
rx_cfg5_fixed_latency_o
:
std_logic_vector
(
27
downto
0
);
cfg_or_tx_ethtype_o
:
std_logic
;
cfg_or_tx_ethtype_o
:
std_logic
;
cfg_or_tx_mac_loc_o
:
std_logic
;
cfg_or_tx_mac_loc_o
:
std_logic
;
cfg_or_tx_mac_tar_o
:
std_logic
;
cfg_or_tx_mac_tar_o
:
std_logic
;
cfg_or_tx_qtag_o
:
std_logic
;
cfg_or_tx_qtag_o
:
std_logic
;
cfg_or_rx_ethertype_o
:
std_logic
;
cfg_or_rx_ethertype_o
:
std_logic
;
cfg_or_rx_mac_loc_o
:
std_logic
;
cfg_or_rx_mac_loc_o
:
std_logic
;
cfg_or_rx_mac_rem_o
:
std_logic
;
cfg_or_rx_mac_rem_o
:
std_logic
;
cfg_or_rx_acc_broadcast_o
:
std_logic
;
cfg_or_rx_acc_broadcast_o
:
std_logic
;
cfg_or_rx_ftr_remote_o
:
std_logic
;
cfg_or_rx_ftr_remote_o
:
std_logic
;
cfg_or_rx_fix_lat_o
:
std_logic
;
cfg_or_rx_fix_lat_o
:
std_logic
;
dbg_ctrl_mux_o
:
std_logic
;
dbg_ctrl_mux_o
:
std_logic
;
dbg_ctrl_start_byte_o
:
std_logic_vector
(
7
downto
0
);
dbg_ctrl_start_byte_o
:
std_logic_vector
(
7
downto
0
);
rstr_rst_sw_o
:
std_logic
;
rstr_rst_sw_o
:
std_logic
;
rx_cfg6_rx_fixed_latency_timeout_o
:
std_logic_vector
(
27
downto
0
);
rx_cfg6_rx_fixed_latency_timeout_o
:
std_logic_vector
(
27
downto
0
);
end
record
;
end
record
;
constant
c_wr_streamers_out_registers_init_value
:
t_wr_streamers_out_registers
:
=
(
constant
c_wr_streamers_out_registers_init_value
:
t_wr_streamers_out_registers
:
=
(
ver_id_o
=>
(
others
=>
'0'
),
ver_id_o
=>
(
others
=>
'0'
),
sscr1_rst_stats_o
=>
'0'
,
sscr1_rst_stats_o
=>
'0'
,
sscr1_rst_seq_id_o
=>
'0'
,
sscr1_rst_seq_id_o
=>
'0'
,
sscr1_snapshot_stats_o
=>
'0'
,
sscr1_snapshot_stats_o
=>
'0'
,
tx_cfg0_ethertype_o
=>
(
others
=>
'0'
),
tx_cfg0_ethertype_o
=>
(
others
=>
'0'
),
tx_cfg1_mac_local_lsb_o
=>
(
others
=>
'0'
),
tx_cfg1_mac_local_lsb_o
=>
(
others
=>
'0'
),
tx_cfg2_mac_local_msb_o
=>
(
others
=>
'0'
),
tx_cfg2_mac_local_msb_o
=>
(
others
=>
'0'
),
tx_cfg3_mac_target_lsb_o
=>
(
others
=>
'0'
),
tx_cfg3_mac_target_lsb_o
=>
(
others
=>
'0'
),
tx_cfg4_mac_target_msb_o
=>
(
others
=>
'0'
),
tx_cfg4_mac_target_msb_o
=>
(
others
=>
'0'
),
tx_cfg5_qtag_ena_o
=>
'0'
,
tx_cfg5_qtag_ena_o
=>
'0'
,
tx_cfg5_qtag_vid_o
=>
(
others
=>
'0'
),
tx_cfg5_qtag_vid_o
=>
(
others
=>
'0'
),
tx_cfg5_qtag_prio_o
=>
(
others
=>
'0'
),
tx_cfg5_qtag_prio_o
=>
(
others
=>
'0'
),
rx_cfg0_ethertype_o
=>
(
others
=>
'0'
),
rx_cfg0_ethertype_o
=>
(
others
=>
'0'
),
rx_cfg0_accept_broadcast_o
=>
'0'
,
rx_cfg0_accept_broadcast_o
=>
'0'
,
rx_cfg0_filter_remote_o
=>
'0'
,
rx_cfg0_filter_remote_o
=>
'0'
,
rx_cfg1_mac_local_lsb_o
=>
(
others
=>
'0'
),
rx_cfg1_mac_local_lsb_o
=>
(
others
=>
'0'
),
rx_cfg2_mac_local_msb_o
=>
(
others
=>
'0'
),
rx_cfg2_mac_local_msb_o
=>
(
others
=>
'0'
),
rx_cfg3_mac_remote_lsb_o
=>
(
others
=>
'0'
),
rx_cfg3_mac_remote_lsb_o
=>
(
others
=>
'0'
),
rx_cfg4_mac_remote_msb_o
=>
(
others
=>
'0'
),
rx_cfg4_mac_remote_msb_o
=>
(
others
=>
'0'
),
rx_cfg5_fixed_latency_o
=>
(
others
=>
'0'
),
rx_cfg5_fixed_latency_o
=>
(
others
=>
'0'
),
cfg_or_tx_ethtype_o
=>
'0'
,
cfg_or_tx_ethtype_o
=>
'0'
,
cfg_or_tx_mac_loc_o
=>
'0'
,
cfg_or_tx_mac_loc_o
=>
'0'
,
cfg_or_tx_mac_tar_o
=>
'0'
,
cfg_or_tx_mac_tar_o
=>
'0'
,
cfg_or_tx_qtag_o
=>
'0'
,
cfg_or_tx_qtag_o
=>
'0'
,
cfg_or_rx_ethertype_o
=>
'0'
,
cfg_or_rx_ethertype_o
=>
'0'
,
cfg_or_rx_mac_loc_o
=>
'0'
,
cfg_or_rx_mac_loc_o
=>
'0'
,
cfg_or_rx_mac_rem_o
=>
'0'
,
cfg_or_rx_mac_rem_o
=>
'0'
,
cfg_or_rx_acc_broadcast_o
=>
'0'
,
cfg_or_rx_acc_broadcast_o
=>
'0'
,
cfg_or_rx_ftr_remote_o
=>
'0'
,
cfg_or_rx_ftr_remote_o
=>
'0'
,
cfg_or_rx_fix_lat_o
=>
'0'
,
cfg_or_rx_fix_lat_o
=>
'0'
,
dbg_ctrl_mux_o
=>
'0'
,
dbg_ctrl_mux_o
=>
'0'
,
dbg_ctrl_start_byte_o
=>
(
others
=>
'0'
),
dbg_ctrl_start_byte_o
=>
(
others
=>
'0'
),
rstr_rst_sw_o
=>
'0'
,
rstr_rst_sw_o
=>
'0'
,
rx_cfg6_rx_fixed_latency_timeout_o
=>
(
others
=>
'0'
)
rx_cfg6_rx_fixed_latency_timeout_o
=>
(
others
=>
'0'
)
);
);
function
"or"
(
left
,
right
:
t_wr_streamers_in_registers
)
return
t_wr_streamers_in_registers
;
function
"or"
(
left
,
right
:
t_wr_streamers_in_registers
)
return
t_wr_streamers_in_registers
;
function
f_x_to_zero
(
x
:
std_logic
)
return
std_logic
;
function
f_x_to_zero
(
x
:
std_logic
)
return
std_logic
;
function
f_x_to_zero
(
x
:
std_logic_vector
)
return
std_logic_vector
;
function
f_x_to_zero
(
x
:
std_logic_vector
)
return
std_logic_vector
;
component
wr_streamers_wb
is
component
wr_streamers_wb
is
port
(
port
(
...
@@ -173,60 +172,56 @@ component wr_streamers_wb is
...
@@ -173,60 +172,56 @@ component wr_streamers_wb is
regs_o
:
out
t_wr_streamers_out_registers
regs_o
:
out
t_wr_streamers_out_registers
);
);
end
component
;
end
component
;
end
package
;
end
package
;
package
body
wr_streamers_wbgen2_pkg
is
package
body
wr_streamers_wbgen2_pkg
is
function
f_x_to_zero
(
x
:
std_logic
)
return
std_logic
is
function
f_x_to_zero
(
x
:
std_logic
)
return
std_logic
is
begin
begin
if
x
=
'1'
then
if
x
=
'1'
then
return
'1'
;
return
'1'
;
else
else
return
'0'
;
return
'0'
;
end
if
;
end
if
;
end
function
;
end
function
;
function
f_x_to_zero
(
x
:
std_logic_vector
)
return
std_logic_vector
is
function
f_x_to_zero
(
x
:
std_logic_vector
)
return
std_logic_vector
is
variable
tmp
:
std_logic_vector
(
x
'length
-1
downto
0
);
variable
tmp
:
std_logic_vector
(
x
'length
-1
downto
0
);
begin
begin
for
i
in
0
to
x
'length
-1
loop
for
i
in
0
to
x
'length
-1
loop
if
(
x
(
i
)
=
'X'
or
x
(
i
)
=
'U
'
)
then
if
(
x
(
i
)
=
'1
'
)
then
tmp
(
i
):
=
'0
'
;
tmp
(
i
):
=
'1
'
;
else
else
tmp
(
i
):
=
x
(
i
)
;
tmp
(
i
):
=
'0'
;
end
if
;
end
if
;
end
loop
;
end
loop
;
return
tmp
;
return
tmp
;
end
function
;
end
function
;
function
"or"
(
left
,
right
:
t_wr_streamers_in_registers
)
return
t_wr_streamers_in_registers
is
function
"or"
(
left
,
right
:
t_wr_streamers_in_registers
)
return
t_wr_streamers_in_registers
is
variable
tmp
:
t_wr_streamers_in_registers
;
variable
tmp
:
t_wr_streamers_in_registers
;
begin
begin
tmp
.
sscr1_rx_latency_acc_overflow_i
:
=
f_x_to_zero
(
left
.
sscr1_rx_latency_acc_overflow_i
)
or
f_x_to_zero
(
right
.
sscr1_rx_latency_acc_overflow_i
);
tmp
.
sscr1_rx_latency_acc_overflow_i
:
=
f_x_to_zero
(
left
.
sscr1_rx_latency_acc_overflow_i
)
or
f_x_to_zero
(
right
.
sscr1_rx_latency_acc_overflow_i
);
tmp
.
sscr1_rst_ts_cyc_i
:
=
f_x_to_zero
(
left
.
sscr1_rst_ts_cyc_i
)
or
f_x_to_zero
(
right
.
sscr1_rst_ts_cyc_i
);
tmp
.
sscr1_rst_ts_cyc_i
:
=
f_x_to_zero
(
left
.
sscr1_rst_ts_cyc_i
)
or
f_x_to_zero
(
right
.
sscr1_rst_ts_cyc_i
);
tmp
.
sscr2_rst_ts_tai_lsb_i
:
=
f_x_to_zero
(
left
.
sscr2_rst_ts_tai_lsb_i
)
or
f_x_to_zero
(
right
.
sscr2_rst_ts_tai_lsb_i
);
tmp
.
sscr2_rst_ts_tai_lsb_i
:
=
f_x_to_zero
(
left
.
sscr2_rst_ts_tai_lsb_i
)
or
f_x_to_zero
(
right
.
sscr2_rst_ts_tai_lsb_i
);
tmp
.
sscr3_rst_ts_tai_msb_i
:
=
f_x_to_zero
(
left
.
sscr3_rst_ts_tai_msb_i
)
or
f_x_to_zero
(
right
.
sscr3_rst_ts_tai_msb_i
);
tmp
.
sscr3_rst_ts_tai_msb_i
:
=
f_x_to_zero
(
left
.
sscr3_rst_ts_tai_msb_i
)
or
f_x_to_zero
(
right
.
sscr3_rst_ts_tai_msb_i
);
tmp
.
rx_stat0_rx_latency_max_i
:
=
f_x_to_zero
(
left
.
rx_stat0_rx_latency_max_i
)
or
f_x_to_zero
(
right
.
rx_stat0_rx_latency_max_i
);
tmp
.
rx_stat0_rx_latency_max_i
:
=
f_x_to_zero
(
left
.
rx_stat0_rx_latency_max_i
)
or
f_x_to_zero
(
right
.
rx_stat0_rx_latency_max_i
);
tmp
.
rx_stat1_rx_latency_min_i
:
=
f_x_to_zero
(
left
.
rx_stat1_rx_latency_min_i
)
or
f_x_to_zero
(
right
.
rx_stat1_rx_latency_min_i
);
tmp
.
rx_stat1_rx_latency_min_i
:
=
f_x_to_zero
(
left
.
rx_stat1_rx_latency_min_i
)
or
f_x_to_zero
(
right
.
rx_stat1_rx_latency_min_i
);
tmp
.
tx_stat2_tx_sent_cnt_lsb_i
:
=
f_x_to_zero
(
left
.
tx_stat2_tx_sent_cnt_lsb_i
)
or
f_x_to_zero
(
right
.
tx_stat2_tx_sent_cnt_lsb_i
);
tmp
.
tx_stat2_tx_sent_cnt_lsb_i
:
=
f_x_to_zero
(
left
.
tx_stat2_tx_sent_cnt_lsb_i
)
or
f_x_to_zero
(
right
.
tx_stat2_tx_sent_cnt_lsb_i
);
tmp
.
tx_stat3_tx_sent_cnt_msb_i
:
=
f_x_to_zero
(
left
.
tx_stat3_tx_sent_cnt_msb_i
)
or
f_x_to_zero
(
right
.
tx_stat3_tx_sent_cnt_msb_i
);
tmp
.
tx_stat3_tx_sent_cnt_msb_i
:
=
f_x_to_zero
(
left
.
tx_stat3_tx_sent_cnt_msb_i
)
or
f_x_to_zero
(
right
.
tx_stat3_tx_sent_cnt_msb_i
);
tmp
.
rx_stat4_rx_rcvd_cnt_lsb_i
:
=
f_x_to_zero
(
left
.
rx_stat4_rx_rcvd_cnt_lsb_i
)
or
f_x_to_zero
(
right
.
rx_stat4_rx_rcvd_cnt_lsb_i
);
tmp
.
rx_stat4_rx_rcvd_cnt_lsb_i
:
=
f_x_to_zero
(
left
.
rx_stat4_rx_rcvd_cnt_lsb_i
)
or
f_x_to_zero
(
right
.
rx_stat4_rx_rcvd_cnt_lsb_i
);
tmp
.
rx_stat5_rx_rcvd_cnt_msb_i
:
=
f_x_to_zero
(
left
.
rx_stat5_rx_rcvd_cnt_msb_i
)
or
f_x_to_zero
(
right
.
rx_stat5_rx_rcvd_cnt_msb_i
);
tmp
.
rx_stat5_rx_rcvd_cnt_msb_i
:
=
f_x_to_zero
(
left
.
rx_stat5_rx_rcvd_cnt_msb_i
)
or
f_x_to_zero
(
right
.
rx_stat5_rx_rcvd_cnt_msb_i
);
tmp
.
rx_stat6_rx_loss_cnt_lsb_i
:
=
f_x_to_zero
(
left
.
rx_stat6_rx_loss_cnt_lsb_i
)
or
f_x_to_zero
(
right
.
rx_stat6_rx_loss_cnt_lsb_i
);
tmp
.
rx_stat6_rx_loss_cnt_lsb_i
:
=
f_x_to_zero
(
left
.
rx_stat6_rx_loss_cnt_lsb_i
)
or
f_x_to_zero
(
right
.
rx_stat6_rx_loss_cnt_lsb_i
);
tmp
.
rx_stat7_rx_loss_cnt_msb_i
:
=
f_x_to_zero
(
left
.
rx_stat7_rx_loss_cnt_msb_i
)
or
f_x_to_zero
(
right
.
rx_stat7_rx_loss_cnt_msb_i
);
tmp
.
rx_stat7_rx_loss_cnt_msb_i
:
=
f_x_to_zero
(
left
.
rx_stat7_rx_loss_cnt_msb_i
)
or
f_x_to_zero
(
right
.
rx_stat7_rx_loss_cnt_msb_i
);
tmp
.
rx_stat8_rx_lost_block_cnt_lsb_i
:
=
f_x_to_zero
(
left
.
rx_stat8_rx_lost_block_cnt_lsb_i
)
or
f_x_to_zero
(
right
.
rx_stat8_rx_lost_block_cnt_lsb_i
);
tmp
.
rx_stat8_rx_lost_block_cnt_lsb_i
:
=
f_x_to_zero
(
left
.
rx_stat8_rx_lost_block_cnt_lsb_i
)
or
f_x_to_zero
(
right
.
rx_stat8_rx_lost_block_cnt_lsb_i
);
tmp
.
rx_stat9_rx_lost_block_cnt_msb_i
:
=
f_x_to_zero
(
left
.
rx_stat9_rx_lost_block_cnt_msb_i
)
or
f_x_to_zero
(
right
.
rx_stat9_rx_lost_block_cnt_msb_i
);
tmp
.
rx_stat9_rx_lost_block_cnt_msb_i
:
=
f_x_to_zero
(
left
.
rx_stat9_rx_lost_block_cnt_msb_i
)
or
f_x_to_zero
(
right
.
rx_stat9_rx_lost_block_cnt_msb_i
);
tmp
.
rx_stat10_rx_latency_acc_lsb_i
:
=
f_x_to_zero
(
left
.
rx_stat10_rx_latency_acc_lsb_i
)
or
f_x_to_zero
(
right
.
rx_stat10_rx_latency_acc_lsb_i
);
tmp
.
rx_stat10_rx_latency_acc_lsb_i
:
=
f_x_to_zero
(
left
.
rx_stat10_rx_latency_acc_lsb_i
)
or
f_x_to_zero
(
right
.
rx_stat10_rx_latency_acc_lsb_i
);
tmp
.
rx_stat11_rx_latency_acc_msb_i
:
=
f_x_to_zero
(
left
.
rx_stat11_rx_latency_acc_msb_i
)
or
f_x_to_zero
(
right
.
rx_stat11_rx_latency_acc_msb_i
);
tmp
.
rx_stat11_rx_latency_acc_msb_i
:
=
f_x_to_zero
(
left
.
rx_stat11_rx_latency_acc_msb_i
)
or
f_x_to_zero
(
right
.
rx_stat11_rx_latency_acc_msb_i
);
tmp
.
rx_stat12_rx_latency_acc_cnt_lsb_i
:
=
f_x_to_zero
(
left
.
rx_stat12_rx_latency_acc_cnt_lsb_i
)
or
f_x_to_zero
(
right
.
rx_stat12_rx_latency_acc_cnt_lsb_i
);
tmp
.
rx_stat12_rx_latency_acc_cnt_lsb_i
:
=
f_x_to_zero
(
left
.
rx_stat12_rx_latency_acc_cnt_lsb_i
)
or
f_x_to_zero
(
right
.
rx_stat12_rx_latency_acc_cnt_lsb_i
);
tmp
.
rx_stat13_rx_latency_acc_cnt_msb_i
:
=
f_x_to_zero
(
left
.
rx_stat13_rx_latency_acc_cnt_msb_i
)
or
f_x_to_zero
(
right
.
rx_stat13_rx_latency_acc_cnt_msb_i
);
tmp
.
rx_stat13_rx_latency_acc_cnt_msb_i
:
=
f_x_to_zero
(
left
.
rx_stat13_rx_latency_acc_cnt_msb_i
)
or
f_x_to_zero
(
right
.
rx_stat13_rx_latency_acc_cnt_msb_i
);
tmp
.
dbg_data_i
:
=
f_x_to_zero
(
left
.
dbg_data_i
)
or
f_x_to_zero
(
right
.
dbg_data_i
);
tmp
.
dbg_data_i
:
=
f_x_to_zero
(
left
.
dbg_data_i
)
or
f_x_to_zero
(
right
.
dbg_data_i
);
tmp
.
dummy_dummy_i
:
=
f_x_to_zero
(
left
.
dummy_dummy_i
)
or
f_x_to_zero
(
right
.
dummy_dummy_i
);
tmp
.
dummy_dummy_i
:
=
f_x_to_zero
(
left
.
dummy_dummy_i
)
or
f_x_to_zero
(
right
.
dummy_dummy_i
);
tmp
.
rx_stat14_rx_buf_overflow_cnt_i
:
=
f_x_to_zero
(
left
.
rx_stat14_rx_buf_overflow_cnt_i
)
or
f_x_to_zero
(
right
.
rx_stat14_rx_buf_overflow_cnt_i
);
tmp
.
rx_stat14_rx_buf_overflow_cnt_i
:
=
f_x_to_zero
(
left
.
rx_stat14_rx_buf_overflow_cnt_i
)
or
f_x_to_zero
(
right
.
rx_stat14_rx_buf_overflow_cnt_i
);
tmp
.
rx_stat15_rx_late_frames_cnt_i
:
=
f_x_to_zero
(
left
.
rx_stat15_rx_late_frames_cnt_i
)
or
f_x_to_zero
(
right
.
rx_stat15_rx_late_frames_cnt_i
);
tmp
.
rx_stat15_rx_late_frames_cnt_i
:
=
f_x_to_zero
(
left
.
rx_stat15_rx_late_frames_cnt_i
)
or
f_x_to_zero
(
right
.
rx_stat15_rx_late_frames_cnt_i
);
tmp
.
rx_stat16_rx_timeout_frames_cnt_i
:
=
f_x_to_zero
(
left
.
rx_stat16_rx_timeout_frames_cnt_i
)
or
f_x_to_zero
(
right
.
rx_stat16_rx_timeout_frames_cnt_i
);
tmp
.
rx_stat16_rx_timeout_frames_cnt_i
:
=
f_x_to_zero
(
left
.
rx_stat16_rx_timeout_frames_cnt_i
)
or
f_x_to_zero
(
right
.
rx_stat16_rx_timeout_frames_cnt_i
);
tmp
.
rx_stat17_rx_match_frames_cnt_i
:
=
f_x_to_zero
(
left
.
rx_stat17_rx_match_frames_cnt_i
)
or
f_x_to_zero
(
right
.
rx_stat17_rx_match_frames_cnt_i
);
tmp
.
rx_stat17_rx_match_frames_cnt_i
:
=
f_x_to_zero
(
left
.
rx_stat17_rx_match_frames_cnt_i
)
or
f_x_to_zero
(
right
.
rx_stat17_rx_match_frames_cnt_i
);
return
tmp
;
return
tmp
;
end
function
;
end
function
;
end
package
body
;
end
package
body
;
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