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White Rabbit core collection
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White Rabbit core collection
Commits
4c98fb83
Commit
4c98fb83
authored
Oct 28, 2011
by
Grzegorz Daniluk
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wr_core: version 2 in separate branch, redesigned and wishbonized
parent
b41659cd
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7 changed files
with
1176 additions
and
711 deletions
+1176
-711
Manifest.py
Manifest.py
+1
-4
Manifest.py
modules/wrc_core/Manifest.py
+5
-4
wr_core.vhd
modules/wrc_core/wr_core.vhd
+354
-393
wrc_periph.vhd
modules/wrc_core/wrc_periph.vhd
+146
-152
wrc_syscon_pkg.vhd
modules/wrc_core/wrc_syscon_pkg.vhd
+99
-0
wrc_syscon_wb.vhd
modules/wrc_core/wrc_syscon_wb.vhd
+460
-0
wrcore_pkg.vhd
modules/wrc_core/wrcore_pkg.vhd
+111
-158
No files found.
Manifest.py
View file @
4c98fb83
...
...
@@ -6,12 +6,9 @@ modules = {"local" :
"modules/timing"
,
"modules/wr_mini_nic"
,
"modules/wr_softpll"
,
"modules/wrc_lm32"
,
"modules/wr_endpoint"
,
"modules/wr_pps_gen"
,
"modules/wrc_core"
],
"git"
:
"git://ohwr.org/hdl-core-lib/general-cores.git::wishbone_with_adapter"
}
\ No newline at end of file
modules/wrc_core/Manifest.py
View file @
4c98fb83
files
=
[
"wr_core.vhd"
,
files
=
[
"xwr_core.vhd"
,
"wr_core.vhd"
,
"wrc_dpram.vhd"
,
"wrcore_pkg.vhd"
,
"wrc_periph.vhd"
,
"wb_reset.vhd"
,
"wbp_mux.vhd"
];
modules
=
{
"local"
:
"wb_conmax"
}
;
"wbp_mux.vhd"
,
"wrc_syscon_wb.vhd"
,
"wrc_syscon_pkg.vhd"
]
;
modules/wrc_core/wr_core.vhd
View file @
4c98fb83
This diff is collapsed.
Click to expand it.
modules/wrc_core/wrc_periph.vhd
View file @
4c98fb83
This diff is collapsed.
Click to expand it.
modules/wrc_core/wrc_syscon_pkg.vhd
0 → 100644
View file @
4c98fb83
---------------------------------------------------------------------------------------
-- Title : Wishbone slave core for WR Core System Controller
---------------------------------------------------------------------------------------
-- File : wrc_syscon_pkg.vhd
-- Author : auto-generated by wbgen2 from wrc_syscon_wb.wb
-- Created : Tue Oct 25 21:17:25 2011
-- Standard : VHDL'87
---------------------------------------------------------------------------------------
-- THIS FILE WAS GENERATED BY wbgen2 FROM SOURCE FILE wrc_syscon_wb.wb
-- DO NOT HAND-EDIT UNLESS IT'S ABSOLUTELY NECESSARY!
---------------------------------------------------------------------------------------
library
ieee
;
use
ieee
.
std_logic_1164
.
all
;
use
ieee
.
numeric_std
.
all
;
package
sysc_wbgen2_pkg
is
-- Input registers (user design -> WB slave)
type
t_sysc_in_registers
is
record
gpsr_fmc_scl_i
:
std_logic
;
gpsr_fmc_sda_i
:
std_logic
;
gpsr_btn1_i
:
std_logic
;
gpsr_btn2_i
:
std_logic
;
hwfr_memsize_i
:
std_logic_vector
(
3
downto
0
);
tvr_i
:
std_logic_vector
(
31
downto
0
);
end
record
;
constant
c_sysc_in_registers_init_value
:
t_sysc_in_registers
:
=
(
gpsr_fmc_scl_i
=>
'0'
,
gpsr_fmc_sda_i
=>
'0'
,
gpsr_btn1_i
=>
'0'
,
gpsr_btn2_i
=>
'0'
,
hwfr_memsize_i
=>
(
others
=>
'0'
),
tvr_i
=>
(
others
=>
'0'
)
);
-- Output registers (WB slave -> user design)
type
t_sysc_out_registers
is
record
rstr_hrst_o
:
std_logic_vector
(
31
downto
0
);
rstr_hrst_wr_o
:
std_logic
;
gpsr_led_stat_o
:
std_logic
;
gpsr_led_link_o
:
std_logic
;
gpsr_fmc_scl_o
:
std_logic
;
gpsr_fmc_scl_load_o
:
std_logic
;
gpsr_fmc_sda_o
:
std_logic
;
gpsr_fmc_sda_load_o
:
std_logic
;
gpsr_net_rst_o
:
std_logic
;
gpcr_led_stat_o
:
std_logic
;
gpcr_led_link_o
:
std_logic
;
gpcr_fmc_scl_o
:
std_logic
;
gpcr_fmc_sda_o
:
std_logic
;
tcr_enable_o
:
std_logic
;
end
record
;
constant
c_sysc_out_registers_init_value
:
t_sysc_out_registers
:
=
(
rstr_hrst_o
=>
(
others
=>
'0'
),
rstr_hrst_wr_o
=>
'0'
,
gpsr_led_stat_o
=>
'0'
,
gpsr_led_link_o
=>
'0'
,
gpsr_fmc_scl_o
=>
'0'
,
gpsr_fmc_scl_load_o
=>
'0'
,
gpsr_fmc_sda_o
=>
'0'
,
gpsr_fmc_sda_load_o
=>
'0'
,
gpsr_net_rst_o
=>
'0'
,
gpcr_led_stat_o
=>
'0'
,
gpcr_led_link_o
=>
'0'
,
gpcr_fmc_scl_o
=>
'0'
,
gpcr_fmc_sda_o
=>
'0'
,
tcr_enable_o
=>
'0'
);
function
"or"
(
left
,
right
:
t_sysc_in_registers
)
return
t_sysc_in_registers
;
function
f_x_to_zero
(
x
:
std_logic
)
return
std_logic
;
end
package
;
package
body
sysc_wbgen2_pkg
is
function
f_x_to_zero
(
x
:
std_logic
)
return
std_logic
is
begin
if
(
x
=
'X'
or
x
=
'U'
)
then
return
'0'
;
else
return
x
;
end
if
;
end
function
;
function
"or"
(
left
,
right
:
t_sysc_in_registers
)
return
t_sysc_in_registers
is
variable
tmp
:
t_sysc_in_registers
;
begin
tmp
.
gpsr_fmc_scl_i
:
=
left
.
gpsr_fmc_scl_i
or
right
.
gpsr_fmc_scl_i
;
tmp
.
gpsr_fmc_sda_i
:
=
left
.
gpsr_fmc_sda_i
or
right
.
gpsr_fmc_sda_i
;
tmp
.
gpsr_btn1_i
:
=
left
.
gpsr_btn1_i
or
right
.
gpsr_btn1_i
;
tmp
.
gpsr_btn2_i
:
=
left
.
gpsr_btn2_i
or
right
.
gpsr_btn2_i
;
tmp
.
hwfr_memsize_i
:
=
left
.
hwfr_memsize_i
or
right
.
hwfr_memsize_i
;
tmp
.
tvr_i
:
=
left
.
tvr_i
or
right
.
tvr_i
;
return
tmp
;
end
function
;
end
package
body
;
modules/wrc_core/wrc_syscon_wb.vhd
0 → 100644
View file @
4c98fb83
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modules/wrc_core/wrcore_pkg.vhd
View file @
4c98fb83
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