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Commit 49c340a6 authored by Tomasz Wlostowski's avatar Tomasz Wlostowski
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wr_softpll: updated to fit the naming conventions, added aux DAC control registers/fields

parent f7a594df
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modules/wr_softpll/Manifest.py
View file @ 49c340a6
files = [ "softpll_wb.vhd",
"wr_softpll.vhd" ];
"wr_softpll.vhd",
"xwr_softpll.vhd" ];
modules/wr_softpll/build_wb.sh
View file @ 49c340a6
#!/bin/bash
wbgen2 -C softpll_regs.h -V softpll_wb.vhd -K ../../sim/softpll_regs.v wr_softpll.wb
\ No newline at end of file
wbgen2 -C softpll_regs.h -V softpll_wb.vhd -K ../../sim/softpll_regs.v wr_softpll.wb -C softpll_regs.h
\ No newline at end of file
modules/wr_softpll/softpll_regs.h 0 → 100644
View file @ 49c340a6
/*
Register definitions for slave core: WR Softcore PLL
* File : softpll_regs.h
* Author : auto-generated by wbgen2 from wr_softpll.wb
* Created : Thu Oct 27 23:54:06 2011
* Standard : ANSI C
THIS FILE WAS GENERATED BY wbgen2 FROM SOURCE FILE wr_softpll.wb
DO NOT HAND-EDIT UNLESS IT'S ABSOLUTELY NECESSARY!
*/
#ifndef __WBGEN2_REGDEFS_WR_SOFTPLL_WB
#define __WBGEN2_REGDEFS_WR_SOFTPLL_WB
#include <inttypes.h>
#if defined( __GNUC__)
#define PACKED __attribute__ ((packed))
#else
#error "Unsupported compiler?"
#endif
#ifndef __WBGEN2_MACROS_DEFINED__
#define __WBGEN2_MACROS_DEFINED__
#define WBGEN2_GEN_MASK(offset, size) (((1<<(size))-1) << (offset))
#define WBGEN2_GEN_WRITE(value, offset, size) (((value) & ((1<<(size))-1)) << (offset))
#define WBGEN2_GEN_READ(reg, offset, size) (((reg) >> (offset)) & ((1<<(size))-1))
#define WBGEN2_SIGN_EXTEND(value, bits) (((value) & (1<<bits) ? ~((1<<(bits))-1): 0 ) | (value))
#endif
/* definitions for register: SPLL Control/Status Register */
/* definitions for field: Tagger enable in reg: SPLL Control/Status Register */
#define SPLL_CSR_TAG_EN_MASK WBGEN2_GEN_MASK(0, 4)
#define SPLL_CSR_TAG_EN_SHIFT 0
#define SPLL_CSR_TAG_EN_W(value) WBGEN2_GEN_WRITE(value, 0, 4)
#define SPLL_CSR_TAG_EN_R(reg) WBGEN2_GEN_READ(reg, 0, 4)
/* definitions for field: Tag ready in reg: SPLL Control/Status Register */
#define SPLL_CSR_TAG_RDY_MASK WBGEN2_GEN_MASK(4, 4)
#define SPLL_CSR_TAG_RDY_SHIFT 4
#define SPLL_CSR_TAG_RDY_W(value) WBGEN2_GEN_WRITE(value, 4, 4)
#define SPLL_CSR_TAG_RDY_R(reg) WBGEN2_GEN_READ(reg, 4, 4)
/* definitions for field: Aux clock locking enable in reg: SPLL Control/Status Register */
#define SPLL_CSR_AUX_EN WBGEN2_GEN_MASK(8, 1)
/* definitions for field: Aux clock locked flag (to slave) in reg: SPLL Control/Status Register */
#define SPLL_CSR_AUX_LOCK WBGEN2_GEN_MASK(9, 1)
/* definitions for register: HPLL Frequency Error */
/* definitions for register: DMPLL Tag ref */
/* definitions for register: DMPLL Tag fb */
/* definitions for register: DMPLL Tag aux */
/* definitions for register: HPLL DAC Output */
/* definitions for register: DMPLL DAC Output */
/* definitions for register: AUX DAC Output */
/* definitions for register: Deglitcher threshold */
/* definitions for register: Interrupt disable register */
/* definitions for field: Got a tag in reg: Interrupt disable register */
#define SPLL_EIC_IDR_TAG WBGEN2_GEN_MASK(0, 1)
/* definitions for register: Interrupt enable register */
/* definitions for field: Got a tag in reg: Interrupt enable register */
#define SPLL_EIC_IER_TAG WBGEN2_GEN_MASK(0, 1)
/* definitions for register: Interrupt mask register */
/* definitions for field: Got a tag in reg: Interrupt mask register */
#define SPLL_EIC_IMR_TAG WBGEN2_GEN_MASK(0, 1)
/* definitions for register: Interrupt status register */
/* definitions for field: Got a tag in reg: Interrupt status register */
#define SPLL_EIC_ISR_TAG WBGEN2_GEN_MASK(0, 1)
PACKED struct SPLL_WB {
/* [0x0]: REG SPLL Control/Status Register */
uint32_t CSR;
/* [0x4]: REG HPLL Frequency Error */
uint32_t PER_HPLL;
/* [0x8]: REG DMPLL Tag ref */
uint32_t TAG_REF;
/* [0xc]: REG DMPLL Tag fb */
uint32_t TAG_FB;
/* [0x10]: REG DMPLL Tag aux */
uint32_t TAG_AUX;
/* [0x14]: REG HPLL DAC Output */
uint32_t DAC_HPLL;
/* [0x18]: REG DMPLL DAC Output */
uint32_t DAC_DMPLL;
/* [0x1c]: REG AUX DAC Output */
uint32_t DAC_AUX;
/* [0x20]: REG Deglitcher threshold */
uint32_t DEGLITCH_THR;
/* padding to: 16 words */
uint32_t __padding_0[7];
/* [0x40]: REG Interrupt disable register */
uint32_t EIC_IDR;
/* [0x44]: REG Interrupt enable register */
uint32_t EIC_IER;
/* [0x48]: REG Interrupt mask register */
uint32_t EIC_IMR;
/* [0x4c]: REG Interrupt status register */
uint32_t EIC_ISR;
};
#endif
modules/wr_softpll/softpll_wb.vhd
View file @ 49c340a6
......@@ -3,7 +3,7 @@
---------------------------------------------------------------------------------------
-- File : softpll_wb.vhd
-- Author : auto-generated by wbgen2 from wr_softpll.wb
-- Created : Tue Oct 25 22:34:41 2011
-- Created : Thu Oct 27 23:54:06 2011
-- Standard : VHDL'87
---------------------------------------------------------------------------------------
-- THIS FILE WAS GENERATED BY wbgen2 FROM SOURCE FILE wr_softpll.wb
......@@ -19,7 +19,7 @@ entity softpll_wb is
port (
rst_n_i : in std_logic;
wb_clk_i : in std_logic;
wb_addr_i : in std_logic_vector(3 downto 0);
wb_addr_i : in std_logic_vector(4 downto 0);
wb_data_i : in std_logic_vector(31 downto 0);
wb_data_o : out std_logic_vector(31 downto 0);
wb_cyc_i : in std_logic;
......@@ -32,6 +32,10 @@ entity softpll_wb is
spll_csr_tag_en_o : out std_logic_vector(3 downto 0);
-- Port for std_logic_vector field: 'Tag ready' in reg: 'SPLL Control/Status Register'
spll_csr_tag_rdy_i : in std_logic_vector(3 downto 0);
-- Port for BIT field: 'Aux clock locking enable' in reg: 'SPLL Control/Status Register'
spll_csr_aux_en_i : in std_logic;
-- Port for BIT field: 'Aux clock locked flag (to slave)' in reg: 'SPLL Control/Status Register'
spll_csr_aux_lock_o : out std_logic;
-- Port for std_logic_vector field: 'Period error value' in reg: 'HPLL Frequency Error'
spll_per_hpll_i : in std_logic_vector(31 downto 0);
tag_hpll_rd_period_o : out std_logic;
......@@ -50,6 +54,9 @@ entity softpll_wb is
-- Ports for PASS_THROUGH field: 'DAC value' in reg: 'DMPLL DAC Output'
spll_dac_dmpll_o : out std_logic_vector(15 downto 0);
spll_dac_dmpll_wr_o : out std_logic;
-- Ports for PASS_THROUGH field: 'DAC value' in reg: 'AUX DAC Output'
spll_dac_aux_o : out std_logic_vector(23 downto 0);
spll_dac_aux_wr_o : out std_logic;
-- Port for std_logic_vector field: 'Threshold' in reg: 'Deglitcher threshold'
spll_deglitch_thr_o : out std_logic_vector(15 downto 0);
irq_tag_i : in std_logic
......@@ -59,6 +66,7 @@ end softpll_wb;
architecture syn of softpll_wb is
signal spll_csr_tag_en_int : std_logic_vector(3 downto 0);
signal spll_csr_aux_lock_int : std_logic ;
signal spll_deglitch_thr_int : std_logic_vector(15 downto 0);
signal eic_idr_int : std_logic_vector(0 downto 0);
signal eic_idr_write_int : std_logic ;
......@@ -74,7 +82,7 @@ signal ack_sreg : std_logic_vector(9 downto 0);
signal rddata_reg : std_logic_vector(31 downto 0);
signal wrdata_reg : std_logic_vector(31 downto 0);
signal bwsel_reg : std_logic_vector(3 downto 0);
signal rwaddr_reg : std_logic_vector(3 downto 0);
signal rwaddr_reg : std_logic_vector(4 downto 0);
signal ack_in_progress : std_logic ;
signal wr_int : std_logic ;
signal rd_int : std_logic ;
......@@ -100,12 +108,14 @@ begin
ack_in_progress <= '0';
rddata_reg <= "00000000000000000000000000000000";
spll_csr_tag_en_int <= "0000";
spll_csr_aux_lock_int <= '0';
tag_hpll_rd_period_o <= '0';
tag_ref_rd_ack_o <= '0';
tag_fb_rd_ack_o <= '0';
tag_aux_rd_ack_o <= '0';
spll_dac_hpll_wr_o <= '0';
spll_dac_dmpll_wr_o <= '0';
spll_dac_aux_wr_o <= '0';
spll_deglitch_thr_int <= "0000000000000000";
eic_idr_write_int <= '0';
eic_ier_write_int <= '0';
......@@ -122,6 +132,7 @@ begin
tag_aux_rd_ack_o <= '0';
spll_dac_hpll_wr_o <= '0';
spll_dac_dmpll_wr_o <= '0';
spll_dac_aux_wr_o <= '0';
eic_idr_write_int <= '0';
eic_ier_write_int <= '0';
eic_isr_write_int <= '0';
......@@ -129,18 +140,22 @@ begin
else
spll_dac_hpll_wr_o <= '0';
spll_dac_dmpll_wr_o <= '0';
spll_dac_aux_wr_o <= '0';
end if;
else
if ((wb_cyc_i = '1') and (wb_stb_i = '1')) then
case rwaddr_reg(3 downto 0) is
when "0000" =>
case rwaddr_reg(4 downto 0) is
when "00000" =>
if (wb_we_i = '1') then
spll_csr_tag_en_int <= wrdata_reg(3 downto 0);
rddata_reg(8) <= 'X';
rddata_reg(9) <= 'X';
spll_csr_aux_lock_int <= wrdata_reg(9);
else
rddata_reg(3 downto 0) <= spll_csr_tag_en_int;
rddata_reg(7 downto 4) <= spll_csr_tag_rdy_i;
rddata_reg(8) <= 'X';
rddata_reg(9) <= 'X';
rddata_reg(8) <= spll_csr_aux_en_i;
rddata_reg(9) <= spll_csr_aux_lock_int;
rddata_reg(10) <= 'X';
rddata_reg(11) <= 'X';
rddata_reg(12) <= 'X';
......@@ -166,7 +181,7 @@ begin
end if;
ack_sreg(0) <= '1';
ack_in_progress <= '1';
when "0001" =>
when "00001" =>
if (wb_we_i = '1') then
else
rddata_reg(31 downto 0) <= spll_per_hpll_i;
......@@ -174,7 +189,7 @@ begin
end if;
ack_sreg(0) <= '1';
ack_in_progress <= '1';
when "0010" =>
when "00010" =>
if (wb_we_i = '1') then
else
rddata_reg(31 downto 0) <= spll_tag_ref_i;
......@@ -182,7 +197,7 @@ begin
end if;
ack_sreg(0) <= '1';
ack_in_progress <= '1';
when "0011" =>
when "00011" =>
if (wb_we_i = '1') then
else
rddata_reg(31 downto 0) <= spll_tag_fb_i;
......@@ -190,7 +205,7 @@ begin
end if;
ack_sreg(0) <= '1';
ack_in_progress <= '1';
when "0100" =>
when "00100" =>
if (wb_we_i = '1') then
else
rddata_reg(31 downto 0) <= spll_tag_aux_i;
......@@ -198,7 +213,7 @@ begin
end if;
ack_sreg(0) <= '1';
ack_in_progress <= '1';
when "0101" =>
when "00101" =>
if (wb_we_i = '1') then
spll_dac_hpll_wr_o <= '1';
else
......@@ -237,7 +252,7 @@ begin
end if;
ack_sreg(0) <= '1';
ack_in_progress <= '1';
when "0110" =>
when "00110" =>
if (wb_we_i = '1') then
spll_dac_dmpll_wr_o <= '1';
else
......@@ -276,7 +291,46 @@ begin
end if;
ack_sreg(0) <= '1';
ack_in_progress <= '1';
when "0111" =>
when "00111" =>
if (wb_we_i = '1') then
spll_dac_aux_wr_o <= '1';
else
rddata_reg(0) <= 'X';
rddata_reg(1) <= 'X';
rddata_reg(2) <= 'X';
rddata_reg(3) <= 'X';
rddata_reg(4) <= 'X';
rddata_reg(5) <= 'X';
rddata_reg(6) <= 'X';
rddata_reg(7) <= 'X';
rddata_reg(8) <= 'X';
rddata_reg(9) <= 'X';
rddata_reg(10) <= 'X';
rddata_reg(11) <= 'X';
rddata_reg(12) <= 'X';
rddata_reg(13) <= 'X';
rddata_reg(14) <= 'X';
rddata_reg(15) <= 'X';
rddata_reg(16) <= 'X';
rddata_reg(17) <= 'X';
rddata_reg(18) <= 'X';
rddata_reg(19) <= 'X';
rddata_reg(20) <= 'X';
rddata_reg(21) <= 'X';
rddata_reg(22) <= 'X';
rddata_reg(23) <= 'X';
rddata_reg(24) <= 'X';
rddata_reg(25) <= 'X';
rddata_reg(26) <= 'X';
rddata_reg(27) <= 'X';
rddata_reg(28) <= 'X';
rddata_reg(29) <= 'X';
rddata_reg(30) <= 'X';
rddata_reg(31) <= 'X';
end if;
ack_sreg(0) <= '1';
ack_in_progress <= '1';
when "01000" =>
if (wb_we_i = '1') then
spll_deglitch_thr_int <= wrdata_reg(15 downto 0);
else
......@@ -300,7 +354,7 @@ begin
end if;
ack_sreg(0) <= '1';
ack_in_progress <= '1';
when "1000" =>
when "10000" =>
if (wb_we_i = '1') then
eic_idr_write_int <= '1';
else
......@@ -339,7 +393,7 @@ begin
end if;
ack_sreg(0) <= '1';
ack_in_progress <= '1';
when "1001" =>
when "10001" =>
if (wb_we_i = '1') then
eic_ier_write_int <= '1';
else
......@@ -378,7 +432,7 @@ begin
end if;
ack_sreg(0) <= '1';
ack_in_progress <= '1';
when "1010" =>
when "10010" =>
if (wb_we_i = '1') then
else
rddata_reg(0) <= eic_imr_int(0);
......@@ -416,7 +470,7 @@ begin
end if;
ack_sreg(0) <= '1';
ack_in_progress <= '1';
when "1011" =>
when "10011" =>
if (wb_we_i = '1') then
eic_isr_write_int <= '1';
else
......@@ -471,6 +525,9 @@ begin
-- Tagger enable
spll_csr_tag_en_o <= spll_csr_tag_en_int;
-- Tag ready
-- Aux clock locking enable
-- Aux clock locked flag (to slave)
spll_csr_aux_lock_o <= spll_csr_aux_lock_int;
-- Period error value
-- Tag value
-- Tag value
......@@ -481,6 +538,9 @@ begin
-- DAC value
-- pass-through field: DAC value in register: DMPLL DAC Output
spll_dac_dmpll_o <= wrdata_reg(15 downto 0);
-- DAC value
-- pass-through field: DAC value in register: AUX DAC Output
spll_dac_aux_o <= wrdata_reg(23 downto 0);
-- Threshold
spll_deglitch_thr_o <= spll_deglitch_thr_int;
-- extra code for reg/fifo/mem: Interrupt disable register
......
modules/wr_softpll/wr_softpll.vhd
View file @ 49c340a6
......@@ -27,9 +27,15 @@ entity wr_softpll is
dac_dmpll_data_o : out std_logic_vector(15 downto 0);
dac_dmpll_load_o : out std_logic;
wb_addr_i : in std_logic_vector(5 downto 0);
wb_data_i : in std_logic_vector(31 downto 0);
wb_data_o : out std_logic_vector(31 downto 0);
dac_aux_data_o : out std_logic_vector(23 downto 0);
dac_aux_load_o : out std_logic;
clk_aux_lock_en_i : in std_logic;
clk_aux_locked_o : out std_logic;
wb_adr_i : in std_logic_vector(6 downto 0);
wb_dat_i : in std_logic_vector(31 downto 0);
wb_dat_o : out std_logic_vector(31 downto 0);
wb_cyc_i : in std_logic;
wb_sel_i : in std_logic_vector(3 downto 0);
wb_stb_i : in std_logic;
......@@ -79,12 +85,12 @@ architecture rtl of wr_softpll is
tag_o : out std_logic_vector(g_counter_bits-1 downto 0);
tag_stb_p1_o : out std_logic);
end component;
component softpll_wb
port (
rst_n_i : in std_logic;
wb_clk_i : in std_logic;
wb_addr_i : in std_logic_vector(3 downto 0);
wb_addr_i : in std_logic_vector(4 downto 0);
wb_data_i : in std_logic_vector(31 downto 0);
wb_data_o : out std_logic_vector(31 downto 0);
wb_cyc_i : in std_logic;
......@@ -95,6 +101,8 @@ architecture rtl of wr_softpll is
wb_irq_o : out std_logic;
spll_csr_tag_en_o : out std_logic_vector(3 downto 0);
spll_csr_tag_rdy_i : in std_logic_vector(3 downto 0);
spll_csr_aux_en_i : in std_logic;
spll_csr_aux_lock_o : out std_logic;
spll_per_hpll_i : in std_logic_vector(31 downto 0);
tag_hpll_rd_period_o : out std_logic;
spll_tag_ref_i : in std_logic_vector(31 downto 0);
......@@ -107,9 +115,12 @@ architecture rtl of wr_softpll is
spll_dac_hpll_wr_o : out std_logic;
spll_dac_dmpll_o : out std_logic_vector(15 downto 0);
spll_dac_dmpll_wr_o : out std_logic;
spll_dac_aux_o : out std_logic_vector(23 downto 0);
spll_dac_aux_wr_o : out std_logic;
spll_deglitch_thr_o : out std_logic_vector(15 downto 0);
irq_tag_i : in std_logic);
end component;
component hpll_period_detect
generic (
g_freq_err_frac_bits : integer := 1);
......@@ -156,6 +167,8 @@ architecture rtl of wr_softpll is
signal spll_csr_tag_rdy : std_logic_vector(3 downto 0);
signal spll_dac_hpll : std_logic_vector(15 downto 0);
signal spll_dac_hpll_wr : std_logic;
signal spll_dac_aux : std_logic_vector(23 downto 0);
signal spll_dac_aux_wr : std_logic;
signal spll_dac_dmpll : std_logic_vector(15 downto 0);
signal spll_dac_dmpll_wr : std_logic;
signal irq_tag : std_logic;
......@@ -181,8 +194,8 @@ architecture rtl of wr_softpll is
begin -- rtl
resized_addr(5 downto 0) <= wb_addr_i;
resized_addr(c_wishbone_address_width-1 downto 4) <= (others => '0');
resized_addr(6 downto 0) <= wb_adr_i;
resized_addr(c_wishbone_address_width-1 downto 7) <= (others => '0');
U_Adapter : wb_slave_adapter
generic map(
......@@ -198,12 +211,12 @@ begin -- rtl
master_i => wb_out,
master_o => wb_in,
sl_adr_i => resized_addr,
sl_dat_i => wb_data_i,
sl_dat_i => wb_dat_i,
sl_sel_i => wb_sel_i,
sl_cyc_i => wb_cyc_i,
sl_stb_i => wb_stb_i,
sl_we_i => wb_we_i,
sl_dat_o => wb_data_o,
sl_dat_o => wb_dat_o,
sl_ack_o => wb_ack_o,
sl_stall_o => wb_stall_o);
......@@ -323,7 +336,7 @@ begin -- rtl
deglitch_threshold_i => deglitch_thr_slv,
dbg_dmtdout_o => open);
DMTD_AUX : dmtd_with_deglitcher
DMTD_AUX : dmtd_with_deglitcher
generic map (
g_counter_bits => g_tag_bits)
port map (
......@@ -393,7 +406,7 @@ begin -- rtl
port map (
rst_n_i => rst_n_i,
wb_clk_i => clk_sys_i,
wb_addr_i => wb_in.adr(3 downto 0),
wb_addr_i => wb_in.adr(4 downto 0),
wb_data_i => wb_in.dat,
wb_data_o => wb_out.dat,
wb_cyc_i => wb_in.cyc,
......@@ -416,8 +429,16 @@ begin -- rtl
spll_dac_hpll_o => spll_dac_hpll,
spll_dac_hpll_wr_o => spll_dac_hpll_wr,
spll_dac_dmpll_o => spll_dac_dmpll,
spll_dac_dmpll_wr_o => spll_dac_dmpll_wr,
spll_dac_aux_o => spll_dac_aux,
spll_dac_aux_wr_o => spll_dac_aux_wr,
spll_csr_aux_en_i => clk_aux_lock_en_i,
spll_csr_aux_lock_o => clk_aux_locked_o,
spll_deglitch_thr_o => deglitch_thr_slv,
irq_tag_i => irq_tag);
......@@ -428,6 +449,9 @@ begin -- rtl
dac_dmpll_load_o <= spll_dac_dmpll_wr;
dac_dmpll_data_o <= spll_dac_dmpll;
dac_aux_load_o <= spll_dac_aux_wr;
dac_aux_data_o <= spll_dac_aux;
collect_tags : process(clk_sys_i)
begin
if rising_edge(clk_sys_i) then
......@@ -435,6 +459,7 @@ begin -- rtl
spll_per_hpll <= (others => '0');
spll_tag_ref <= (others => '0');
spll_tag_fb <= (others => '0');
spll_tag_aux <= (others => '0');
spll_csr_tag_rdy <= (others => '0');
else
......@@ -459,7 +484,7 @@ begin -- rtl
spll_csr_tag_rdy(3) <= '0';
end if;
if(tag_aux_p = '1') then
if(tag_aux_p = '1') then
spll_tag_aux <= std_logic_vector(to_unsigned(0, 32-g_tag_bits)) & tag_aux;
spll_csr_tag_rdy(0) <= spll_csr_tag_en(0);
elsif(tag_aux_rd_ack = '1') then
......
modules/wr_softpll/wr_softpll.wb
View file @ 49c340a6
......@@ -26,6 +26,23 @@ peripheral {
access_bus = READ_ONLY;
access_dev = WRITE_ONLY;
};
field {
name = "Aux clock locking enable";
prefix = "AUX_EN";
type = BIT;
access_bus = READ_ONLY;
access_dev = WRITE_ONLY;
};
field {
name = "Aux clock locked flag (to slave)";
prefix = "AUX_LOCK";
type = BIT;
access_bus = READ_WRITE;
access_dev = READ_ONLY;
};
};
reg {
......@@ -106,6 +123,17 @@ peripheral {
type = PASS_THROUGH;
size = 16;
};
};
reg {
name = "AUX DAC Output";
prefix = "DAC_AUX";
field {
name = "DAC value";
type = PASS_THROUGH;
size = 24;
};
};
reg {
......
modules/wr_softpll/xwb_wr_softpll.vhd → modules/wr_softpll/xwr_softpll.vhd
View file @ 49c340a6
......@@ -5,7 +5,7 @@ use ieee.numeric_std.all;
use work.gencores_pkg.all;
use work.wishbone_pkg.all;
entity xwb_wr_softpll is
entity xwr_softpll is
generic(
g_deglitcher_threshold : integer;
g_tag_bits : integer;
......@@ -26,6 +26,12 @@ entity xwb_wr_softpll is
dac_dmpll_data_o : out std_logic_vector(15 downto 0);
dac_dmpll_load_o : out std_logic;
dac_aux_data_o : out std_logic_vector(23 downto 0);
dac_aux_load_o : out std_logic;
clk_aux_lock_en_i : in std_logic := '0';
clk_aux_locked_o : out std_logic;
slave_i : in t_wishbone_slave_in;
slave_o : out t_wishbone_slave_out;
......@@ -33,9 +39,9 @@ entity xwb_wr_softpll is
debug_o : out std_logic_vector(3 downto 0)
);
end wr_softpll;
end xwr_softpll;
architecture behavioral of xwb_wr_softpll is
architecture wrapper of xwr_softpll is
component wr_softpll is
generic(
......@@ -55,9 +61,13 @@ architecture behavioral of xwb_wr_softpll is
dac_hpll_load_o : out std_logic;
dac_dmpll_data_o : out std_logic_vector(15 downto 0);
dac_dmpll_load_o : out std_logic;
wb_addr_i : in std_logic_vector(5 downto 0);
wb_data_i : in std_logic_vector(31 downto 0);
wb_data_o : out std_logic_vector(31 downto 0);
dac_aux_data_o : out std_logic_vector(23 downto 0);
dac_aux_load_o : out std_logic;
clk_aux_lock_en_i : in std_logic;
clk_aux_locked_o : out std_logic;
wb_adr_i : in std_logic_vector(6 downto 0);
wb_dat_i : in std_logic_vector(31 downto 0);
wb_dat_o : out std_logic_vector(31 downto 0);
wb_cyc_i : in std_logic;
wb_sel_i : in std_logic_vector(3 downto 0);
wb_stb_i : in std_logic;
......@@ -75,10 +85,9 @@ begin -- behavioral
generic map(
g_deglitcher_threshold => g_deglitcher_threshold,
g_tag_bits => g_tag_bits,
g_interface_mode => CLASSIC;
g_address_granularity => WORD
);
port(
g_interface_mode => g_interface_mode,
g_address_granularity => g_address_granularity)
port map (
clk_sys_i => clk_sys_i,
rst_n_i => rst_n_i,
clk_ref_i => clk_ref_i,
......@@ -89,9 +98,13 @@ begin -- behavioral
dac_hpll_load_o => dac_hpll_load_o,
dac_dmpll_data_o => dac_dmpll_data_o,
dac_dmpll_load_o => dac_dmpll_load_o,
wb_addr_i => slave_i.adr(5 downto 0);
wb_data_i => slave_i.dat,
wb_data_o => slave_o.dat,
dac_aux_load_o => dac_aux_load_o,
dac_aux_data_o => dac_aux_data_o,
clk_aux_locked_o => clk_aux_locked_o,
clk_aux_lock_en_i => clk_aux_lock_en_i,
wb_adr_i => slave_i.adr(6 downto 0),
wb_dat_i => slave_i.dat,
wb_dat_o => slave_o.dat,
wb_cyc_i => slave_i.cyc,
wb_sel_i => slave_i.sel,
wb_stb_i => slave_i.stb,
......@@ -102,4 +115,4 @@ begin -- behavioral
debug_o => debug_o
);
end behavioral;
end wrapper;
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