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White Rabbit core collection
Commit 41b25aba authored by Tomasz Wlostowski's avatar Tomasz Wlostowski Committed by Grzegorz Daniluk
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wr_gtx_phy_kintex7_lp: wip

parent 4b0e3748
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Showing with 165 additions and 126 deletions
platform/xilinx/wr_gtp_phy/kintex7-lp/gtx_comma_detect_lp.vhd
View file @ 41b25aba
......@@ -11,7 +11,7 @@ entity gtx_comma_detect_kintex7_lp is
clk_rx_i : in std_logic;
rst_i : in std_logic;
rx_data_raw_i : in std_logic_vector(39 downto 0);
rx_data_raw_i : in std_logic_vector(19 downto 0);
comma_target_pos_i : in std_logic_vector(7 downto 0);
comma_current_pos_o : out std_logic_vector(7 downto 0);
......@@ -32,13 +32,13 @@ architecture rtl of gtx_comma_detect_kintex7_lp is
constant c_COMMA_SHIFT_WE_WANT : std_logic_vector(6 downto 0) := "0110000";
-- fixme
signal rx_data_d0, rx_data_d1 : std_logic_vector(39 downto 0);
signal rx_data_merged : std_logic_vector(40*3-1 downto 0);
signal rx_data_d0 : std_logic_vector(19 downto 0);
signal rx_data_merged : std_logic_vector(39 downto 0);
signal first_comma : std_logic_vector(7 downto 0);
signal cnt : unsigned(15 downto 0);
signal state : t_state;
signal comma_found : std_logic_vector(70 downto 0);
signal comma_found : std_logic_vector(19 downto 0);
component chipscope_ila_v6 is
port (
......@@ -68,18 +68,6 @@ architecture rtl of gtx_comma_detect_kintex7_lp is
return std_logic_vector(to_unsigned(0, output_bits));
end f_onehot_encode;
function f_decimate(x: std_logic_vector; first : integer; count:integer;step:integer) return std_logic_vector is
variable rv: std_logic_vector(count -1 downto 0);
begin
for i in 0 to count-1 loop
rv(i) := x(first + step * i);
end loop;
return rv;
end function;
constant c_K28_5_PLUS : std_logic_vector(9 downto 0) := "1010000011";
signal comma_pos : std_logic_vector(7 downto 0);
......@@ -122,18 +110,11 @@ begin
if rst_i = '1' then
comma_found <= (others => '0');
else
rx_data_d0 <= rx_data_raw_i;
rx_data_d1 <= rx_data_d0;
rx_data_merged <= rx_data_d1 & rx_data_d0 & rx_data_raw_i;
-- 1 8b10b bit= 4 oversampled bits
for i in 0 to 70 loop
lookup := f_decimate(rx_data_merged, i, 10, 4 );
if lookup = c_K28_5_PLUS or
lookup = (not c_K28_5_PLUS) then
rx_data_merged(39 downto 0) <= rx_data_d0 & rx_data_raw_i;
for i in 0 to 19 loop
if rx_data_merged(i + 9 downto i) = c_K28_5_PLUS or
rx_data_merged(i + 9 downto i) = (not c_K28_5_PLUS) then
comma_found(i) <= '1';
else
comma_found(i) <= '0';
......
platform/xilinx/wr_gtp_phy/kintex7-lp/gtxe2_lp.vhd
View file @ 41b25aba
......@@ -113,7 +113,7 @@ port
RXUSRCLK_IN : in std_logic;
RXUSRCLK2_IN : in std_logic;
------------------ Receive Ports - FPGA RX interface Ports -----------------
RXDATA_OUT : out std_logic_vector(39 downto 0);
rxdata_out : out std_logic_vector(19 downto 0);
--------------------------- Receive Ports - RX AFE -------------------------
GTXRXP_IN : in std_logic;
------------------------ Receive Ports - RX AFE Ports ----------------------
......@@ -135,7 +135,7 @@ port
TXUSRCLK_IN : in std_logic;
TXUSRCLK2_IN : in std_logic;
------------------ Transmit Ports - TX Data Path interface -----------------
TXDATA_IN : in std_logic_vector(39 downto 0);
txdata_in : in std_logic_vector(79 downto 0);
---------------- Transmit Ports - TX Driver and OOB signaling --------------
GTXTXN_OUT : out std_logic;
GTXTXP_OUT : out std_logic;
......@@ -169,16 +169,16 @@ architecture RTL of whiterabbit_gtxe2_channel_wrapper_GT is
-- RX Datapath signals
signal rxdata_i : std_logic_vector(63 downto 0);
signal rxchariscomma_float_i : std_logic_vector(5 downto 0);
signal rxcharisk_i : std_logic_vector(7 downto 0);
signal rxdisperr_i : std_logic_vector(7 downto 0);
signal rxnotintable_float_i : std_logic_vector(5 downto 0);
signal rxrundisp_float_i : std_logic_vector(5 downto 0);
signal rxdata_out_i :std_logic_vector(39 downto 0);
signal rxdata_out_i : std_logic_vector(19 downto 0);
signal rxcharisk_i : std_logic_vector(7 downto 0);
signal rxdisperr_i : std_logic_vector(7 downto 0);
-- TX Datapath signals
signal txdata_i : std_logic_vector(63 downto 0);
signal txdata_in_i : std_logic_vector(39 downto 0);
signal txdata_in_i : std_logic_vector(79 downto 0);
signal txchardispmode_i : std_logic_vector(7 downto 0);
signal txchardispval_i : std_logic_vector(7 downto 0);
signal txkerr_float_i : std_logic_vector(2 downto 0);
......@@ -197,25 +197,20 @@ begin
------------------- GT Datapath byte mapping -----------------
--The GT deserializes the rightmost parallel bit (LSb) first
RXDATA_OUT <= rxdata_out_i(39 downto 0);
RXDATA_OUT <= rxdata_out_i(19 downto 0);
--The GT serializes the rightmost parallel bit (LSb) first
txdata_in_i <= TXDATA_IN;
------------- GT RXDATA Assignments for 20 bit datapath -------
------------- GT RXDATA Assignments for 40 bit datapath -------
rxdata_out_i <= (rxdisperr_i(3) & rxcharisk_i(3) & rxdata_i(31 downto 24) &
rxdisperr_i(2) & rxcharisk_i(2) & rxdata_i(23 downto 16) &
rxdisperr_i(1) & rxcharisk_i(1) & rxdata_i(15 downto 8) &
rxdisperr_i(0) & rxcharisk_i(0) & rxdata_i(7 downto 0) );
rxdata_out_i <= (rxdisperr_i(1) & rxcharisk_i(1) & rxdata_i(15 downto 8) & rxdisperr_i(0) & rxcharisk_i(0) & rxdata_i(7 downto 0));
------------- GT txdata_i Assignments for 40 bit datapath -------
------------- GT txdata_i Assignments for 80 bit datapath -------
txchardispmode_i <= (tied_to_ground_vec_i(3 downto 0) & txdata_in_i(39) & txdata_in_i(29) & txdata_in_i(19) & txdata_in_i(9));
txchardispval_i <= (tied_to_ground_vec_i(3 downto 0) & txdata_in_i(38) & txdata_in_i(28) & txdata_in_i(18) & txdata_in_i(8));
txdata_i <= (tied_to_ground_vec_i(31 downto 0) & txdata_in_i(37 downto 30) & txdata_in_i(27 downto 20) & txdata_in_i(17 downto 10) & txdata_in_i(7 downto 0));
txchardispmode_i <= (txdata_in_i(79) & txdata_in_i(69) & txdata_in_i(59) & txdata_in_i(49) & txdata_in_i(39) & txdata_in_i(29) & txdata_in_i(19) & txdata_in_i(9));
txchardispval_i <= (txdata_in_i(78) & txdata_in_i(68) & txdata_in_i(58) & txdata_in_i(48) & txdata_in_i(38) & txdata_in_i(28) & txdata_in_i(18) & txdata_in_i(8));
txdata_i <= (txdata_in_i(77 downto 70) & txdata_in_i(67 downto 60) & txdata_in_i(57 downto 50) & txdata_in_i(47 downto 40) & txdata_in_i(37 downto 30) & txdata_in_i(27 downto 20) & txdata_in_i(17 downto 10) & txdata_in_i(7 downto 0));
----------------------------- GTXE2 Instance --------------------------
......@@ -255,8 +250,8 @@ begin
CBCC_DATA_SOURCE_SEL => ("ENCODED"),
CLK_COR_SEQ_2_USE => ("FALSE"),
CLK_COR_KEEP_IDLE => ("FALSE"),
CLK_COR_MAX_LAT => (19),
CLK_COR_MIN_LAT => (15),
CLK_COR_MAX_LAT => (9),
CLK_COR_MIN_LAT => (7),
CLK_COR_PRECEDENCE => ("TRUE"),
CLK_COR_REPEAT_WAIT => (0),
CLK_COR_SEQ_LEN => (1),
......@@ -304,7 +299,7 @@ begin
ES_VERT_OFFSET => ("000000000"),
-------------------------FPGA RX Interface Attributes-------------------------
RX_DATA_WIDTH => (40),
RX_DATA_WIDTH => (20),
---------------------------PMA Attributes----------------------------
OUTREFCLK_SEL_INV => ("11"),
......@@ -372,7 +367,7 @@ begin
--For SATA Gen2 GTP- set RXCDR_CFG=83'h0_0000_47FE_2060_2448_1010
--For SATA Gen1 GTP- set RXCDR_CFG=83'h0_0000_47FE_1060_2448_1010
RXCDR_CFG => (x"03000023ff40200020"),
RXCDR_CFG => (x"03000023ff40080020"),
RXCDR_FR_RESET_ON_EIDLE => ('0'),
RXCDR_HOLD_DURING_EIDLE => ('0'),
RXCDR_PH_RESET_ON_EIDLE => ('0'),
......@@ -425,10 +420,10 @@ begin
TXPH_CFG => (x"0780"),
TXPHDLY_CFG => (x"084020"),
TXPH_MONITOR_SEL => ("00000"),
TX_XCLK_SEL => ("TXOUT"),
TX_XCLK_SEL => ("TXUSR"),
-------------------------FPGA TX Interface Attributes-------------------------
TX_DATA_WIDTH => (40),
TX_DATA_WIDTH => (80),
-------------------------TX Configurable Driver Attributes-------------------------
TX_DEEMPH0 => ("00000"),
......@@ -467,7 +462,7 @@ begin
CPLL_INIT_CFG => (x"00001E"),
CPLL_LOCK_CFG => (x"01E8"),
CPLL_REFCLK_DIV => (1),
RXOUT_DIV => (2),
RXOUT_DIV => (8),
TXOUT_DIV => (2),
SATA_CPLL_CFG => ("VCO_3000MHZ"),
......@@ -493,7 +488,7 @@ begin
TX_CLKMUX_PD => ('1'),
-------------------------FPGA RX Interface Attribute-------------------------
RX_INT_DATAWIDTH => (1),
RX_INT_DATAWIDTH => (0),
-------------------------FPGA TX Interface Attribute-------------------------
TX_INT_DATAWIDTH => (1),
......@@ -776,7 +771,7 @@ begin
TXOUTCLK => TXOUTCLK_OUT,
TXOUTCLKFABRIC => TXOUTCLKFABRIC_OUT,
TXOUTCLKPCS => TXOUTCLKPCS_OUT,
TXOUTCLKSEL => "011",
TXOUTCLKSEL => "010",
TXRATEDONE => open,
--------------------- Transmit Ports - TX Gearbox Ports --------------------
TXCHARISK(7 downto 2) => tied_to_ground_vec_i(5 downto 0),
......
platform/xilinx/wr_gtp_phy/kintex7-lp/wr_gtx_phy_kintex7_lp.vhd
View file @ 41b25aba
......@@ -6,7 +6,7 @@
-- Author : Peter Jansweijer, Tomasz Wlostowski
-- Company : CERN BE-CO-HT
-- Created : 2013-04-08
-- Last update: 2019-06-12
-- Last update: 2019-06-14
-- Platform : FPGA-generic
-- Standard : VHDL'93
-------------------------------------------------------------------------------
......@@ -80,10 +80,10 @@ entity wr_gtx_phy_kintex7_lp is
tx_locked_o : out std_logic;
-- data input (8 bits, not 8b10b-encoded)
tx_data_i : in std_logic_vector(7 downto 0);
tx_data_i : in std_logic_vector(15 downto 0);
-- 1 when tx_data_i contains a control code, 0 when it's a data byte
tx_k_i : in std_logic_vector(0 downto 0);
tx_k_i : in std_logic_vector(1 downto 0);
-- disparity of the currently transmitted 8b10b code (1 = plus, 0 = minus).
-- Necessary for the PCS to generate proper frame termination sequences.
......@@ -101,10 +101,10 @@ entity wr_gtx_phy_kintex7_lp is
-- 8b10b-decoded data output. The data output must be kept invalid before
-- the transceiver is locked on the incoming signal to prevent the EP from
-- detecting a false carrier.
rx_data_o : out std_logic_vector(7 downto 0);
rx_data_o : out std_logic_vector(15 downto 0);
-- 1 when the byte on rx_data_o is a control code
rx_k_o : out std_logic_vector(0 downto 0);
rx_k_o : out std_logic_vector(1 downto 0);
-- encoding error indication
rx_enc_err_o : out std_logic;
......@@ -187,16 +187,22 @@ architecture rtl of wr_gtx_phy_kintex7_lp is
signal rst_done : std_logic;
signal rst_done_n : std_logic;
signal rx_k_o_int : std_logic_vector(0 downto 0);
signal rx_data_o_int : std_logic_vector(7 downto 0);
signal rx_k_int : std_logic_vector(0 downto 0);
signal rx_data_int : std_logic_vector(7 downto 0);
signal rx_k_o_int : std_logic_vector(1 downto 0);
signal rx_data_o_int : std_logic_vector(15 downto 0);
signal rx_k_int : std_logic_vector(1 downto 0);
signal rx_data_int : std_logic_vector(15 downto 0);
signal rx_data_wrap : std_logic_vector(15 downto 0);
signal rx_charisk_wrap : std_logic_vector(1 downto 0);
signal rx_disperr_wrap : std_logic_vector(1 downto 0);
signal rx_data_raw : std_logic_vector(19 downto 0);
signal rx_enc_err_o_int : std_logic;
signal rx_disp_err, rx_code_err : std_logic_vector(1 downto 0);
signal tx_is_k_swapped : std_logic_vector(0 downto 0);
signal tx_data_swapped : std_logic_vector(7 downto 0);
signal tx_is_k_swapped : std_logic_vector(1 downto 0);
signal tx_data_swapped : std_logic_vector(15 downto 0);
signal cur_disp : t_8b10b_disparity;
......@@ -215,10 +221,7 @@ architecture rtl of wr_gtx_phy_kintex7_lp is
signal rx_rec_clk_sampled, tx_out_clk_sampled : std_logic;
signal gtx_loopback : std_logic_vector(2 downto 0);
signal rx_data_raw : std_logic_vector(39 downto 0);
signal tx_data_8b10b : std_logic_vector(9 downto 0);
signal tx_data_8b10b : std_logic_vector(19 downto 0);
function f_widen(x : std_logic_vector; ratio : integer) return std_logic_vector is
variable rv : std_logic_vector(x'length * ratio -1 downto 0);
......@@ -230,19 +233,17 @@ architecture rtl of wr_gtx_phy_kintex7_lp is
return rv;
end function;
function f_decimate(x: std_logic_vector; first : integer; count:integer;step:integer) return std_logic_vector is
variable rv: std_logic_vector(count -1 downto 0);
begin
for i in 0 to count-1 loop
rv(i) := x(first + step * i);
end loop;
return rv;
end function;
signal comma_target_pos : std_logic_vector(7 downto 0);
signal comma_current_pos : std_logic_vector(7 downto 0);
signal tx_out_clk_div2 : std_logic;
signal gtx_rst_n_txdiv2 : std_logic;
signal run_disparity_q0, run_disparity_q1 : std_logic;
signal run_disparity_reg : std_logic;
signal pll_clkfbout_bufin,tx_out_clk_div2_bufin, pll_clkfbout : std_logic;
begin -- rtl
......@@ -263,6 +264,16 @@ begin -- rtl
synced_o => tx_enable_refclk
);
U_SyncTxUsrcCLK2Reset : gc_sync_ffs
port map
(
clk_i => tx_out_clk_div2,
rst_n_i => gtx_rst_n,
data_i => '1',
synced_o => gtx_rst_n_txdiv2
);
U_SyncRxEnable : gc_sync_ffs
port map
(
......@@ -350,12 +361,8 @@ begin -- rtl
tx_enc_err_o <= '0';
U_BUF_TxOutClk : BUFG
port map (
I => tx_out_clk_bufin,
O => tx_out_clk);
tx_clk_o <= tx_out_clk;
tx_clk_o <= tx_out_clk_div2;
tx_locked_o <= qpll_locked_i;
U_BUF_RxRecClk : BUFG
......@@ -367,12 +374,39 @@ begin -- rtl
U_Enc1 : entity work.gc_enc_8b10b
port map (
clk_i => tx_out_clk,
rst_n_i => gtx_rst_n,
in_8b_i => tx_data_i,
clk_i => tx_out_clk_div2,
rst_n_i => gtx_rst_n_txdiv2,
in_8b_i => tx_data_i(15 downto 8),
dispar_i => run_disparity_reg,
dispar_o => run_disparity_q0,
ctrl_i => tx_k_i(1),
out_10b_o => tx_data_8b10b(19 downto 10));
U_Enc2 : entity work.gc_enc_8b10b
port map (
clk_i => tx_out_clk_div2,
rst_n_i => gtx_rst_n_txdiv2,
in_8b_i => tx_data_i(7 downto 0),
dispar_i => run_disparity_q0,
dispar_o => run_disparity_q1,
ctrl_i => tx_k_i(0),
out_10b_o => tx_data_8b10b);
out_10b_o => tx_data_8b10b(9 downto 0));
p_latch_disparity : process(tx_out_clk_div2)
begin
if rising_edge(tx_out_clk_div2) then
if tx_sw_reset = '1' then
run_disparity_reg <= '0';
else
run_disparity_reg <= run_disparity_q1;
end if;
end if;
end process;
U_GTX_INST : entity work.WHITERABBIT_GTXE2_CHANNEL_WRAPPER_GT
generic map
......@@ -435,7 +469,7 @@ begin -- rtl
TXUSERRDY_IN => qpll_locked_i,
------------------ Transmit Ports - FPGA TX Interface Ports ----------------
TXUSRCLK_IN => tx_out_clk,
TXUSRCLK2_IN => tx_out_clk,
TXUSRCLK2_IN => tx_out_clk_div2,
------------------ Transmit Ports - TX Data Path interface -----------------
TXDATA_IN => f_widen(tx_data_8b10b, 4),
---------------- Transmit Ports - TX Driver and OOB signaling --------------
......@@ -451,7 +485,48 @@ begin -- rtl
TXPRBSSEL_IN => "000" --tx_prbs_sel_i
);
U_GenTxUsrClk : PLLE2_ADV
generic map (
BANDWIDTH =>"HIGH",
COMPENSATION => "ZHOLD",
STARTUP_WAIT => "FALSE",
DIVCLK_DIVIDE => 1,
CLKFBOUT_MULT => 14,
CLKFBOUT_PHASE => 0.000,
CLKOUT0_DIVIDE => 28,
CLKOUT0_PHASE => 0.000,
CLKOUT0_DUTY_CYCLE => 0.500,
CLKIN1_PERIOD => 8.000)
port map (
CLKFBOUT => pll_clkfbout_bufin,
CLKOUT0 => tx_out_clk_div2_bufin,
CLKFBIN => pll_clkfbout,
CLKIN1 => tx_out_clk,
CLKIN2 => '0',
CLKINSEL => '1',
DADDR => "0000000",
DI => x"0000",
DWE => '0',
PWRDWN => '0',
DCLK => '0',
DEN => '0',
RST => gtx_tx_reset_a);
U_BUF_TxOutClk : BUFG
port map (
I => tx_out_clk_bufin,
O => tx_out_clk);
U_BUF_TxOutClk2 : BUFG
port map (
I => tx_out_clk_div2_bufin,
O => tx_out_clk_div2);
U_BUF_TxOutClkFB : BUFG
port map (
I => pll_clkfbout_bufin,
O => pll_clkfbout);
txpll_lockdet <= qpll_locked_i;
......@@ -463,18 +538,6 @@ begin -- rtl
rdy_o <= everything_ready;
process(clk_ref_i)
begin
if rising_edge(clk_ref_i) then
if tx_enable_refclk = '0' then
tx_is_k_swapped <= "0";
tx_data_swapped <= (others => '0');
else
tx_is_k_swapped <= tx_k_i;
tx_data_swapped <= tx_data_i(7 downto 0);
end if;
end if;
end process;
......@@ -517,28 +580,28 @@ begin -- rtl
aligned_o => link_aligned);
gtx_rst_n <= not gtx_rst;
U_Dec1 : gc_dec_8b10b
port map (
clk_i => rx_rec_clk,
rst_n_i => gtx_rst_n,
in_10b_i => f_decimate(rx_data_raw, 0, 10, 4),
ctrl_o => rx_k_int(0),
code_err_o => rx_code_err(0),
rdisp_err_o => open,
out_8b_o => rx_data_int(7 downto 0));
-- U_Dec2 : gc_dec_8b10b
-- port map (
-- clk_i => rx_rec_clk,
-- rst_n_i => gtx_rst_n,
-- in_10b_i => (rx_data_raw(9 downto 0)),
-- ctrl_o => rx_k_int(0),
-- code_err_o => rx_code_err(0),
-- rdisp_err_o => open,
-- out_8b_o => rx_data_int(7 downto 0));
U_Dec1 : gc_dec_8b10b
port map (
clk_i => rx_rec_clk,
rst_n_i => gtx_rst_n,
in_10b_i => (rx_data_raw(19 downto 10)),
ctrl_o => rx_k_int(1),
code_err_o => rx_code_err(1),
rdisp_err_o => open,
out_8b_o => rx_data_int(15 downto 8));
U_Dec2 : gc_dec_8b10b
port map (
clk_i => rx_rec_clk,
rst_n_i => gtx_rst_n,
in_10b_i => (rx_data_raw(9 downto 0)),
ctrl_o => rx_k_int(0),
code_err_o => rx_code_err(0),
rdisp_err_o => open,
out_8b_o => rx_data_int(7 downto 0));
rx_disp_err <= (others => '0');
......@@ -555,9 +618,9 @@ begin -- rtl
rx_enc_err_o_int <= '0';
elsif rising_edge(rx_rec_clk) then
if(rx_enable_rxclk = '1') then
rx_data_o_int <= rx_data_int(7 downto 0);
rx_k_o_int <= rx_k_int;
rx_enc_err_o_int <= '0';
rx_data_o_int <= rx_data_int(7 downto 0) & rx_data_int(15 downto 8);
rx_k_o_int <= rx_k_int(0) & rx_k_int(1);
rx_enc_err_o_int <= rx_disp_err(0) or rx_disp_err(1) or rx_code_err(0) or rx_code_err(1);
else
rx_data_o_int <= (others => '1');
rx_k_o_int <= (others => '1');
......@@ -572,7 +635,7 @@ begin -- rtl
if tx_enable_refclk = '0' then
cur_disp <= RD_MINUS;
else
cur_disp <= f_next_8b10b_disparity8(cur_disp, tx_k_i(0), tx_data_i);
cur_disp <= f_next_8b10b_disparity16(cur_disp, tx_k_i, tx_data_i);
end if;
end if;
end process;
......
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