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White Rabbit core collection
Commit 2b4daa08 authored by Pascal Bos's avatar Pascal Bos Committed by Grzegorz Daniluk
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added clbv4 files.

parent 19bab703
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board/Manifest.py
View file @ 2b4daa08
try:
if board in ["spec", "svec", "vfchd", "clbv2", "clbv3", "common"]:
if board in ["spec", "svec", "vfchd", "clbv2", "clbv3", "clbv4", "common"]:
modules = {"local" : [ board ] }
except NameError:
pass
board/clbv4/Manifest.py 0 → 100644
View file @ 2b4daa08
files = [
"wr_clbv4_pkg.vhd",
"xwrc_board_clbv4.vhd",
"wrc_board_clbv4.vhd",
]
modules = {
"local" : [
"../common",
]
}
board/clbv4/wr_clbv4_pkg.vhd 0 → 100644
View file @ 2b4daa08
-------------------------------------------------------------------------------
-- Title : WRPC Wrapper for CLBv4
-- Project : WR PTP Core
-- URL : http://www.ohwr.org/projects/wr-cores/wiki/Wrpc_core
-------------------------------------------------------------------------------
-- File : wr_clbv4_pkg.vhd
-- Author(s) : Pascal Bos
-- Company : Nikhef
-- Created : 2019-06-18
-- Last update: 2019-06-18
-- Standard : VHDL'93
-------------------------------------------------------------------------------
-- Copyright (c) 2017 Nikhef
-------------------------------------------------------------------------------
-- GNU LESSER GENERAL PUBLIC LICENSE
--
-- This source file is free software; you can redistribute it
-- and/or modify it under the terms of the GNU Lesser General
-- Public License as published by the Free Software Foundation;
-- either version 2.1 of the License, or (at your option) any
-- later version.
--
-- This source is distributed in the hope that it will be
-- useful, but WITHOUT ANY WARRANTY; without even the implied
-- warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR
-- PURPOSE. See the GNU Lesser General Public License for more
-- details.
--
-- You should have received a copy of the GNU Lesser General
-- Public License along with this source; if not, download it
-- from http://www.gnu.org/licenses/lgpl-2.1.html
--
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
library work;
use work.wishbone_pkg.all;
use work.wrcore_pkg.all;
use work.wr_fabric_pkg.all;
use work.endpoint_pkg.all;
use work.wr_board_pkg.all;
use work.streamers_pkg.all;
package wr_CLBv4_pkg is
component xwrc_board_clbv4 is
generic (
g_simulation : integer := 0;
g_with_external_clock_input : boolean := TRUE;
g_aux_clks : integer := 0;
g_fabric_iface : t_board_fabric_iface := plain;
g_streamers_op_mode : t_streamers_op_mode := TX_AND_RX;
g_tx_streamer_params : t_tx_streamer_params := c_tx_streamer_params_defaut;
g_rx_streamer_params : t_rx_streamer_params := c_rx_streamer_params_defaut;
g_dpram_initf : string := "default_xilinx";
g_diag_id : integer := 0;
g_diag_ver : integer := 0;
g_diag_ro_size : integer := 0;
g_diag_rw_size : integer := 0);
port (
areset_n_i : in std_logic;
areset_edge_n_i : in std_logic := '1';
clk_125m_dmtd_n_i : in std_logic;
clk_125m_dmtd_p_i : in std_logic;
clk_125m_gtx_n_i : in std_logic;
clk_125m_gtx_p_i : in std_logic;
clk_aux_i : in std_logic_vector(g_aux_clks-1 downto 0) := (others => '0');
clk_10m_ext_i : in std_logic := '0';
pps_ext_i : in std_logic := '0';
clk_sys_62m5_o : out std_logic;
clk_ref_62m5_o : out std_logic;
clk_dmtd_62m5_o : out std_logic;
rst_sys_62m5_n_o : out std_logic;
rst_ref_62m5_n_o : out std_logic;
dac_refclk_cs_n_o : out std_logic;
dac_refclk_sclk_o : out std_logic;
dac_refclk_din_o : out std_logic;
dac_dmtd_cs_n_o : out std_logic;
dac_dmtd_sclk_o : out std_logic;
dac_dmtd_din_o : out std_logic;
sfp_txp_o : out std_logic;
sfp_txn_o : out std_logic;
sfp_rxp_i : in std_logic;
sfp_rxn_i : in std_logic;
sfp_det_i : in std_logic := '1';
sfp_sda_i : in std_logic;
sfp_sda_o : out std_logic;
sfp_scl_i : in std_logic;
sfp_scl_o : out std_logic;
sfp_rate_select_o : out std_logic;
sfp_tx_fault_i : in std_logic := '0';
sfp_tx_disable_o : out std_logic;
sfp_los_i : in std_logic := '0';
eeprom_sda_i : in std_logic;
eeprom_sda_o : out std_logic;
eeprom_scl_i : in std_logic;
eeprom_scl_o : out std_logic;
onewire_i : in std_logic;
onewire_oen_o : out std_logic;
uart_rxd_i : in std_logic;
uart_txd_o : out std_logic;
wrf_src_o : out t_wrf_source_out;
wrf_src_i : in t_wrf_source_in := c_dummy_src_in;
wrf_snk_o : out t_wrf_sink_out;
wrf_snk_i : in t_wrf_sink_in := c_dummy_snk_in;
wrs_tx_data_i : in std_logic_vector(g_tx_streamer_params.data_width-1 downto 0) := (others => '0');
wrs_tx_valid_i : in std_logic := '0';
wrs_tx_dreq_o : out std_logic;
wrs_tx_last_i : in std_logic := '1';
wrs_tx_flush_i : in std_logic := '0';
wrs_tx_cfg_i : in t_tx_streamer_cfg := c_tx_streamer_cfg_default;
wrs_rx_first_o : out std_logic;
wrs_rx_last_o : out std_logic;
wrs_rx_data_o : out std_logic_vector(g_rx_streamer_params.data_width-1 downto 0);
wrs_rx_valid_o : out std_logic;
wrs_rx_dreq_i : in std_logic := '0';
wrs_rx_cfg_i : in t_rx_streamer_cfg := c_rx_streamer_cfg_default;
aux_diag_i : in t_generic_word_array(g_diag_ro_size-1 downto 0) := (others => (others => '0'));
aux_diag_o : out t_generic_word_array(g_diag_rw_size-1 downto 0);
tm_dac_value_o : out std_logic_vector(23 downto 0);
tm_dac_wr_o : out std_logic_vector(g_aux_clks-1 downto 0);
tm_clk_aux_lock_en_i : in std_logic_vector(g_aux_clks-1 downto 0) := (others => '0');
tm_clk_aux_locked_o : out std_logic_vector(g_aux_clks-1 downto 0);
timestamps_o : out t_txtsu_timestamp;
timestamps_ack_i : in std_logic := '1';
abscal_txts_o : out std_logic;
abscal_rxts_o : out std_logic;
fc_tx_pause_req_i : in std_logic := '0';
fc_tx_pause_delay_i : in std_logic_vector(15 downto 0) := x"0000";
fc_tx_pause_ready_o : out std_logic;
tm_link_up_o : out std_logic;
tm_time_valid_o : out std_logic;
tm_tai_o : out std_logic_vector(39 downto 0);
tm_cycles_o : out std_logic_vector(27 downto 0);
led_act_o : out std_logic;
led_link_o : out std_logic;
btn1_i : in std_logic := '1';
btn2_i : in std_logic := '1';
pps_p_o : out std_logic;
pps_led_o : out std_logic;
link_ok_o : out std_logic);
end component xwrc_board_clbv4;
component wrc_board_clbv4 is
generic (
g_simulation : integer := 0;
g_with_external_clock_input : integer := 1;
g_aux_clks : integer := 0;
g_fabric_iface : string := "PLAINFBRC";
g_streamers_op_mode : t_streamers_op_mode := TX_AND_RX;
g_tx_streamer_params : t_tx_streamer_params := c_tx_streamer_params_defaut;
g_rx_streamer_params : t_rx_streamer_params := c_rx_streamer_params_defaut;
g_dpram_initf : string := "default_xilinx";
g_diag_id : integer := 0;
g_diag_ver : integer := 0;
g_diag_ro_vector_width : integer := 0;
g_diag_rw_vector_width : integer := 0);
port (
areset_n_i : in std_logic;
areset_edge_n_i : in std_logic := '1';
clk_125m_dmtd_n_i : in std_logic;
clk_125m_dmtd_p_i : in std_logic;
clk_125m_gtp_n_i : in std_logic;
clk_125m_gtp_p_i : in std_logic;
clk_10m_ext_i : in std_logic := '0';
pps_ext_i : in std_logic := '0';
clk_sys_62m5_o : out std_logic;
clk_ref_62m5_o : out std_logic;
rst_sys_62m5_n_o : out std_logic;
rst_ref_62m5_n_o : out std_logic;
dac_refclk_cs_n_o : out std_logic;
dac_refclk_sclk_o : out std_logic;
dac_refclk_din_o : out std_logic;
dac_dmtd_cs_n_o : out std_logic;
dac_dmtd_sclk_o : out std_logic;
dac_dmtd_din_o : out std_logic;
sfp_txp_o : out std_logic;
sfp_txn_o : out std_logic;
sfp_rxp_i : in std_logic;
sfp_rxn_i : in std_logic;
sfp_det_i : in std_logic := '1';
sfp_sda_i : in std_logic;
sfp_sda_o : out std_logic;
sfp_scl_i : in std_logic;
sfp_scl_o : out std_logic;
sfp_rate_select_o : out std_logic;
sfp_tx_fault_i : in std_logic := '0';
sfp_tx_disable_o : out std_logic;
sfp_los_i : in std_logic := '0';
eeprom_sda_i : in std_logic;
eeprom_sda_o : out std_logic;
eeprom_scl_i : in std_logic;
eeprom_scl_o : out std_logic;
onewire_i : in std_logic;
onewire_oen_o : out std_logic;
uart_rxd_i : in std_logic;
uart_txd_o : out std_logic;
flash_sclk_o : out std_logic;
flash_ncs_o : out std_logic;
flash_mosi_o : out std_logic;
flash_miso_i : in std_logic;
wb_adr_i : in std_logic_vector(c_wishbone_address_width-1 downto 0) := (others => '0');
wb_dat_i : in std_logic_vector(c_wishbone_data_width-1 downto 0) := (others => '0');
wb_dat_o : out std_logic_vector(c_wishbone_data_width-1 downto 0);
wb_sel_i : in std_logic_vector(c_wishbone_address_width/8-1 downto 0) := (others => '0');
wb_we_i : in std_logic := '0';
wb_cyc_i : in std_logic := '0';
wb_stb_i : in std_logic := '0';
wb_ack_o : out std_logic;
wb_int_o : out std_logic;
wb_err_o : out std_logic;
wb_rty_o : out std_logic;
wb_stall_o : out std_logic;
aux_master_adr_o : out std_logic_vector(c_wishbone_address_width-1 downto 0);
aux_master_dat_o : out std_logic_vector(c_wishbone_data_width-1 downto 0);
aux_master_dat_i : in std_logic_vector(c_wishbone_data_width-1 downto 0) := (others => '0');
aux_master_sel_o : out std_logic_vector(c_wishbone_address_width/8-1 downto 0);
aux_master_we_o : out std_logic;
aux_master_cyc_o : out std_logic;
aux_master_stb_o : out std_logic;
aux_master_ack_i : in std_logic := '0';
aux_master_int_i : in std_logic := '0';
aux_master_err_i : in std_logic := '0';
aux_master_rty_i : in std_logic := '0';
aux_master_stall_i : in std_logic := '0';
wrf_src_adr_o : out std_logic_vector(1 downto 0);
wrf_src_dat_o : out std_logic_vector(15 downto 0);
wrf_src_cyc_o : out std_logic;
wrf_src_stb_o : out std_logic;
wrf_src_we_o : out std_logic;
wrf_src_sel_o : out std_logic_vector(1 downto 0);
wrf_src_ack_i : in std_logic;
wrf_src_stall_i : in std_logic;
wrf_src_err_i : in std_logic;
wrf_src_rty_i : in std_logic;
wrf_snk_adr_i : in std_logic_vector(1 downto 0);
wrf_snk_dat_i : in std_logic_vector(15 downto 0);
wrf_snk_cyc_i : in std_logic;
wrf_snk_stb_i : in std_logic;
wrf_snk_we_i : in std_logic;
wrf_snk_sel_i : in std_logic_vector(1 downto 0);
wrf_snk_ack_o : out std_logic;
wrf_snk_stall_o : out std_logic;
wrf_snk_err_o : out std_logic;
wrf_snk_rty_o : out std_logic;
wrs_tx_data_i : in std_logic_vector(g_tx_streamer_params.data_width-1 downto 0) := (others => '0');
wrs_tx_valid_i : in std_logic := '0';
wrs_tx_dreq_o : out std_logic;
wrs_tx_last_i : in std_logic := '1';
wrs_tx_flush_i : in std_logic := '0';
wrs_tx_cfg_mac_l_i : in std_logic_vector(47 downto 0) := x"000000000000";
wrs_tx_cfg_mac_t_i : in std_logic_vector(47 downto 0) := x"ffffffffffff";
wrs_tx_cfg_etype_i : in std_logic_vector(15 downto 0) := x"dbff";
wrs_rx_first_o : out std_logic;
wrs_rx_last_o : out std_logic;
wrs_rx_data_o : out std_logic_vector(g_rx_streamer_params.data_width-1 downto 0);
wrs_rx_valid_o : out std_logic;
wrs_rx_dreq_i : in std_logic := '0';
wrs_rx_cfg_mac_l_i : in std_logic_vector(47 downto 0) := x"000000000000";
wrs_rx_cfg_mac_r_i : in std_logic_vector(47 downto 0) := x"000000000000";
wrs_rx_cfg_etype_i : in std_logic_vector(15 downto 0) := x"dbff";
wrs_rx_cfg_acc_b_i : in std_logic := '1';
wrs_rx_cfg_flt_r_i : in std_logic := '0';
wrs_rx_cfg_fix_l_i : in std_logic_vector(27 downto 0) := x"0000000";
wb_eth_adr_o : out std_logic_vector(c_wishbone_address_width-1 downto 0);
wb_eth_dat_o : out std_logic_vector(c_wishbone_data_width-1 downto 0);
wb_eth_dat_i : in std_logic_vector(c_wishbone_data_width-1 downto 0) := (others => '0');
wb_eth_sel_o : out std_logic_vector(c_wishbone_address_width/8-1 downto 0);
wb_eth_we_o : out std_logic;
wb_eth_cyc_o : out std_logic;
wb_eth_stb_o : out std_logic;
wb_eth_ack_i : in std_logic := '0';
wb_eth_int_i : in std_logic := '0';
wb_eth_err_i : in std_logic := '0';
wb_eth_rty_i : in std_logic := '0';
wb_eth_stall_i : in std_logic := '0';
aux_diag_i : in std_logic_vector(g_diag_ro_vector_width - 1 downto 0) := (others => '0');
aux_diag_o : out std_logic_vector(g_diag_rw_vector_width - 1 downto 0) := (others => '0');
tm_dac_value_o : out std_logic_vector(23 downto 0);
tm_dac_wr_o : out std_logic_vector(g_aux_clks-1 downto 0);
tm_clk_aux_lock_en_i : in std_logic_vector(g_aux_clks-1 downto 0) := (others => '0');
tm_clk_aux_locked_o : out std_logic_vector(g_aux_clks-1 downto 0);
tstamps_stb_o : out std_logic;
tstamps_tsval_o : out std_logic_vector(31 downto 0);
tstamps_port_id_o : out std_logic_vector(5 downto 0);
tstamps_frame_id_o : out std_logic_vector(15 downto 0);
tstamps_incorrect_o : out std_logic;
tstamps_ack_i : in std_logic := '1';
abscal_txts_o : out std_logic;
abscal_rxts_o : out std_logic;
fc_tx_pause_req_i : in std_logic := '0';
fc_tx_pause_delay_i : in std_logic_vector(15 downto 0) := x"0000";
fc_tx_pause_ready_o : out std_logic;
tm_link_up_o : out std_logic;
tm_time_valid_o : out std_logic;
tm_tai_o : out std_logic_vector(39 downto 0);
tm_cycles_o : out std_logic_vector(27 downto 0);
led_act_o : out std_logic;
led_link_o : out std_logic;
btn1_i : in std_logic := '1';
btn2_i : in std_logic := '1';
pps_p_o : out std_logic;
pps_led_o : out std_logic;
link_ok_o : out std_logic);
end component wrc_board_clbv4;
end wr_clbv4_pkg;
board/clbv4/wrc_board_clbv4.vhd 0 → 100644
View file @ 2b4daa08
-------------------------------------------------------------------------------
-- Title : WRPC Wrapper for clbv4
-- Project : WR PTP Core
-- URL : http://www.ohwr.org/projects/wr-cores/wiki/Wrpc_core
-------------------------------------------------------------------------------
-- File : wrc_board_clbv4.vhd
-- Author(s) : Pascal Bos <bosp@nikhef.nl>
-- Company : Nikhef
-- Created : 2019-05-22
-- Last update: 2019-05-22
-- Standard : VHDL'93
-------------------------------------------------------------------------------
-- Description: Top-level wrapper for WR PTP core including all the modules
-- needed to operate the core on the clbv4 board.
-- Version with no VHDL records on the top-level (mainly for Verilog
-- instantiation).
-------------------------------------------------------------------------------
-- Copyright (c) 2019 Nikhef
-------------------------------------------------------------------------------
-- GNU LESSER GENERAL PUBLIC LICENSE
--
-- This source file is free software; you can redistribute it
-- and/or modify it under the terms of the GNU Lesser General
-- Public License as published by the Free Software Foundation;
-- either version 2.1 of the License, or (at your option) any
-- later version.
--
-- This source is distributed in the hope that it will be
-- useful, but WITHOUT ANY WARRANTY; without even the implied
-- warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR
-- PURPOSE. See the GNU Lesser General Public License for more
-- details.
--
-- You should have received a copy of the GNU Lesser General
-- Public License along with this source; if not, download it
-- from http://www.gnu.org/licenses/lgpl-2.1.html
--
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
library work;
use work.gencores_pkg.all;
use work.wrcore_pkg.all;
use work.wishbone_pkg.all;
use work.etherbone_pkg.all;
use work.wr_fabric_pkg.all;
use work.endpoint_pkg.all;
use work.streamers_pkg.all;
use work.wr_xilinx_pkg.all;
use work.wr_board_pkg.all;
use work.wr_clbv4_pkg.all;
entity wrc_board_clbv4 is
generic(
-- set to 1 to speed up some initialization processes during simulation
g_simulation : integer := 0;
-- Select whether to include external ref clock input
g_with_external_clock_input : integer := 1;
-- Number of aux clocks syntonized by WRPC to WR timebase
g_aux_clks : integer := 0;
-- "plainfbrc" = expose WRC fabric interface
-- "streamers" = attach WRC streamers to fabric interface
-- "etherbone" = attach Etherbone slave to fabric interface
g_fabric_iface : string := "plainfbrc";
-- parameters configuration when g_fabric_iface = "streamers" (otherwise ignored)
g_streamers_op_mode : t_streamers_op_mode := TX_AND_RX;
g_tx_streamer_params : t_tx_streamer_params := c_tx_streamer_params_defaut;
g_rx_streamer_params : t_rx_streamer_params := c_rx_streamer_params_defaut;
-- memory initialisation file for embedded CPU
g_dpram_initf : string := "default_xilinx";
-- identification (id and ver) of the layout of words in the generic diag interface
g_diag_id : integer := 0;
g_diag_ver : integer := 0;
-- size the generic diag interface
g_diag_ro_vector_width : integer := 0;
g_diag_rw_vector_width : integer := 0
);
port (
---------------------------------------------------------------------------
-- Clocks/resets
---------------------------------------------------------------------------
-- Reset from system fpga
areset_n_i : in std_logic;
-- Optional reset input active low with rising edge detection. Does not
-- reset PLLs.
areset_edge_n_i : in std_logic := '1';
-- Clock inputs from the board
clk_125m_dmtd_p_i : in std_logic;
clk_125m_dmtd_n_i : in std_logic;
clk_125m_gtp_n_i : in std_logic;
clk_125m_gtp_p_i : in std_logic;
-- 10MHz ext ref clock input (g_with_external_clock_input = TRUE)
clk_10m_ext_i : in std_logic := '0';
-- External PPS input (g_with_external_clock_input = TRUE)
pps_ext_i : in std_logic := '0';
-- 62.5MHz sys clock output
clk_sys_62m5_o : out std_logic;
-- 125MHz ref clock output
clk_ref_62m5_o : out std_logic;
-- active low reset outputs, synchronous to 62m5 and 125m clocks
rst_sys_62m5_n_o : out std_logic;
rst_ref_62m5_n_o : out std_logic;
---------------------------------------------------------------------------
-- Shared SPI interface to DACs
---------------------------------------------------------------------------
dac_refclk_cs_n_o : out std_logic;
dac_refclk_sclk_o : out std_logic;
dac_refclk_din_o : out std_logic;
dac_dmtd_cs_n_o : out std_logic;
dac_dmtd_sclk_o : out std_logic;
dac_dmtd_din_o : out std_logic;
---------------------------------------------------------------------------
-- SFP I/O for transceiver and SFP management info
---------------------------------------------------------------------------
sfp_txp_o : out std_logic;
sfp_txn_o : out std_logic;
sfp_rxp_i : in std_logic;
sfp_rxn_i : in std_logic;
sfp_det_i : in std_logic := '1';
sfp_sda_i : in std_logic;
sfp_sda_o : out std_logic;
sfp_scl_i : in std_logic;
sfp_scl_o : out std_logic;
sfp_rate_select_o : out std_logic;
sfp_tx_fault_i : in std_logic := '0';
sfp_tx_disable_o : out std_logic;
sfp_los_i : in std_logic := '0';
---------------------------------------------------------------------------
-- I2C EEPROM
---------------------------------------------------------------------------
eeprom_sda_i : in std_logic;
eeprom_sda_o : out std_logic;
eeprom_scl_i : in std_logic;
eeprom_scl_o : out std_logic;
---------------------------------------------------------------------------
-- Onewire interface
---------------------------------------------------------------------------
onewire_i : in std_logic;
onewire_oen_o : out std_logic;
---------------------------------------------------------------------------
-- UART
---------------------------------------------------------------------------
uart_rxd_i : in std_logic;
uart_txd_o : out std_logic;
---------------------------------------------------------------------------
-- No Flash memory SPI interface
---------------------------------------------------------------------------
---------------------------------------------------------------------------
-- External WB interface
---------------------------------------------------------------------------
wb_adr_i : in std_logic_vector(c_wishbone_address_width-1 downto 0) := (others => '0');
wb_dat_i : in std_logic_vector(c_wishbone_data_width-1 downto 0) := (others => '0');
wb_dat_o : out std_logic_vector(c_wishbone_data_width-1 downto 0);
wb_sel_i : in std_logic_vector(c_wishbone_address_width/8-1 downto 0) := (others => '0');
wb_we_i : in std_logic := '0';
wb_cyc_i : in std_logic := '0';
wb_stb_i : in std_logic := '0';
wb_ack_o : out std_logic;
wb_int_o : out std_logic;
wb_err_o : out std_logic;
wb_rty_o : out std_logic;
wb_stall_o : out std_logic;
aux_master_adr_o : out std_logic_vector(c_wishbone_address_width-1 downto 0);
aux_master_dat_o : out std_logic_vector(c_wishbone_data_width-1 downto 0);
aux_master_dat_i : in std_logic_vector(c_wishbone_data_width-1 downto 0) := (others => '0');
aux_master_sel_o : out std_logic_vector(c_wishbone_address_width/8-1 downto 0);
aux_master_we_o : out std_logic;
aux_master_cyc_o : out std_logic;
aux_master_stb_o : out std_logic;
aux_master_ack_i : in std_logic := '0';
aux_master_int_i : in std_logic := '0';
aux_master_err_i : in std_logic := '0';
aux_master_rty_i : in std_logic := '0';
aux_master_stall_i : in std_logic := '0';
---------------------------------------------------------------------------
-- WR fabric interface (when g_fabric_iface = "plain")
---------------------------------------------------------------------------
wrf_src_adr_o : out std_logic_vector(1 downto 0);
wrf_src_dat_o : out std_logic_vector(15 downto 0);
wrf_src_cyc_o : out std_logic;
wrf_src_stb_o : out std_logic;
wrf_src_we_o : out std_logic;
wrf_src_sel_o : out std_logic_vector(1 downto 0);
wrf_src_ack_i : in std_logic;
wrf_src_stall_i : in std_logic;
wrf_src_err_i : in std_logic;
wrf_src_rty_i : in std_logic;
wrf_snk_adr_i : in std_logic_vector(1 downto 0);
wrf_snk_dat_i : in std_logic_vector(15 downto 0);
wrf_snk_cyc_i : in std_logic;
wrf_snk_stb_i : in std_logic;
wrf_snk_we_i : in std_logic;
wrf_snk_sel_i : in std_logic_vector(1 downto 0);
wrf_snk_ack_o : out std_logic;
wrf_snk_stall_o : out std_logic;
wrf_snk_err_o : out std_logic;
wrf_snk_rty_o : out std_logic;
---------------------------------------------------------------------------
-- WR streamers (when g_fabric_iface = "streamers")
---------------------------------------------------------------------------
wrs_tx_data_i : in std_logic_vector(g_tx_streamer_params.data_width-1 downto 0) := (others => '0');
wrs_tx_valid_i : in std_logic := '0';
wrs_tx_dreq_o : out std_logic;
wrs_tx_last_i : in std_logic := '1';
wrs_tx_flush_i : in std_logic := '0';
wrs_tx_cfg_mac_l_i : in std_logic_vector(47 downto 0) := x"000000000000";
wrs_tx_cfg_mac_t_i : in std_logic_vector(47 downto 0) := x"ffffffffffff";
wrs_tx_cfg_etype_i : in std_logic_vector(15 downto 0) := x"dbff";
wrs_rx_first_o : out std_logic;
wrs_rx_last_o : out std_logic;
wrs_rx_data_o : out std_logic_vector(g_rx_streamer_params.data_width-1 downto 0);
wrs_rx_valid_o : out std_logic;
wrs_rx_dreq_i : in std_logic := '0';
wrs_rx_cfg_mac_l_i : in std_logic_vector(47 downto 0) := x"000000000000";
wrs_rx_cfg_mac_r_i : in std_logic_vector(47 downto 0) := x"000000000000";
wrs_rx_cfg_etype_i : in std_logic_vector(15 downto 0) := x"dbff";
wrs_rx_cfg_acc_b_i : in std_logic := '1';
wrs_rx_cfg_flt_r_i : in std_logic := '0';
wrs_rx_cfg_fix_l_i : in std_logic_vector(27 downto 0) := x"0000000";
---------------------------------------------------------------------------
-- Etherbone WB master interface (when g_fabric_iface = "etherbone")
---------------------------------------------------------------------------
wb_eth_adr_o : out std_logic_vector(c_wishbone_address_width-1 downto 0);
wb_eth_dat_o : out std_logic_vector(c_wishbone_data_width-1 downto 0);
wb_eth_dat_i : in std_logic_vector(c_wishbone_data_width-1 downto 0) := (others => '0');
wb_eth_sel_o : out std_logic_vector(c_wishbone_address_width/8-1 downto 0);
wb_eth_we_o : out std_logic;
wb_eth_cyc_o : out std_logic;
wb_eth_stb_o : out std_logic;
wb_eth_ack_i : in std_logic := '0';
wb_eth_int_i : in std_logic := '0';
wb_eth_err_i : in std_logic := '0';
wb_eth_rty_i : in std_logic := '0';
wb_eth_stall_i : in std_logic := '0';
---------------------------------------------------------------------------
-- Generic diagnostics interface (access from WRPC via SNMP or uart console
---------------------------------------------------------------------------
aux_diag_i : in std_logic_vector(g_diag_ro_vector_width - 1 downto 0) := (others => '0');
aux_diag_o : out std_logic_vector(g_diag_rw_vector_width - 1 downto 0) := (others => '0');
---------------------------------------------------------------------------
-- Aux clocks control
---------------------------------------------------------------------------
tm_dac_value_o : out std_logic_vector(23 downto 0);
tm_dac_wr_o : out std_logic_vector(g_aux_clks-1 downto 0);
tm_clk_aux_lock_en_i : in std_logic_vector(g_aux_clks-1 downto 0) := (others => '0');
tm_clk_aux_locked_o : out std_logic_vector(g_aux_clks-1 downto 0);
---------------------------------------------------------------------------
-- External Tx Timestamping I/F
---------------------------------------------------------------------------
tstamps_stb_o : out std_logic;
tstamps_tsval_o : out std_logic_vector(31 downto 0);
tstamps_port_id_o : out std_logic_vector(5 downto 0);
tstamps_frame_id_o : out std_logic_vector(15 downto 0);
tstamps_incorrect_o : out std_logic;
tstamps_ack_i : in std_logic := '1';
-----------------------------------------
-- Timestamp helper signals, used for Absolute Calibration
-----------------------------------------
abscal_txts_o : out std_logic;
abscal_rxts_o : out std_logic;
---------------------------------------------------------------------------
-- Pause Frame Control
---------------------------------------------------------------------------
fc_tx_pause_req_i : in std_logic := '0';
fc_tx_pause_delay_i : in std_logic_vector(15 downto 0) := x"0000";
fc_tx_pause_ready_o : out std_logic;
---------------------------------------------------------------------------
-- Timecode I/F
---------------------------------------------------------------------------
tm_link_up_o : out std_logic;
tm_time_valid_o : out std_logic;
tm_tai_o : out std_logic_vector(39 downto 0);
tm_cycles_o : out std_logic_vector(27 downto 0);
---------------------------------------------------------------------------
-- Buttons, LEDs and PPS output
---------------------------------------------------------------------------
led_act_o : out std_logic;
led_link_o : out std_logic;
btn1_i : in std_logic := '1';
btn2_i : in std_logic := '1';
-- 1PPS output
pps_p_o : out std_logic;
pps_led_o : out std_logic;
-- Link ok indication
link_ok_o : out std_logic
);
end entity wrc_board_clbv4;
architecture std_wrapper of wrc_board_clbv4 is
-----------------------------------------------------------------------------
-- Signals
-----------------------------------------------------------------------------
-- WR fabric interface
signal wrf_src_out : t_wrf_source_out;
signal wrf_src_in : t_wrf_source_in;
signal wrf_snk_out : t_wrf_sink_out;
signal wrf_snk_in : t_wrf_sink_in;
-- External WB interface
-- Etherbone interface
-- Aux diagnostics
constant c_diag_ro_size : integer := g_diag_ro_vector_width/32;
constant c_diag_rw_size : integer := g_diag_rw_vector_width/32;
signal aux_diag_in : t_generic_word_array(c_diag_ro_size-1 downto 0);
signal aux_diag_out : t_generic_word_array(c_diag_rw_size-1 downto 0);
-- External Tx Timestamping I/F
signal timestamps_out : t_txtsu_timestamp;
-- streamers config
signal wrs_tx_cfg_in : t_tx_streamer_cfg;
signal wrs_rx_cfg_in : t_rx_streamer_cfg;
begin -- architecture struct
wrf_src_adr_o <= wrf_src_out.adr;
wrf_src_dat_o <= wrf_src_out.dat;
wrf_src_cyc_o <= wrf_src_out.cyc;
wrf_src_stb_o <= wrf_src_out.stb;
wrf_src_we_o <= wrf_src_out.we;
wrf_src_sel_o <= wrf_src_out.sel;
wrf_src_in.ack <= wrf_src_ack_i;
wrf_src_in.stall <= wrf_src_stall_i;
wrf_src_in.err <= wrf_src_err_i;
wrf_src_in.rty <= wrf_src_rty_i;
wrf_snk_in.adr <= wrf_snk_adr_i;
wrf_snk_in.dat <= wrf_snk_dat_i;
wrf_snk_in.cyc <= wrf_snk_cyc_i;
wrf_snk_in.stb <= wrf_snk_stb_i;
wrf_snk_in.we <= wrf_snk_we_i;
wrf_snk_in.sel <= wrf_snk_sel_i;
wrf_snk_ack_o <= wrf_snk_out.ack;
wrf_snk_stall_o <= wrf_snk_out.stall;
wrf_snk_err_o <= wrf_snk_out.err;
wrf_snk_rty_o <= wrf_snk_out.rty;
aux_diag_in <= f_de_vectorize_diag(aux_diag_i, g_diag_ro_vector_width);
aux_diag_o <= f_vectorize_diag(aux_diag_out, g_diag_rw_vector_width);
tstamps_stb_o <= timestamps_out.stb;
tstamps_tsval_o <= timestamps_out.tsval;
tstamps_port_id_o <= timestamps_out.port_id;
tstamps_frame_id_o <= timestamps_out.frame_id;
wrs_tx_cfg_in.mac_local <= wrs_tx_cfg_mac_l_i;
wrs_tx_cfg_in.mac_target <= wrs_tx_cfg_mac_t_i;
wrs_tx_cfg_in.ethertype <= wrs_tx_cfg_etype_i;
wrs_rx_cfg_in.mac_local <= wrs_rx_cfg_mac_l_i;
wrs_rx_cfg_in.mac_remote <= wrs_rx_cfg_mac_r_i;
wrs_rx_cfg_in.ethertype <= wrs_rx_cfg_etype_i;
wrs_rx_cfg_in.accept_broadcasts <= wrs_rx_cfg_acc_b_i;
wrs_rx_cfg_in.filter_remote <= wrs_rx_cfg_flt_r_i;
wrs_rx_cfg_in.fixed_latency <= wrs_rx_cfg_fix_l_i;
-- Instantiate the records-based module
cmp_xwrc_board_clbv4 : xwrc_board_clbv4
generic map (
g_simulation => g_simulation,
g_with_external_clock_input => f_int2bool(g_with_external_clock_input),
g_aux_clks => g_aux_clks,
g_fabric_iface => f_str2iface_type(g_fabric_iface),
g_streamers_op_mode => g_streamers_op_mode,
g_tx_streamer_params => g_tx_streamer_params,
g_rx_streamer_params => g_rx_streamer_params,
g_dpram_initf => g_dpram_initf,
g_diag_id => g_diag_id,
g_diag_ver => g_diag_ver,
g_diag_ro_size => c_diag_ro_size,
g_diag_rw_size => c_diag_rw_size)
port map (
areset_n_i => areset_n_i,
areset_edge_n_i => areset_edge_n_i,
clk_125m_dmtd_p_i => clk_125m_dmtd_p_i,
clk_125m_dmtd_n_i => clk_125m_dmtd_n_i,
clk_125m_gtp_n_i => clk_125m_gtp_n_i,
clk_125m_gtp_p_i => clk_125m_gtp_p_i,
clk_10m_ext_i => clk_10m_ext_i,
pps_ext_i => pps_ext_i,
clk_sys_62m5_o => clk_sys_62m5_o,
clk_ref_62m5_o => clk_ref_62m5_o,
rst_sys_62m5_n_o => rst_sys_62m5_n_o,
rst_ref_62m5_n_o => rst_ref_62m5_n_o,
dac_refclk_cs_n_o => dac_refclk_cs_n_o,
dac_refclk_sclk_o => dac_refclk_sclk_o,
dac_refclk_din_o => dac_refclk_din_o,
dac_dmtd_cs_n_o => dac_dmtd_cs_n_o,
dac_dmtd_sclk_o => dac_dmtd_sclk_o,
dac_dmtd_din_o => dac_dmtd_din_o,
sfp_txp_o => sfp_txp_o,
sfp_txn_o => sfp_txn_o,
sfp_rxp_i => sfp_rxp_i,
sfp_rxn_i => sfp_rxn_i,
sfp_det_i => sfp_det_i,
sfp_sda_i => sfp_sda_i,
sfp_sda_o => sfp_sda_o,
sfp_scl_i => sfp_scl_i,
sfp_scl_o => sfp_scl_o,
sfp_rate_select_o => sfp_rate_select_o,
sfp_tx_fault_i => sfp_tx_fault_i,
sfp_tx_disable_o => sfp_tx_disable_o,
sfp_los_i => sfp_los_i,
eeprom_sda_i => eeprom_sda_i,
eeprom_sda_o => eeprom_sda_o,
eeprom_scl_i => eeprom_scl_i,
eeprom_scl_o => eeprom_scl_o,
onewire_i => onewire_i,
onewire_oen_o => onewire_oen_o,
uart_rxd_i => uart_rxd_i,
uart_txd_o => uart_txd_o,
wrf_src_o => wrf_src_out,
wrf_src_i => wrf_src_in,
wrf_snk_o => wrf_snk_out,
wrf_snk_i => wrf_snk_in,
wrs_tx_data_i => wrs_tx_data_i,
wrs_tx_valid_i => wrs_tx_valid_i,
wrs_tx_dreq_o => wrs_tx_dreq_o,
wrs_tx_last_i => wrs_tx_last_i,
wrs_tx_flush_i => wrs_tx_flush_i,
wrs_tx_cfg_i => wrs_tx_cfg_in,
wrs_rx_first_o => wrs_rx_first_o,
wrs_rx_last_o => wrs_rx_last_o,
wrs_rx_data_o => wrs_rx_data_o,
wrs_rx_valid_o => wrs_rx_valid_o,
wrs_rx_dreq_i => wrs_rx_dreq_i,
wrs_rx_cfg_i => wrs_rx_cfg_in,
aux_diag_i => aux_diag_in,
aux_diag_o => aux_diag_out,
tm_dac_value_o => tm_dac_value_o,
tm_dac_wr_o => tm_dac_wr_o,
tm_clk_aux_lock_en_i => tm_clk_aux_lock_en_i,
tm_clk_aux_locked_o => tm_clk_aux_locked_o,
timestamps_o => timestamps_out,
timestamps_ack_i => tstamps_ack_i,
abscal_txts_o => abscal_txts_o,
abscal_rxts_o => abscal_rxts_o,
fc_tx_pause_req_i => fc_tx_pause_req_i,
fc_tx_pause_delay_i => fc_tx_pause_delay_i,
fc_tx_pause_ready_o => fc_tx_pause_ready_o,
tm_link_up_o => tm_link_up_o,
tm_time_valid_o => tm_time_valid_o,
tm_tai_o => tm_tai_o,
tm_cycles_o => tm_cycles_o,
led_act_o => led_act_o,
led_link_o => led_link_o,
btn1_i => btn1_i,
btn2_i => btn2_i,
pps_p_o => pps_p_o,
pps_led_o => pps_led_o,
link_ok_o => link_ok_o);
end architecture std_wrapper;
board/clbv4/xwrc_board_clbv4.vhd 0 → 100644
View file @ 2b4daa08
-------------------------------------------------------------------------------
-- Title : WRPC Wrapper for clbv4
-- Project : WR PTP Core
-- URL : http://www.ohwr.org/projects/wr-cores/wiki/Wrpc_core
-------------------------------------------------------------------------------
-- File : xwrc_board_clbv4.vhd
-- Author(s) : Pascal Bos <bosp@nikhef.nl>
-- Company : Nikhef
-- Created : 2019-05-06
-- Last update: 2019-05-06
-- Standard : VHDL'93
-------------------------------------------------------------------------------
-- Description: Top-level wrapper for WR PTP core including all the modules
-- needed to operate the core on the clbv3 board.
-------------------------------------------------------------------------------
-- Copyright (c) 2019 Nikhef
-------------------------------------------------------------------------------
-- GNU LESSER GENERAL PUBLIC LICENSE
--
-- This source file is free software; you can redistribute it
-- and/or modify it under the terms of the GNU Lesser General
-- Public License as published by the Free Software Foundation;
-- either version 2.1 of the License, or (at your option) any
-- later version.
--
-- This source is distributed in the hope that it will be
-- useful, but WITHOUT ANY WARRANTY; without even the implied
-- warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR
-- PURPOSE. See the GNU Lesser General Public License for more
-- details.
--
-- You should have received a copy of the GNU Lesser General
-- Public License along with this source; if not, download it
-- from http://www.gnu.org/licenses/lgpl-2.1.html
--
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
library work;
use work.gencores_pkg.all;
use work.wrcore_pkg.all;
use work.wishbone_pkg.all;
--use work.etherbone_pkg.all;
use work.wr_fabric_pkg.all;
use work.endpoint_pkg.all;
use work.streamers_pkg.all;
use work.wr_xilinx_pkg.all;
use work.wr_board_pkg.all;
use work.wr_clbv4_pkg.all;
library unisim;
use unisim.vcomponents.all;
entity xwrc_board_clbv4 is
generic(
-- set to 1 to speed up some initialization processes during simulation
g_simulation : integer := 0;
-- Select whether to include external ref clock input
g_with_external_clock_input : boolean := TRUE;
-- Number of aux clocks syntonized by WRPC to WR timebase
g_aux_clks : integer := 1;
-- plain = expose WRC fabric interface
-- streamers = attach WRC streamers to fabric interface
-- etherbone = attach Etherbone slave to fabric interface
g_fabric_iface : t_board_fabric_iface := plain;
-- parameters configuration when g_fabric_iface = "streamers" (otherwise ignored)
g_streamers_op_mode : t_streamers_op_mode := TX_AND_RX;
g_tx_streamer_params : t_tx_streamer_params := c_tx_streamer_params_defaut;
g_rx_streamer_params : t_rx_streamer_params := c_rx_streamer_params_defaut;
-- memory initialisation file for embedded CPU
g_dpram_initf : string := "default_xilinx";
-- identification (id and ver) of the layout of words in the generic diag interface
g_diag_id : integer := 0;
g_diag_ver : integer := 0;
-- size the generic diag interface
g_diag_ro_size : integer := 0;
g_diag_rw_size : integer := 0
);
port (
---------------------------------------------------------------------------
-- Clocks/resets
---------------------------------------------------------------------------
-- Reset input (active low, can be async)
areset_n_i : in std_logic;
-- Optional reset input active low with rising edge detection. Does not
-- reset PLLs.
areset_edge_n_i : in std_logic := '1';
-- Clock inputs from the board
clk_125m_dmtd_n_i : in std_logic; -- 124.992 MHz
clk_125m_dmtd_p_i : in std_logic;
clk_125m_gtx_n_i : in std_logic;
clk_125m_gtx_p_i : in std_logic;
-- Aux clocks, which can be disciplined by the WR Core
clk_aux_i : in std_logic_vector(g_aux_clks-1 downto 0) := (others => '0');
-- 10MHz ext ref clock input (g_with_external_clock_input = TRUE)
clk_10m_ext_i : in std_logic := '0';
-- External PPS input (g_with_external_clock_input = TRUE)
pps_ext_i : in std_logic := '0';
-- 62.5MHz sys clock output
clk_sys_62m5_o : out std_logic;
-- 62.5MHz ref clock output
clk_ref_62m5_o : out std_logic;
-- 124.992 / 2 = 62.496 MHz dmtd clock output
clk_dmtd_62m5_o : out std_logic;
-- active low reset outputs, synchronous to 62m5 and 125m clocks
rst_sys_62m5_n_o : out std_logic;
rst_ref_62m5_n_o : out std_logic;
---------------------------------------------------------------------------
-- Shared SPI interface to DACs
---------------------------------------------------------------------------
dac_refclk_cs_n_o : out std_logic;
dac_refclk_sclk_o : out std_logic;
dac_refclk_din_o : out std_logic;
dac_dmtd_cs_n_o : out std_logic;
dac_dmtd_sclk_o : out std_logic;
dac_dmtd_din_o : out std_logic;
---------------------------------------------------------------------------
-- SFP I/O for transceiver and SFP management info
---------------------------------------------------------------------------
sfp_txp_o : out std_logic;
sfp_txn_o : out std_logic;
sfp_rxp_i : in std_logic;
sfp_rxn_i : in std_logic;
sfp_det_i : in std_logic := '1';
sfp_sda_i : in std_logic;
sfp_sda_o : out std_logic;
sfp_scl_i : in std_logic;
sfp_scl_o : out std_logic;
sfp_rate_select_o : out std_logic;
sfp_tx_fault_i : in std_logic := '0';
sfp_tx_disable_o : out std_logic;
sfp_los_i : in std_logic := '0';
---------------------------------------------------------------------------
-- I2C EEPROM
---------------------------------------------------------------------------
eeprom_sda_i : in std_logic;
eeprom_sda_o : out std_logic;
eeprom_scl_i : in std_logic;
eeprom_scl_o : out std_logic;
---------------------------------------------------------------------------
-- Onewire interface
---------------------------------------------------------------------------
onewire_i : in std_logic;
onewire_oen_o : out std_logic;
---------------------------------------------------------------------------
-- UART
---------------------------------------------------------------------------
uart_rxd_i : in std_logic;
uart_txd_o : out std_logic;
---------------------------------------------------------------------------
-- No Flash memory SPI interface
---------------------------------------------------------------------------
---------------------------------------------------------------------------
-- No External WB interface
---------------------------------------------------------------------------
---------------------------------------------------------------------------
-- WR fabric interface (when g_fabric_iface = "plainfbrc")
---------------------------------------------------------------------------
wrf_src_o : out t_wrf_source_out;
wrf_src_i : in t_wrf_source_in := c_dummy_src_in;
wrf_snk_o : out t_wrf_sink_out;
wrf_snk_i : in t_wrf_sink_in := c_dummy_snk_in;
---------------------------------------------------------------------------
-- WR streamers (when g_fabric_iface = "streamers")
---------------------------------------------------------------------------
wrs_tx_data_i : in std_logic_vector(g_tx_streamer_params.data_width-1 downto 0) := (others => '0');
wrs_tx_valid_i : in std_logic := '0';
wrs_tx_dreq_o : out std_logic;
wrs_tx_last_i : in std_logic := '1';
wrs_tx_flush_i : in std_logic := '0';
wrs_tx_cfg_i : in t_tx_streamer_cfg := c_tx_streamer_cfg_default;
wrs_rx_first_o : out std_logic;
wrs_rx_last_o : out std_logic;
wrs_rx_data_o : out std_logic_vector(g_rx_streamer_params.data_width-1 downto 0);
wrs_rx_valid_o : out std_logic;
wrs_rx_dreq_i : in std_logic := '0';
wrs_rx_cfg_i : in t_rx_streamer_cfg := c_rx_streamer_cfg_default;
---------------------------------------------------------------------------
-- No Etherbone WB master interface (when g_fabric_iface = "etherbone")
---------------------------------------------------------------------------
---------------------------------------------------------------------------
-- Generic diagnostics interface (access from WRPC via SNMP or uart console
---------------------------------------------------------------------------
aux_diag_i : in t_generic_word_array(g_diag_ro_size-1 downto 0) := (others => (others => '0'));
aux_diag_o : out t_generic_word_array(g_diag_rw_size-1 downto 0);
---------------------------------------------------------------------------
-- Aux clocks control
---------------------------------------------------------------------------
tm_dac_value_o : out std_logic_vector(23 downto 0);
tm_dac_wr_o : out std_logic_vector(g_aux_clks-1 downto 0);
tm_clk_aux_lock_en_i : in std_logic_vector(g_aux_clks-1 downto 0) := (others => '0');
tm_clk_aux_locked_o : out std_logic_vector(g_aux_clks-1 downto 0);
---------------------------------------------------------------------------
-- External Tx Timestamping I/F
---------------------------------------------------------------------------
timestamps_o : out t_txtsu_timestamp;
timestamps_ack_i : in std_logic := '1';
-----------------------------------------
-- Timestamp helper signals, used for Absolute Calibration
-----------------------------------------
abscal_txts_o : out std_logic;
abscal_rxts_o : out std_logic;
---------------------------------------------------------------------------
-- Pause Frame Control
---------------------------------------------------------------------------
fc_tx_pause_req_i : in std_logic := '0';
fc_tx_pause_delay_i : in std_logic_vector(15 downto 0) := x"0000";
fc_tx_pause_ready_o : out std_logic;
---------------------------------------------------------------------------
-- Timecode I/F
---------------------------------------------------------------------------
tm_link_up_o : out std_logic;
tm_time_valid_o : out std_logic;
tm_tai_o : out std_logic_vector(39 downto 0);
tm_cycles_o : out std_logic_vector(27 downto 0);
---------------------------------------------------------------------------
-- Buttons, LEDs and PPS output
---------------------------------------------------------------------------
led_act_o : out std_logic;
led_link_o : out std_logic;
btn1_i : in std_logic := '1';
btn2_i : in std_logic := '1';
-- 1PPS output
pps_p_o : out std_logic;
pps_led_o : out std_logic;
-- Link ok indication
link_ok_o : out std_logic
);
end entity xwrc_board_clbv4;
architecture struct of xwrc_board_clbv4 is
-----------------------------------------------------------------------------
-- Signals
-----------------------------------------------------------------------------
-- IBUFDS
signal clk_125m_dmtd_buf : std_logic;
signal clk_dmtd : std_logic;
-- PLLs, clocks
signal clk_pll_62m5 : std_logic;
signal clk_ref_62m5 : std_logic;
signal pll_locked : std_logic;
signal clk_10m_ext : std_logic;
-- Reset logic
signal areset_edge_ppulse : std_logic;
signal rst_62m5_n : std_logic;
signal rstlogic_arst_n : std_logic;
signal rstlogic_clk_in : std_logic_vector(1 downto 0);
signal rstlogic_rst_out : std_logic_vector(1 downto 0);
-- PLL DACs
signal dac_dmtd_load : std_logic;
signal dac_dmtd_data : std_logic_vector(15 downto 0);
signal dac_refclk_load : std_logic;
signal dac_refclk_data : std_logic_vector(15 downto 0);
-- OneWire
signal onewire_in : std_logic_vector(1 downto 0);
signal onewire_en : std_logic_vector(1 downto 0);
-- PHY
signal phy16_to_wrc : t_phy_16bits_to_wrc;
signal phy16_from_wrc : t_phy_16bits_from_wrc;
-- External reference
signal ext_ref_mul : std_logic;
signal ext_ref_mul_locked : std_logic;
signal ext_ref_mul_stopped : std_logic;
signal ext_ref_rst : std_logic;
begin -- architecture struct
-----------------------------------------------------------------------------
-- Platform-dependent part (PHY, PLLs, buffers, etc)
-----------------------------------------------------------------------------
cmp_ibufgds_dmtd : IBUFGDS
generic map (
DIFF_TERM => TRUE)
port map (
O => clk_125m_dmtd_buf,
I => clk_125m_dmtd_p_i,
IB => clk_125m_dmtd_n_i);
clk_dmtd_62m5_o <= clk_dmtd;
cmp_xwrc_platform : xwrc_platform_xilinx
generic map (
g_fpga_family => "kintex7",
g_direct_dmtd => TRUE,
g_with_external_clock_input => g_with_external_clock_input,
g_use_default_plls => TRUE,
g_simulation => g_simulation)
port map (
areset_n_i => areset_n_i,
clk_10m_ext_i => clk_10m_ext_i,
clk_125m_dmtd_i => clk_125m_dmtd_buf,
clk_125m_gtp_p_i => clk_125m_gtx_p_i, --Note clbv4 used GTX instead of GTPs
clk_125m_gtp_n_i => clk_125m_gtx_n_i,
sfp_txn_o => sfp_txn_o,
sfp_txp_o => sfp_txp_o,
sfp_rxn_i => sfp_rxn_i,
sfp_rxp_i => sfp_rxp_i,
sfp_tx_fault_i => sfp_tx_fault_i,
sfp_los_i => sfp_los_i,
sfp_tx_disable_o => sfp_tx_disable_o,
clk_62m5_sys_o => clk_pll_62m5,
clk_125m_ref_o => clk_ref_62m5, -- Note: This is a 62m5 Clock for 16 bit PHYs!
clk_62m5_dmtd_o => clk_dmtd,
pll_locked_o => pll_locked,
clk_10m_ext_o => clk_10m_ext,
phy16_o => phy16_to_wrc,
phy16_i => phy16_from_wrc,
ext_ref_mul_o => ext_ref_mul,
ext_ref_mul_locked_o => ext_ref_mul_locked,
ext_ref_mul_stopped_o => ext_ref_mul_stopped,
ext_ref_rst_i => ext_ref_rst);
clk_sys_62m5_o <= clk_pll_62m5;
clk_ref_62m5_o <= clk_ref_62m5;
-----------------------------------------------------------------------------
-- Reset logic
-----------------------------------------------------------------------------
-- Detect when areset_edge_n_i goes high (end of reset) and use this edge to
-- generate rstlogic_arst_n. This is needed to connect optional reset like PCIe
-- reset. When baord runs standalone, we need to ignore PCIe reset being
-- constantly low.
cmp_arst_edge: gc_sync_ffs
generic map (
g_sync_edge => "positive")
port map (
clk_i => clk_pll_62m5,
rst_n_i => '1',
data_i => areset_edge_n_i,
ppulse_o => areset_edge_ppulse);
-- logic AND of all async reset sources (active low)
rstlogic_arst_n <= pll_locked and areset_n_i and (not areset_edge_ppulse);
-- concatenation of all clocks required to have synced resets
rstlogic_clk_in(0) <= clk_pll_62m5;
rstlogic_clk_in(1) <= clk_ref_62m5;
cmp_rstlogic_reset : gc_reset
generic map (
g_clocks => 2, -- 62.5MHz, 125MHz
g_logdelay => 4, -- 16 clock cycles
g_syncdepth => 3) -- length of sync chains
port map (
free_clk_i => clk_125m_dmtd_buf,
locked_i => rstlogic_arst_n,
clks_i => rstlogic_clk_in,
rstn_o => rstlogic_rst_out);
-- distribution of resets (already synchronized to their clock domains)
rst_62m5_n <= rstlogic_rst_out(0);
rst_sys_62m5_n_o <= rst_62m5_n;
rst_ref_62m5_n_o <= rstlogic_rst_out(1);
-----------------------------------------------------------------------------
-- 2x SPI DAC
-----------------------------------------------------------------------------
cmp_dmtd_dac : gc_serial_dac
generic map (
g_num_data_bits => 16,
g_num_extra_bits => 8,
g_num_cs_select => 1,
g_sclk_polarity => 0)
port map (
clk_i => clk_pll_62m5,
rst_n_i => rst_62m5_n,
value_i => dac_dmtd_data,
cs_sel_i => "1",
load_i => dac_dmtd_load,
sclk_divsel_i => "001",
dac_cs_n_o(0) => dac_dmtd_cs_n_o,
dac_sclk_o => dac_dmtd_sclk_o,
dac_sdata_o => dac_dmtd_din_o);
cmp_refclk_dac : gc_serial_dac
generic map (
g_num_data_bits => 16,
g_num_extra_bits => 8,
g_num_cs_select => 1,
g_sclk_polarity => 0)
port map (
clk_i => clk_pll_62m5,
rst_n_i => rst_62m5_n,
value_i => dac_refclk_data,
cs_sel_i => "1",
load_i => dac_refclk_load,
sclk_divsel_i => "001",
dac_cs_n_o(0) => dac_refclk_cs_n_o,
dac_sclk_o => dac_refclk_sclk_o,
dac_sdata_o => dac_refclk_din_o);
-----------------------------------------------------------------------------
-- The WR PTP core with optional fabric interface attached
-----------------------------------------------------------------------------
cmp_board_common : xwrc_board_common
generic map (
g_simulation => g_simulation,
g_with_external_clock_input => g_with_external_clock_input,
g_board_name => "CLB4",
g_phys_uart => TRUE,
g_virtual_uart => TRUE,
g_aux_clks => g_aux_clks,
g_ep_rxbuf_size => 1024,
g_tx_runt_padding => TRUE,
g_dpram_initf => g_dpram_initf,
g_dpram_size => 131072/4,
g_interface_mode => PIPELINED,
g_address_granularity => BYTE,
g_aux_sdb => c_wrc_periph3_sdb,
g_softpll_enable_debugger => FALSE,
g_vuart_fifo_size => 1024,
g_pcs_16bit => TRUE,
g_diag_id => g_diag_id,
g_diag_ver => g_diag_ver,
g_diag_ro_size => g_diag_ro_size,
g_diag_rw_size => g_diag_rw_size,
g_streamers_op_mode => g_streamers_op_mode,
g_tx_streamer_params => g_tx_streamer_params,
g_rx_streamer_params => g_rx_streamer_params,
g_fabric_iface => g_fabric_iface
)
port map (
clk_sys_i => clk_pll_62m5,
clk_dmtd_i => clk_dmtd,
clk_ref_i => clk_ref_62m5,
clk_aux_i => clk_aux_i,
clk_10m_ext_i => clk_10m_ext,
clk_ext_mul_i => ext_ref_mul,
clk_ext_mul_locked_i => ext_ref_mul_locked,
clk_ext_stopped_i => ext_ref_mul_stopped,
clk_ext_rst_o => ext_ref_rst,
pps_ext_i => pps_ext_i,
rst_n_i => rst_62m5_n,
dac_hpll_load_p1_o => dac_dmtd_load,
dac_hpll_data_o => dac_dmtd_data,
dac_dpll_load_p1_o => dac_refclk_load,
dac_dpll_data_o => dac_refclk_data,
phy16_o => phy16_from_wrc,
phy16_i => phy16_to_wrc,
scl_o => eeprom_scl_o,
scl_i => eeprom_scl_i,
sda_o => eeprom_sda_o,
sda_i => eeprom_sda_i,
sfp_scl_o => sfp_scl_o,
sfp_scl_i => sfp_scl_i,
sfp_sda_o => sfp_sda_o,
sfp_sda_i => sfp_sda_i,
sfp_det_i => sfp_det_i,
spi_sclk_o => open,
spi_ncs_o => open,
spi_mosi_o => open,
spi_miso_i => '0',
uart_rxd_i => uart_rxd_i,
uart_txd_o => uart_txd_o,
owr_pwren_o => open,
owr_en_o => onewire_en,
owr_i => onewire_in,
wrf_src_o => wrf_src_o,
wrf_src_i => wrf_src_i,
wrf_snk_o => wrf_snk_o,
wrf_snk_i => wrf_snk_i,
wrs_tx_data_i => wrs_tx_data_i,
wrs_tx_valid_i => wrs_tx_valid_i,
wrs_tx_dreq_o => wrs_tx_dreq_o,
wrs_tx_last_i => wrs_tx_last_i,
wrs_tx_flush_i => wrs_tx_flush_i,
wrs_tx_cfg_i => wrs_tx_cfg_i,
wrs_rx_first_o => wrs_rx_first_o,
wrs_rx_last_o => wrs_rx_last_o,
wrs_rx_data_o => wrs_rx_data_o,
wrs_rx_valid_o => wrs_rx_valid_o,
wrs_rx_dreq_i => wrs_rx_dreq_i,
wrs_rx_cfg_i => wrs_rx_cfg_i,
aux_diag_i => aux_diag_i,
aux_diag_o => aux_diag_o,
tm_dac_value_o => tm_dac_value_o,
tm_dac_wr_o => tm_dac_wr_o,
tm_clk_aux_lock_en_i => tm_clk_aux_lock_en_i,
tm_clk_aux_locked_o => tm_clk_aux_locked_o,
timestamps_o => timestamps_o,
timestamps_ack_i => timestamps_ack_i,
abscal_txts_o => abscal_txts_o,
abscal_rxts_o => abscal_rxts_o,
fc_tx_pause_req_i => fc_tx_pause_req_i,
fc_tx_pause_delay_i => fc_tx_pause_delay_i,
fc_tx_pause_ready_o => fc_tx_pause_ready_o,
tm_link_up_o => tm_link_up_o,
tm_time_valid_o => tm_time_valid_o,
tm_tai_o => tm_tai_o,
tm_cycles_o => tm_cycles_o,
led_act_o => led_act_o,
led_link_o => led_link_o,
btn1_i => btn1_i,
btn2_i => btn2_i,
pps_p_o => pps_p_o,
pps_led_o => pps_led_o,
link_ok_o => link_ok_o);
sfp_rate_select_o <= '1';
onewire_oen_o <= onewire_en(0);
onewire_in(0) <= onewire_i;
onewire_in(1) <= '1';
end architecture struct;
syn/clbv4_ref_design/Manifest.py 0 → 100644
View file @ 2b4daa08
board = "clbv4"
target = "xilinx"
action = "synthesis"
syn_device = "xc7k160t"
syn_grade = "-2"
syn_package = "fbg676"
syn_top = "clbv4_wr_ref_top"
syn_project = "clbv4_wr_ref.xpr"
syn_tool = "vivado"
modules = { "local" : "../../top/clbv4_ref_design/"}
top/clbv4_ref_design/Manifest.py 0 → 100644
View file @ 2b4daa08
fetchto = "../../ip_cores"
files = [
"clbv4_wr_ref_top.vhd",
"clbv4_wr_ref_top.xdc",
"clbv4_wr_ref_top.bmm",
]
modules = {
"local" : [
"../../",
],
"git" : [
"git://ohwr.org/hdl-core-lib/general-cores.git",
"git://ohwr.org/hdl-core-lib/etherbone-core.git",
],
}
top/clbv4_ref_design/clbv4_wr_ref_top.bmm 0 → 100644
View file @ 2b4daa08
/* FILE : clbv4_wr_ref_top.bmm
* Define a BRAM map for the LM32 memory.
* Run ISE Translate -> "Floorplan Area/IO/Logic (PlanAhead)" once (without this BMM file
* attached to the ISE Project) to find out that there are 16 ramloops and each RAMB36E1
* Note: *THE RAMLOOP ORDER WITHIN A BUS_BLOCK IS VERY IMPORTANT!!!*
* Define ramloop 15 downto 0 and databits 31 downto 0 !!! Otherwise the memory
* content will be swapped and the program fails to execute. Aperently the ramloop
* number and bit definitions are not read by data2mem.
*
*
* Address space LM32 memory
* g_dpram_size = 90112/4 = 22528
* This size is in 32 bit words => byte size = 4 * 22528 = 90112 bytes
*
* ATTENTION PARITY!
* Although the memory is implemented in RAMB36E1 the address same MUST be defined as
* RAMB32 (insetad of RAMB36) since we are NOT using parity! If the address space is
* defined as RAMB36 then data2mem is expecting an extra nibble for each 32 bit instruction
* in the ".elf" file and since this nibble is not provided, the ramblocks will be filled
* such that a nibble shift is accumulating in the data.
* Note that this can be examined using the command
* "data2mem -bm clbv4_wr_ref_top_bd.bmm -bt clbv4_wr_ref_top_elf.bit -d > dump.txt"
*
* ATTENTION Xilinx Synthesis
* XST implements the 22K * 32 bit as:
* 22 blocks of 1K * 32 bits
*
****************************************************************************************/
ADDRESS_SPACE lm32_wrpc_memory COMBINED [0x00000000:0x0001FFFF]
ADDRESS_RANGE RAMB32
BUS_BLOCK
cmp_xwrc_board_clbv4/cmp_board_common/cmp_xwr_core/WRPC/DPRAM/U_DPRAM/gen_splitram.U_RAM_SPLIT/ram3_reg_0_7 [31];
cmp_xwrc_board_clbv4/cmp_board_common/cmp_xwr_core/WRPC/DPRAM/U_DPRAM/gen_splitram.U_RAM_SPLIT/ram3_reg_0_6 [30];
cmp_xwrc_board_clbv4/cmp_board_common/cmp_xwr_core/WRPC/DPRAM/U_DPRAM/gen_splitram.U_RAM_SPLIT/ram3_reg_0_5 [29];
cmp_xwrc_board_clbv4/cmp_board_common/cmp_xwr_core/WRPC/DPRAM/U_DPRAM/gen_splitram.U_RAM_SPLIT/ram3_reg_0_4 [28];
cmp_xwrc_board_clbv4/cmp_board_common/cmp_xwr_core/WRPC/DPRAM/U_DPRAM/gen_splitram.U_RAM_SPLIT/ram3_reg_0_3 [27];
cmp_xwrc_board_clbv4/cmp_board_common/cmp_xwr_core/WRPC/DPRAM/U_DPRAM/gen_splitram.U_RAM_SPLIT/ram3_reg_0_2 [26];
cmp_xwrc_board_clbv4/cmp_board_common/cmp_xwr_core/WRPC/DPRAM/U_DPRAM/gen_splitram.U_RAM_SPLIT/ram3_reg_0_1 [25];
cmp_xwrc_board_clbv4/cmp_board_common/cmp_xwr_core/WRPC/DPRAM/U_DPRAM/gen_splitram.U_RAM_SPLIT/ram3_reg_0_0 [24];
cmp_xwrc_board_clbv4/cmp_board_common/cmp_xwr_core/WRPC/DPRAM/U_DPRAM/gen_splitram.U_RAM_SPLIT/ram2_reg_0_7 [23];
cmp_xwrc_board_clbv4/cmp_board_common/cmp_xwr_core/WRPC/DPRAM/U_DPRAM/gen_splitram.U_RAM_SPLIT/ram2_reg_0_6 [22];
cmp_xwrc_board_clbv4/cmp_board_common/cmp_xwr_core/WRPC/DPRAM/U_DPRAM/gen_splitram.U_RAM_SPLIT/ram2_reg_0_5 [21];
cmp_xwrc_board_clbv4/cmp_board_common/cmp_xwr_core/WRPC/DPRAM/U_DPRAM/gen_splitram.U_RAM_SPLIT/ram2_reg_0_4 [20];
cmp_xwrc_board_clbv4/cmp_board_common/cmp_xwr_core/WRPC/DPRAM/U_DPRAM/gen_splitram.U_RAM_SPLIT/ram2_reg_0_3 [19];
cmp_xwrc_board_clbv4/cmp_board_common/cmp_xwr_core/WRPC/DPRAM/U_DPRAM/gen_splitram.U_RAM_SPLIT/ram2_reg_0_2 [18];
cmp_xwrc_board_clbv4/cmp_board_common/cmp_xwr_core/WRPC/DPRAM/U_DPRAM/gen_splitram.U_RAM_SPLIT/ram2_reg_0_1 [17];
cmp_xwrc_board_clbv4/cmp_board_common/cmp_xwr_core/WRPC/DPRAM/U_DPRAM/gen_splitram.U_RAM_SPLIT/ram2_reg_0_0 [16];
cmp_xwrc_board_clbv4/cmp_board_common/cmp_xwr_core/WRPC/DPRAM/U_DPRAM/gen_splitram.U_RAM_SPLIT/ram1_reg_0_7 [15];
cmp_xwrc_board_clbv4/cmp_board_common/cmp_xwr_core/WRPC/DPRAM/U_DPRAM/gen_splitram.U_RAM_SPLIT/ram1_reg_0_6 [14];
cmp_xwrc_board_clbv4/cmp_board_common/cmp_xwr_core/WRPC/DPRAM/U_DPRAM/gen_splitram.U_RAM_SPLIT/ram1_reg_0_5 [13];
cmp_xwrc_board_clbv4/cmp_board_common/cmp_xwr_core/WRPC/DPRAM/U_DPRAM/gen_splitram.U_RAM_SPLIT/ram1_reg_0_4 [12];
cmp_xwrc_board_clbv4/cmp_board_common/cmp_xwr_core/WRPC/DPRAM/U_DPRAM/gen_splitram.U_RAM_SPLIT/ram1_reg_0_3 [11];
cmp_xwrc_board_clbv4/cmp_board_common/cmp_xwr_core/WRPC/DPRAM/U_DPRAM/gen_splitram.U_RAM_SPLIT/ram1_reg_0_2 [10];
cmp_xwrc_board_clbv4/cmp_board_common/cmp_xwr_core/WRPC/DPRAM/U_DPRAM/gen_splitram.U_RAM_SPLIT/ram1_reg_0_1 [9];
cmp_xwrc_board_clbv4/cmp_board_common/cmp_xwr_core/WRPC/DPRAM/U_DPRAM/gen_splitram.U_RAM_SPLIT/ram1_reg_0_0 [8];
cmp_xwrc_board_clbv4/cmp_board_common/cmp_xwr_core/WRPC/DPRAM/U_DPRAM/gen_splitram.U_RAM_SPLIT/ram0_reg_0_7 [7];
cmp_xwrc_board_clbv4/cmp_board_common/cmp_xwr_core/WRPC/DPRAM/U_DPRAM/gen_splitram.U_RAM_SPLIT/ram0_reg_0_6 [6];
cmp_xwrc_board_clbv4/cmp_board_common/cmp_xwr_core/WRPC/DPRAM/U_DPRAM/gen_splitram.U_RAM_SPLIT/ram0_reg_0_5 [5];
cmp_xwrc_board_clbv4/cmp_board_common/cmp_xwr_core/WRPC/DPRAM/U_DPRAM/gen_splitram.U_RAM_SPLIT/ram0_reg_0_4 [4];
cmp_xwrc_board_clbv4/cmp_board_common/cmp_xwr_core/WRPC/DPRAM/U_DPRAM/gen_splitram.U_RAM_SPLIT/ram0_reg_0_3 [3];
cmp_xwrc_board_clbv4/cmp_board_common/cmp_xwr_core/WRPC/DPRAM/U_DPRAM/gen_splitram.U_RAM_SPLIT/ram0_reg_0_2 [2];
cmp_xwrc_board_clbv4/cmp_board_common/cmp_xwr_core/WRPC/DPRAM/U_DPRAM/gen_splitram.U_RAM_SPLIT/ram0_reg_0_1 [1];
cmp_xwrc_board_clbv4/cmp_board_common/cmp_xwr_core/WRPC/DPRAM/U_DPRAM/gen_splitram.U_RAM_SPLIT/ram0_reg_0_0 [0];
END_BUS_BLOCK;
END_ADDRESS_RANGE;
END_ADDRESS_SPACE;
top/clbv4_ref_design/clbv4_wr_ref_top.vhd 0 → 100644
View file @ 2b4daa08
-------------------------------------------------------------------------------
-- Title : WRPC reference design for KM3NeT Central Logic Board (CLBv4)
-- : based on kintex-7
-- Project : WR PTP Core
-- URL : http://www.ohwr.org/projects/wr-cores/wiki/Wrpc_core
-------------------------------------------------------------------------------
-- File : clbv4_wr_ref_top.vhd
-- Author(s) : Pascal Bos <bosp@nikhef.nl>
-- Company : Nikhef
-- Created : 2019-05-06
-- Last update: 2019-05-06
-- Standard : VHDL'93
-------------------------------------------------------------------------------
-- Description: Top-level file for the WRPC reference design on the clbv4.
--
-- This is a reference top HDL that instanciates the WR PTP Core together with
-- its peripherals to be run on a CLB card.
--
-- There are two main usecases for this HDL file:
-- * let new users easily synthesize a WR PTP Core bitstream that can be run on
-- reference hardware
-- * provide a reference top HDL file showing how the WRPC can be instantiated
-- in HDL projects.
--
-------------------------------------------------------------------------------
-- Copyright (c) 2019 Nikhef
-------------------------------------------------------------------------------
-- GNU LESSER GENERAL PUBLIC LICENSE
--
-- This source file is free software; you can redistribute it
-- and/or modify it under the terms of the GNU Lesser General
-- Public License as published by the Free Software Foundation;
-- either version 2.1 of the License, or (at your option) any
-- later version.
--
-- This source is distributed in the hope that it will be
-- useful, but WITHOUT ANY WARRANTY; without even the implied
-- warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR
-- PURPOSE. See the GNU Lesser General Public License for more
-- details.
--
-- You should have received a copy of the GNU Lesser General
-- Public License along with this source; if not, download it
-- from http://www.gnu.org/licenses/lgpl-2.1.html
--
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library work;
use work.gencores_pkg.all;
use work.wishbone_pkg.all;
use work.wr_board_pkg.all;
use work.wr_clbv4_pkg.all;
library unisim;
use unisim.vcomponents.all;
entity clbv4_wr_ref_top is
generic (
g_dpram_initf : string := "../../../../bin/wrpc/wrc_phy16_direct_dmtd.bram";
-- In Vivado Project-Mode, during a Synthesis run or an Implementation run, the Vivado working
-- directory temporarily changes to the "project_name/project_name.runs/run_name" directory.
-- Simulation-mode enable parameter. Set by default (synthesis) to 0, and
-- changed to non-zero in the instantiation of the top level DUT in the testbench.
-- Its purpose is to reduce some internal counters/timeouts to speed up simulations.
g_simulation : integer := 0
);
port (
---------------------------------------------------------------------------`
-- Clocks/resets
---------------------------------------------------------------------------
-- Local oscillators
clk_125m_dmtd_p_i : in std_logic; -- 124.992 MHz PLL reference
clk_125m_dmtd_n_i : in std_logic;
clk_125m_gtx_n_i : in std_logic; -- 125.000 MHz GTX reference
clk_125m_gtx_p_i : in std_logic;
---------------------------------------------------------------------------
-- SPI interface to DACs
---------------------------------------------------------------------------
dac_refclk_cs_n_o : out std_logic;
dac_refclk_sclk_o : out std_logic;
dac_refclk_din_o : out std_logic;
dac_dmtd_cs_n_o : out std_logic;
dac_dmtd_sclk_o : out std_logic;
dac_dmtd_din_o : out std_logic;
---------------------------------------------------------------------------
-- SFP I/O for transceiver
---------------------------------------------------------------------------
sfp_txp_o : out std_logic;
sfp_txn_o : out std_logic;
sfp_rxp_i : in std_logic;
sfp_rxn_i : in std_logic;
--sfp_mod_def0_i : in std_logic; -- sfp detect not present on GlenAir module
sfp_mod_def1_b : inout std_logic; -- scl
sfp_mod_def2_b : inout std_logic; -- sda
sfp_rate_select_o : out std_logic;
sfp_tx_fault_i : in std_logic;
sfp_tx_disable_o : out std_logic;
sfp_los_i : in std_logic;
---------------------------------------------------------------------------
-- Onewire interface
---------------------------------------------------------------------------
onewire_b : inout std_logic;
---------------------------------------------------------------------------
-- UART
---------------------------------------------------------------------------
uart_rxd_i : in std_logic;
uart_txd_o : out std_logic;
---------------------------------------------------------------------------
-- No Flash memory SPI interface
---------------------------------------------------------------------------
---------------------------------------------------------------------------
-- Miscellanous clbv3 pins
---------------------------------------------------------------------------
-- Red LED next to the SFP: blinking indicates that packets are being
-- transferred.
led_act_o : out std_logic;
-- Green LED next to the SFP: indicates if the link is up.
led_link_o : out std_logic;
-- Reset control
reset_i : in std_logic;
suicide : out std_logic;
WDI : out std_logic;
WD_SET : out std_logic_vector(2 downto 0);
-- test_lemo outputs PPS
test_lemo : out std_logic;
-- Monitoring signals output on External Debug Connector J35
pps_mon : out std_logic;
ref_clk_mon : out std_logic;
---------------------------------------------------------------------------
-- Digital I/O FMC Pins
-- used in this design to output WR-aligned 1-PPS (in Slave mode) and input
-- 10MHz & 1-PPS from external reference (in GrandMaster mode).
---------------------------------------------------------------------------
-- Clock input from LEMO 5 on the mezzanine front panel. Used as 10MHz
-- external reference input.
dio_clk_p_i : in std_logic;
dio_clk_n_i : in std_logic;
-- Differential inputs, dio_p_i(N) inputs the current state of I/O (N+1) on
-- the mezzanine front panel.
dio_n_i : in std_logic_vector(4 downto 0);
dio_p_i : in std_logic_vector(4 downto 0);
-- Differential outputs. When the I/O (N+1) is configured as output (i.e. when
-- dio_oe_n_o(N) = 0), the value of dio_p_o(N) determines the logic state
-- of I/O (N+1) on the front panel of the mezzanine
dio_n_o : out std_logic_vector(4 downto 0);
dio_p_o : out std_logic_vector(4 downto 0);
-- Output enable. When dio_oe_n_o(N) is 0, connector (N+1) on the front
-- panel is configured as an output.
dio_oe_n_o : out std_logic_vector(4 downto 0);
-- Termination enable. When dio_term_en_o(N) is 1, connector (N+1) on the front
-- panel is 50-ohm terminated
dio_term_en_o : out std_logic_vector(4 downto 0);
-- Two LEDs on the mezzanine panel. Only Top one is currently used - to
-- blink 1-PPS.
dio_led_top_o : out std_logic;
dio_led_bot_o : out std_logic;
-- I2C interface for accessing FMC EEPROM. Deprecated, was used in
-- pre-v3.0 releases to store WRPC configuration. Now we use Flash for this.
dio_scl_b : inout std_logic;
dio_sda_b : inout std_logic;
-- Bulls-eye connector outputs
txts_p_o : out std_logic;
txts_n_o : out std_logic;
rxts_p_o : out std_logic;
rxts_n_o : out std_logic;
pps_p_o : out std_logic;
pps_n_o : out std_logic;
clk_ref_62m5_p_o : out std_logic;
clk_ref_62m5_n_o : out std_logic;
clk_dmtd_62m5_p_o : out std_logic;
clk_dmtd_62m5_n_o : out std_logic
);
end entity clbv4_wr_ref_top;
architecture top of clbv4_wr_ref_top is
-----------------------------------------------------------------------------
-- Signals
-----------------------------------------------------------------------------
-- clock and reset
signal reset_n : std_logic;
signal clk_sys_62m5 : std_logic;
signal rst_sys_62m5_n : std_logic;
signal rst_ref_62m5_n : std_logic;
signal clk_ref_62m5 : std_logic;
signal clk_dmtd_62m5 : std_logic;
signal clk_ref_div2 : std_logic;
signal clk_ext_10m : std_logic;
-- I2C EEPROM
signal eeprom_sda_in : std_logic;
signal eeprom_sda_out : std_logic;
signal eeprom_scl_in : std_logic;
signal eeprom_scl_out : std_logic;
-- SFP
signal sfp_sda_in : std_logic;
signal sfp_sda_out : std_logic;
signal sfp_scl_in : std_logic;
signal sfp_scl_out : std_logic;
-- OneWire
signal onewire_data : std_logic;
signal onewire_oe : std_logic;
-- LEDs and GPIO
signal wrc_abscal_txts_out : std_logic;
signal wrc_abscal_rxts_out : std_logic;
signal wrc_pps_out : std_logic;
signal wrc_pps_led : std_logic;
signal wrc_pps_in : std_logic;
signal svec_led : std_logic_vector(15 downto 0);
-- DIO Mezzanine
signal dio_in : std_logic_vector(4 downto 0);
signal dio_out : std_logic_vector(4 downto 0);
-- BullsEye connector outputs
signal txts_oddr : std_logic;
signal rxts_oddr : std_logic;
signal pps_oddr : std_logic;
signal clk_ref_62m5_oddr : std_logic;
signal clk_dmtd_62m5_oddr : std_logic;
begin -- architecture top
suicide<= '1';
reset_n <= not reset_i; -- Reset = high active on CLB
WDI <= '0';
WD_SET <="001"; --disable Watchdog
-----------------------------------------------------------------------------
-- The WR PTP core board package (WB Slave + WB Master)
-----------------------------------------------------------------------------
cmp_xwrc_board_clbv4 : xwrc_board_clbv4
generic map (
g_simulation => g_simulation,
g_with_external_clock_input => TRUE,
g_dpram_initf => g_dpram_initf,
g_fabric_iface => PLAIN)
port map (
areset_n_i => reset_n,
clk_125m_dmtd_n_i => clk_125m_dmtd_n_i,
clk_125m_dmtd_p_i => clk_125m_dmtd_p_i,
clk_125m_gtx_n_i => clk_125m_gtx_n_i,
clk_125m_gtx_p_i => clk_125m_gtx_p_i,
clk_10m_ext_i => clk_ext_10m,
clk_sys_62m5_o => clk_sys_62m5,
clk_ref_62m5_o => clk_ref_62m5,
clk_dmtd_62m5_o => clk_dmtd_62m5,
rst_sys_62m5_n_o => rst_sys_62m5_n,
rst_ref_62m5_n_o => rst_ref_62m5_n,
dac_refclk_cs_n_o => dac_refclk_cs_n_o,
dac_refclk_sclk_o => dac_refclk_sclk_o,
dac_refclk_din_o => dac_refclk_din_o,
dac_dmtd_cs_n_o => dac_dmtd_cs_n_o,
dac_dmtd_sclk_o => dac_dmtd_sclk_o,
dac_dmtd_din_o => dac_dmtd_din_o,
sfp_txp_o => sfp_txp_o,
sfp_txn_o => sfp_txn_o,
sfp_rxp_i => sfp_rxp_i,
sfp_rxn_i => sfp_rxn_i,
sfp_det_i => '0',
sfp_sda_i => sfp_sda_in,
sfp_sda_o => sfp_sda_out,
sfp_scl_i => sfp_scl_in,
sfp_scl_o => sfp_scl_out,
sfp_rate_select_o => sfp_rate_select_o,
sfp_tx_fault_i => sfp_tx_fault_i,
sfp_tx_disable_o => sfp_tx_disable_o,
sfp_los_i => sfp_los_i,
eeprom_sda_i => eeprom_sda_in,
eeprom_sda_o => eeprom_sda_out,
eeprom_scl_i => eeprom_scl_in,
eeprom_scl_o => eeprom_scl_out,
onewire_i => onewire_data,
onewire_oen_o => onewire_oe,
-- Uart
uart_rxd_i => uart_rxd_i,
uart_txd_o => uart_txd_o,
abscal_txts_o => wrc_abscal_txts_out,
abscal_rxts_o => wrc_abscal_rxts_out,
pps_ext_i => wrc_pps_in,
pps_p_o => wrc_pps_out,
pps_led_o => wrc_pps_led,
led_link_o => led_link_o,
led_act_o => led_act_o);
-- Tristates for SFP EEPROM
sfp_mod_def1_b <= '0' when sfp_scl_out = '0' else 'Z';
sfp_mod_def2_b <= '0' when sfp_sda_out = '0' else 'Z';
sfp_scl_in <= sfp_mod_def1_b;
sfp_sda_in <= sfp_mod_def2_b;
-- tri-state onewire access
onewire_b <= '0' when (onewire_oe = '1') else 'Z';
onewire_data <= onewire_b;
------------------------------------------------------------------------------
-- Digital I/O FMC Mezzanine connections
------------------------------------------------------------------------------
gen_dio_iobufs: for I in 0 to 4 generate
U_ibuf: IBUFDS
generic map (
DIFF_TERM => true)
port map (
O => dio_in(i),
I => dio_p_i(i),
IB => dio_n_i(i));
U_obuf : OBUFDS
port map (
I => dio_out(i),
O => dio_p_o(i),
OB => dio_n_o(i));
end generate;
-- Configure Digital I/Os 0 to 2 as outputs
dio_oe_n_o(2 downto 0) <= (others => '0');
-- Configure Digital I/Os 3 and 4 as inputs for external reference
dio_oe_n_o(3) <= '1'; -- for external 1-PPS
dio_oe_n_o(4) <= '1'; -- for external 10MHz clock
-- Configure Digital I/Os 3 to 4 inputs to be terminated.
dio_term_en_o <= "11000";
-- EEPROM I2C tri-states
dio_sda_b <= '0' when (eeprom_sda_out = '0') else 'Z';
eeprom_sda_in <= dio_sda_b;
dio_scl_b <= '0' when (eeprom_scl_out = '0') else 'Z';
eeprom_scl_in <= dio_scl_b;
-- Div by 2 reference clock to LEMO connector
process(clk_ref_62m5)
begin
if rising_edge(clk_ref_62m5) then
clk_ref_div2 <= not clk_ref_div2;
end if;
end process;
cmp_ibugds_extref: IBUFGDS
generic map (
DIFF_TERM => true)
port map (
O => clk_ext_10m,
I => dio_clk_p_i,
IB => dio_clk_n_i);
wrc_pps_in <= dio_in(3);
dio_out(0) <= wrc_pps_out;
dio_out(1) <= wrc_abscal_rxts_out;
dio_out(2) <= wrc_abscal_txts_out;
test_lemo <= wrc_pps_out;
pps_mon <= wrc_pps_out;
ref_clk_mon <= clk_ref_62m5;
-- LEDs
U_Extend_PPS : gc_extend_pulse
generic map (
g_width => 10000000)
port map (
clk_i => clk_ref_62m5,
rst_n_i => rst_ref_62m5_n,
pulse_i => wrc_pps_led,
extended_o => dio_led_top_o);
dio_led_bot_o <= '0';
------------------------------------------------------------------------------
-- BullsEye connector outputs
------------------------------------------------------------------------------
-- tx timestamp for absolute calibration
oddr_txts: ODDR
generic map(
DDR_CLK_EDGE => "SAME_EDGE",
INIT => '0',
SRTYPE => "SYNC")
port map(
Q => txts_oddr,
C => clk_ref_62m5,
CE => '1',
D1 => wrc_abscal_txts_out,
D2 => wrc_abscal_txts_out,
R => '0',
S => '0');
obuf_txts: OBUFDS
generic map(
CAPACITANCE => "DONT_CARE",
IOSTANDARD => "DEFAULT",
SLEW => "SLOW")
port map(
O => txts_p_o,
OB => txts_n_o,
I => txts_oddr);
-- rx timestamp for absolute calibration
oddr_rxts: ODDR
generic map(
DDR_CLK_EDGE => "SAME_EDGE",
INIT => '0',
SRTYPE => "SYNC")
port map(
Q => rxts_oddr,
C => clk_ref_62m5,
CE => '1',
D1 => wrc_abscal_rxts_out,
D2 => wrc_abscal_rxts_out,
R => '0',
S => '0');
obuf_rxts: OBUFDS
generic map(
CAPACITANCE => "DONT_CARE",
IOSTANDARD => "DEFAULT",
SLEW => "SLOW")
port map(
O => rxts_p_o,
OB => rxts_n_o,
I => rxts_oddr);
-- PPS (also used for absolute calibration)
oddr_pps: ODDR
generic map(
DDR_CLK_EDGE => "SAME_EDGE",
INIT => '0',
SRTYPE => "SYNC")
port map(
Q => pps_oddr,
C => clk_ref_62m5,
CE => '1',
D1 => wrc_pps_out,
D2 => wrc_pps_out,
R => '0',
S => '0');
obuf_pps: OBUFDS
generic map(
CAPACITANCE => "DONT_CARE",
IOSTANDARD => "DEFAULT",
SLEW => "SLOW")
port map(
O => pps_p_o,
OB => pps_n_o,
I => pps_oddr);
-- clk_ref_62m5
oddr_clk_ref_62m5: ODDR
generic map(
DDR_CLK_EDGE => "SAME_EDGE",
INIT => '0',
SRTYPE => "SYNC")
port map(
Q => clk_ref_62m5_oddr,
C => clk_ref_62m5,
CE => '1',
D1 => '1',
D2 => '0',
R => '0',
S => '0');
obuf_clk_ref_62m5: OBUFDS
generic map(
CAPACITANCE => "DONT_CARE",
IOSTANDARD => "DEFAULT",
SLEW => "SLOW")
port map(
O => clk_ref_62m5_p_o,
OB => clk_ref_62m5_n_o,
I => clk_ref_62m5_oddr);
-- clk_dmtd_62m5 (debug purposes)
oddr_clk_dmtd_62m5: ODDR
generic map(
DDR_CLK_EDGE => "SAME_EDGE",
INIT => '0',
SRTYPE => "SYNC")
port map(
Q => clk_dmtd_62m5_oddr,
C => clk_dmtd_62m5,
CE => '1',
D1 => '1',
D2 => '0',
R => '0',
S => '0');
obuf_clk_dmtd_62m5: OBUFDS
generic map(
CAPACITANCE => "DONT_CARE",
IOSTANDARD => "DEFAULT",
SLEW => "SLOW")
port map(
O => clk_dmtd_62m5_p_o,
OB => clk_dmtd_62m5_n_o,
I => clk_dmtd_62m5_oddr);
end architecture top;
top/clbv4_ref_design/clbv4_wr_ref_top.xdc 0 → 100644
View file @ 2b4daa08
# ---------------------------------------------------------------------------`
# -- Clocks/resets
# ---------------------------------------------------------------------------
# -- Local oscillators
#Bank 15 VCCO - 2.5 V -- CVPD-922-124.992 MHz PLL reference
set_property PACKAGE_PIN F17 [get_ports clk_125m_dmtd_p_i]
set_property IOSTANDARD LVDS_25 [get_ports clk_125m_dmtd_p_i]
set_property PACKAGE_PIN E17 [get_ports clk_125m_dmtd_n_i]
set_property IOSTANDARD LVDS_25 [get_ports clk_125m_dmtd_n_i]
create_clock -period 8.000 -name clk_125m_dmtd_p_i -waveform {0.000 4.000} [get_ports clk_125m_dmtd_p_i]
#create_clock -period 8.000 -name clk_125m_dmtd_n_i -waveform {0.000 4.000} [get_ports clk_125m_dmtd_n_i] # AR57109: "Only P side needs constraint"
create_generated_clock -name clk_dmtd -source [get_ports clk_125m_dmtd_p_i] -divide_by 2 [get_pins cmp_xwrc_board_clbv4/cmp_xwrc_platform/gen_default_plls.gen_kintex7_artix7_default_plls.gen_kintex7_artix7_direct_dmtd.clk_dmtd_reg/Q]
#Bank 116 -- 125.000 MHz GTP reference
set_property PACKAGE_PIN D6 [get_ports clk_125m_gtx_p_i]
set_property PACKAGE_PIN D5 [get_ports clk_125m_gtx_n_i]
create_clock -period 8.000 -name clk_125m_gtx_p_i -waveform {0.000 4.000} [get_ports clk_125m_gtx_p_i]
#create_clock -period 8.000 -name clk_125m_gtx_n_i -waveform {0.000 4.000} [get_ports clk_125m_gtx_n_i] # AR57109: "Only P side needs constraint"
create_clock -period 16.000 -name RXOUTCLK -waveform {0.000 8.000} [get_pins cmp_xwrc_board_clbv4/cmp_xwrc_platform/gen_phy_kintex7.cmp_gtx/U_GTX_INST/gtxe2_i/RXOUTCLK]
create_clock -period 16.000 -name TXOUTCLK -waveform {0.000 8.000} [get_pins cmp_xwrc_board_clbv4/cmp_xwrc_platform/gen_phy_kintex7.cmp_gtx/U_GTX_INST/gtxe2_i/TXOUTCLK]
create_clock -period 100.000 -name dio_clk_p_i -waveform {0.000 50.000} [get_ports dio_clk_p_i]
set_clock_groups -asynchronous \
-group {clk_sys } \
-group {clk_dmtd } \
-group {clk_125m_dmtd_p_i } \
-group {clk_125m_gtx_p_i } \
-group {RXOUTCLK} \
-group {TXOUTCLK} \
-group {clk_ext_mul } \
-group {dio_clk_p_i}
# ---------------------------------------------------------------------------
# -- SPI interface to DACs
# ---------------------------------------------------------------------------
#Bank 16 VCCO - 3.3 V
set_property PACKAGE_PIN B15 [get_ports dac_dmtd_din_o]
set_property IOSTANDARD LVCMOS33 [get_ports dac_dmtd_din_o]
set_property PACKAGE_PIN B14 [get_ports dac_dmtd_sclk_o]
set_property IOSTANDARD LVCMOS33 [get_ports dac_dmtd_sclk_o]
set_property PACKAGE_PIN A15 [get_ports dac_dmtd_cs_n_o]
set_property IOSTANDARD LVCMOS33 [get_ports dac_dmtd_cs_n_o]
set_property PACKAGE_PIN A13 [get_ports dac_refclk_din_o]
set_property IOSTANDARD LVCMOS33 [get_ports dac_refclk_din_o]
set_property PACKAGE_PIN A12 [get_ports dac_refclk_sclk_o]
set_property IOSTANDARD LVCMOS33 [get_ports dac_refclk_sclk_o]
set_property PACKAGE_PIN A14 [get_ports dac_refclk_cs_n_o]
set_property IOSTANDARD LVCMOS33 [get_ports dac_refclk_cs_n_o]
# ---------------------------------------------------------------------------
# -- SFP I/O for transceiver
# ---------------------------------------------------------------------------
#Bank 116
set_property PACKAGE_PIN B5 [get_ports sfp_rxn_i]
set_property PACKAGE_PIN B6 [get_ports sfp_rxp_i]
set_property PACKAGE_PIN A3 [get_ports sfp_txn_o]
set_property PACKAGE_PIN A4 [get_ports sfp_txp_o]
##Bank 14 VCCO - 3.3 V -- sfp detect NOT PRESENT
#set_property PACKAGE_PIN E26 [get_ports sfp_mod_def0_i]
#set_property IOSTANDARD LVCMOS33 [get_ports sfp_mod_def0_i]
#Bank 14 VCCO - 3.3 V -- scl
set_property PACKAGE_PIN J26 [get_ports sfp_mod_def1_b]
set_property IOSTANDARD LVCMOS33 [get_ports sfp_mod_def1_b]
#Bank 14 VCCO - 3.3 V -- sda
set_property PACKAGE_PIN H26 [get_ports sfp_mod_def2_b]
set_property IOSTANDARD LVCMOS33 [get_ports sfp_mod_def2_b]
#Bank 14 VCCO - 3.3 V NOT PRESENT
set_property PACKAGE_PIN G26 [get_ports sfp_rate_select_o]
set_property IOSTANDARD LVCMOS33 [get_ports sfp_rate_select_o]
#Bank 14 VCCO - 3.3 V
set_property PACKAGE_PIN C26 [get_ports sfp_tx_fault_i]
set_property IOSTANDARD LVCMOS33 [get_ports sfp_tx_fault_i]
#Bank 14 VCCO - 3.3 V
set_property PACKAGE_PIN D26 [get_ports sfp_tx_disable_o]
set_property IOSTANDARD LVCMOS33 [get_ports sfp_tx_disable_o]
#Bank 14 VCCO - 3.3 V
set_property PACKAGE_PIN F25 [get_ports sfp_los_i]
set_property IOSTANDARD LVCMOS33 [get_ports sfp_los_i]
# ---------------------------------------------------------------------------
# -- Onewire interface
# ---------------------------------------------------------------------------
#Bank 14 VCCO - 3.3 V
set_property PACKAGE_PIN L23 [get_ports onewire_b]
set_property IOSTANDARD LVCMOS33 [get_ports onewire_b]
# ---------------------------------------------------------------------------
# -- UART
# ---------------------------------------------------------------------------
#TEST & DEBUG
# Signal uart_rxd_i is an input in the design and must be connected to pin 21/13 (TXD_SCI) of U26 (CP2105)
# Signal uart_txd_o is an output in the design and must be connected to pin 20/12 (RXD_SCI) of U26 (CP2105)
# Rx signals are pulled down so the USB on the CLB and the USB on the G-Board can be OR-ed
#Bank 15 VCCO - 2.5 V
set_property PACKAGE_PIN D19 [get_ports uart_rxd_i]
set_property IOSTANDARD LVCMOS25 [get_ports uart_rxd_i]
set_property PULLDOWN true [get_ports uart_rxd_i]
set_property PACKAGE_PIN D20 [get_ports uart_txd_o]
set_property IOSTANDARD LVCMOS25 [get_ports uart_txd_o]
#Bank 15 VCCO - 1.8 V
#set_property PACKAGE_PIN B19 [get_ports USB_RX2]
#set_property IOSTANDARD LVCMOS25 [get_ports USB_RX2]
#set_property PULLDOWN true [get_ports USB_RX2]
#set_property PACKAGE_PIN C19 [get_ports USB_TX2]
#set_property IOSTANDARD LVCMOS25 [get_ports USB_TX2]
#USB Connection on Test&Debug Connector (J35)
#Bank 16 VCCO - 3.3 V
#set_property PACKAGE_PIN F13 [get_ports USBEXT_RX1]
#set_property IOSTANDARD LVCMOS33 [get_ports USBEXT_RX1]
#set_property PULLDOWN true [get_ports USBEXT_RX1]
#set_property PACKAGE_PIN F14 [get_ports USBEXT_TX1]
#set_property IOSTANDARD LVCMOS33 [get_ports USBEXT_TX1]
#set_property PACKAGE_PIN C13 [get_ports USBEXT_RX2]
#set_property IOSTANDARD LVCMOS33 [get_ports USBEXT_RX2]
#set_property PULLDOWN true [get_ports USBEXT_RX2]
#set_property PACKAGE_PIN C14 [get_ports USBEXT_TX2]
#set_property IOSTANDARD LVCMOS33 [get_ports USBEXT_TX2]
# ---------------------------------------------------------------------------
# -- WATCHDOG
# ---------------------------------------------------------------------------
set_property PACKAGE_PIN G12 [get_ports WDI]
set_property IOSTANDARD LVCMOS33 [get_ports WDI]
set_property PACKAGE_PIN F12 [get_ports {WD_SET[0]}]
set_property IOSTANDARD LVCMOS33 [get_ports {WD_SET[0]}]
set_property PACKAGE_PIN D14 [get_ports {WD_SET[1]}]
set_property IOSTANDARD LVCMOS33 [get_ports {WD_SET[1]}]
set_property PACKAGE_PIN D13 [get_ports {WD_SET[2]}]
set_property IOSTANDARD LVCMOS33 [get_ports {WD_SET[2]}]
# ---------------------------------------------------------------------------
# -- Miscellanous CLBv4 pins
# ---------------------------------------------------------------------------
#Bank 15 VCCO - 3.3 V
set_property PACKAGE_PIN C16 [get_ports led_act_o]
set_property IOSTANDARD LVCMOS25 [get_ports led_act_o]
#set_property PACKAGE_PIN C16 [get_ports {GPIO_LED[0]}]
#set_property IOSTANDARD LVCMOS25 [get_ports {GPIO_LED[0]}]
#set_property PACKAGE_PIN B16 [get_ports {GPIO_LED[1]}]
#set_property IOSTANDARD LVCMOS25 [get_ports {GPIO_LED[1]}]
#set_property PACKAGE_PIN B17 [get_ports {GPIO_LED[2]}]
#set_property IOSTANDARD LVCMOS25 [get_ports {GPIO_LED[2]}]
#set_property PACKAGE_PIN A17 [get_ports {GPIO_LED[3]}]
#set_property IOSTANDARD LVCMOS25 [get_ports {GPIO_LED[3]}]
#set_property PACKAGE_PIN A18 [get_ports {GPIO_LED[4]}]
#set_property IOSTANDARD LVCMOS25 [get_ports {GPIO_LED[4]}]
#set_property PACKAGE_PIN A19 [get_ports {GPIO_LED[5]}]
#set_property IOSTANDARD LVCMOS25 [get_ports {GPIO_LED[5]}]
set_property PACKAGE_PIN B16 [get_ports led_link_o]
set_property IOSTANDARD LVCMOS25 [get_ports led_link_o]
#Bank 16 VCCO - 3.3 V
set_property PACKAGE_PIN E11 [get_ports reset_i]
set_property IOSTANDARD LVCMOS33 [get_ports reset_i]
#Bank 15 VCCO - 2.5 V
set_property PACKAGE_PIN K15 [get_ports suicide]
set_property IOSTANDARD LVCMOS25 [get_ports suicide]
#Bank 16 VCCO - 3.3 V
set_property PACKAGE_PIN B11 [get_ports test_lemo]
set_property IOSTANDARD LVCMOS33 [get_ports test_lemo]
#Bank 14 VCCO - 3.3 V Monitoring signals output on External Debug Connector J35
set_property PACKAGE_PIN D25 [get_ports pps_mon]
set_property IOSTANDARD LVCMOS33 [get_ports pps_mon]
set_property PACKAGE_PIN F23 [get_ports ref_clk_mon]
set_property IOSTANDARD LVCMOS33 [get_ports ref_clk_mon]
# ---------------------------------------------------------------------------
# -- Digital I/O FMC Pins
# -- used in this design to output WR-aligned 1-PPS (in Slave mode) and input
# -- 10MHz & 1-PPS from external reference (in GrandMaster mode).
# ---------------------------------------------------------------------------
# -- Clock input from LEMO 5 on the mezzanine front panel. Used as 10MHz
# -- external reference input.
#CLK1_M2C_P
set_property PACKAGE_PIN Y22 [get_ports dio_clk_p_i]
set_property IOSTANDARD LVDS_25 [get_ports dio_clk_p_i]
#CLK1_M2C_N
set_property PACKAGE_PIN AA22 [get_ports dio_clk_n_i]
set_property IOSTANDARD LVDS_25 [get_ports dio_clk_n_i]
# -- Differential inputs, dio_p_i(N) inputs the current state of I/O (N+1) on
# -- the mezzanine front panel.
#LA00_P
set_property PACKAGE_PIN N21 [get_ports {dio_p_i[4]}]
set_property IOSTANDARD LVDS_25 [get_ports {dio_p_i[4]}]
#LA00_N
set_property PACKAGE_PIN N22 [get_ports {dio_n_i[4]}]
set_property IOSTANDARD LVDS_25 [get_ports {dio_n_i[4]}]
#LA03_P
set_property PACKAGE_PIN P16 [get_ports {dio_p_i[3]}]
set_property IOSTANDARD LVDS_25 [get_ports {dio_p_i[3]}]
#LA03_N
set_property PACKAGE_PIN N17 [get_ports {dio_n_i[3]}]
set_property IOSTANDARD LVDS_25 [get_ports {dio_n_i[3]}]
#LA16_P
set_property PACKAGE_PIN AB26 [get_ports {dio_p_i[2]}]
set_property IOSTANDARD LVDS_25 [get_ports {dio_p_i[2]}]
#LA16_N
set_property PACKAGE_PIN AC26 [get_ports {dio_n_i[2]}]
set_property IOSTANDARD LVDS_25 [get_ports {dio_n_i[2]}]
#LA20_P
set_property PACKAGE_PIN K20 [get_ports {dio_p_i[1]}]
set_property IOSTANDARD LVDS_25 [get_ports {dio_p_i[1]}]
#LA20_N
set_property PACKAGE_PIN J20 [get_ports {dio_n_i[1]}]
set_property IOSTANDARD LVDS_25 [get_ports {dio_n_i[1]}]
#LA33_P
set_property PACKAGE_PIN P19 [get_ports {dio_p_i[0]}]
set_property IOSTANDARD LVDS_25 [get_ports {dio_p_i[0]}]
#LA33_N
set_property PACKAGE_PIN P20 [get_ports {dio_n_i[0]}]
set_property IOSTANDARD LVDS_25 [get_ports {dio_n_i[0]}]
# -- Differential outputs. When the I/O (N+1) is configured as output (i.e. when
# -- dio_oe_n_o(N) = 0), the value of dio_p_o(N) determines the logic state
# -- of I/O (N+1) on the front panel of the mezzanine
#LA04_P
set_property PACKAGE_PIN N18 [get_ports {dio_p_o[4]}]
set_property IOSTANDARD LVDS_25 [get_ports {dio_p_o[4]}]
#LA04_N
set_property PACKAGE_PIN M19 [get_ports {dio_n_o[4]}]
set_property IOSTANDARD LVDS_25 [get_ports {dio_n_o[4]}]
#LA07_P
set_property PACKAGE_PIN U19 [get_ports {dio_p_o[3]}]
set_property IOSTANDARD LVDS_25 [get_ports {dio_p_o[3]}]
#LA07_N
set_property PACKAGE_PIN U20 [get_ports {dio_n_o[3]}]
set_property IOSTANDARD LVDS_25 [get_ports {dio_n_o[3]}]
#LA08_P
set_property PACKAGE_PIN W20 [get_ports {dio_p_o[2]}]
set_property IOSTANDARD LVDS_25 [get_ports {dio_p_o[2]}]
#LA08_N
set_property PACKAGE_PIN Y21 [get_ports {dio_n_o[2]}]
set_property IOSTANDARD LVDS_25 [get_ports {dio_n_o[2]}]
#LA28_P
set_property PACKAGE_PIN M21 [get_ports {dio_p_o[1]}]
set_property IOSTANDARD LVDS_25 [get_ports {dio_p_o[1]}]
#LA28_N
set_property PACKAGE_PIN M22 [get_ports {dio_n_o[1]}]
set_property IOSTANDARD LVDS_25 [get_ports {dio_n_o[1]}]
#LA29_P
set_property PACKAGE_PIN N19 [get_ports {dio_p_o[0]}]
set_property IOSTANDARD LVDS_25 [get_ports {dio_p_o[0]}]
#LA29_N
set_property PACKAGE_PIN M20 [get_ports {dio_n_o[0]}]
set_property IOSTANDARD LVDS_25 [get_ports {dio_n_o[0]}]
# -- Output enable. When dio_oe_n_o(N) is 0, connector (N+1) on the front
# -- panel is configured as an output.
#LA05_P
set_property PACKAGE_PIN AE22 [get_ports {dio_oe_n_o[4]}]
set_property IOSTANDARD LVCMOS25 [get_ports {dio_oe_n_o[4]}]
#LA11_P
set_property PACKAGE_PIN U26 [get_ports {dio_oe_n_o[3]}]
set_property IOSTANDARD LVCMOS25 [get_ports {dio_oe_n_o[3]}]
#LA15_N
set_property PACKAGE_PIN AB25 [get_ports {dio_oe_n_o[2]}]
set_property IOSTANDARD LVCMOS25 [get_ports {dio_oe_n_o[2]}]
#LA24_N
set_property PACKAGE_PIN N23 [get_ports {dio_oe_n_o[1]}]
set_property IOSTANDARD LVCMOS25 [get_ports {dio_oe_n_o[1]}]
#LA30_P
set_property PACKAGE_PIN P24 [get_ports {dio_oe_n_o[0]}]
set_property IOSTANDARD LVCMOS25 [get_ports {dio_oe_n_o[0]}]
# -- Termination enable. When dio_term_en_o(N) is 1, connector (N+1) on the front
# -- panel is 50-ohm terminated
#LA09_N
set_property PACKAGE_PIN P25 [get_ports {dio_term_en_o[4]}]
set_property IOSTANDARD LVCMOS25 [get_ports {dio_term_en_o[4]}]
#LA09_P
set_property PACKAGE_PIN R25 [get_ports {dio_term_en_o[3]}]
set_property IOSTANDARD LVCMOS25 [get_ports {dio_term_en_o[3]}]
#LA05_N
set_property PACKAGE_PIN AF22 [get_ports {dio_term_en_o[2]}]
set_property IOSTANDARD LVCMOS25 [get_ports {dio_term_en_o[2]}]
#LA06_N
set_property PACKAGE_PIN AF25 [get_ports {dio_term_en_o[1]}]
set_property IOSTANDARD LVCMOS25 [get_ports {dio_term_en_o[1]}]
#LA30_N
set_property PACKAGE_PIN N24 [get_ports {dio_term_en_o[0]}]
set_property IOSTANDARD LVCMOS25 [get_ports {dio_term_en_o[0]}]
# -- Two LEDs on the mezzanine panel. Only Top one is currently used - to
# -- blink 1-PPS.
#LA01_P
set_property PACKAGE_PIN R21 [get_ports dio_led_top_o]
set_property IOSTANDARD LVCMOS25 [get_ports dio_led_top_o]
#LA01_N
set_property PACKAGE_PIN P21 [get_ports dio_led_bot_o]
set_property IOSTANDARD LVCMOS25 [get_ports dio_led_bot_o]
# -- I2C interface for accessing FMC EEPROM. Deprecated, was used in
# -- pre-v3.0 releases to store WRPC configuration. Now we use Flash for this.
#Bank 14 VCCO - 3.3 V
set_property PACKAGE_PIN J25 [get_ports dio_scl_b]
set_property IOSTANDARD LVCMOS33 [get_ports dio_scl_b]
set_property PACKAGE_PIN J24 [get_ports dio_sda_b]
set_property IOSTANDARD LVCMOS33 [get_ports dio_sda_b]
# ---------------------------------------------------------------------------
# -- Bulls-eye connector outputs
# ---------------------------------------------------------------------------
#Bank 34 VCCO - 1.8 V -- BullsEye 1
set_property PACKAGE_PIN U6 [get_ports txts_p_o]
set_property IOSTANDARD LVDS [get_ports txts_p_o]
#Bank 34 VCCO - 1.8 V -- BullsEye 2
set_property PACKAGE_PIN U5 [get_ports txts_n_o]
set_property IOSTANDARD LVDS [get_ports txts_n_o]
#Bank 34 VCCO - 1.8 V -- BullsEye 3
set_property PACKAGE_PIN U2 [get_ports rxts_p_o]
set_property IOSTANDARD LVDS [get_ports rxts_p_o]
#Bank 34 VCCO - 1.8 V -- BullsEye 4
set_property PACKAGE_PIN U1 [get_ports rxts_n_o]
set_property IOSTANDARD LVDS [get_ports rxts_n_o]
#Bank 15 VCCO - 2.5 V -- BullsEye 5
set_property PACKAGE_PIN D15 [get_ports clk_ref_62m5_p_o]
set_property IOSTANDARD LVDS_25 [get_ports clk_ref_62m5_p_o]
#Bank 15 VCCO - 2.5 V -- BullsEye 6
set_property PACKAGE_PIN D16 [get_ports clk_ref_62m5_n_o]
set_property IOSTANDARD LVDS_25 [get_ports clk_ref_62m5_n_o]
#Bank 15 VCCO - 2.5 V -- BullsEye 7
set_property PACKAGE_PIN C17 [get_ports pps_p_o]
set_property IOSTANDARD LVDS_25 [get_ports pps_p_o]
#Bank 15 VCCO - 2.5 V -- BullsEye 8
set_property PACKAGE_PIN C18 [get_ports pps_n_o]
set_property IOSTANDARD LVDS_25 [get_ports pps_n_o]
#Bank 34 VCCO - 1.8 V -- BullsEye 12
set_property PACKAGE_PIN V3 [get_ports clk_dmtd_62m5_p_o]
set_property IOSTANDARD LVDS [get_ports clk_dmtd_62m5_p_o]
#Bank 34 VCCO - 1.8 V -- BullsEye 13
set_property PACKAGE_PIN W3 [get_ports clk_dmtd_62m5_n_o]
set_property IOSTANDARD LVDS [get_ports clk_dmtd_62m5_n_o]
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