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White Rabbit core collection
Commits
1cb9d610
Commit
1cb9d610
authored
Mar 06, 2019
by
Grzegorz Daniluk
Browse files
Options
Browse Files
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Plain Diff
Merge branch 'switch-v4-merge'
parents
15fd89fd
a85a7e00
Expand all
Show whitespace changes
Inline
Side-by-side
Showing
11 changed files
with
407 additions
and
515 deletions
+407
-515
nic_buffer.vhd
modules/wrsw_nic/nic_buffer.vhd
+4
-3
nic_descriptor_manager.vhd
modules/wrsw_nic/nic_descriptor_manager.vhd
+45
-76
nic_descriptors_pkg.vhd
modules/wrsw_nic/nic_descriptors_pkg.vhd
+20
-22
nic_elastic_buffer.vhd
modules/wrsw_nic/nic_elastic_buffer.vhd
+12
-10
nic_rx_fsm.vhd
modules/wrsw_nic/nic_rx_fsm.vhd
+107
-112
nic_tx_fsm.vhd
modules/wrsw_nic/nic_tx_fsm.vhd
+151
-197
nic_wbgen2_pkg.vhd
modules/wrsw_nic/nic_wbgen2_pkg.vhd
+4
-6
nic_wishbone_slave.vhd
modules/wrsw_nic/nic_wishbone_slave.vhd
+21
-47
wr_nic.wb
modules/wrsw_nic/wr_nic.wb
+10
-15
wrsw_nic.vhd
modules/wrsw_nic/wrsw_nic.vhd
+10
-8
xwrsw_nic.vhd
modules/wrsw_nic/xwrsw_nic.vhd
+23
-19
No files found.
modules/wrsw_nic/nic_buffer.vhd
View file @
1cb9d610
...
...
@@ -78,7 +78,8 @@ begin -- syn
generic
map
(
g_data_width
=>
32
,
g_size
=>
2
**
g_memsize_log2
,
g_dual_clock
=>
false
)
g_dual_clock
=>
false
,
g_with_byte_enable
=>
false
)
port
map
(
-- host port
rst_n_i
=>
rst_n_i
,
...
...
modules/wrsw_nic/nic_descriptor_manager.vhd
View file @
1cb9d610
...
...
@@ -28,13 +28,12 @@ library work;
use
work
.
nic_constants_pkg
.
all
;
use
work
.
nic_descriptors_pkg
.
all
;
entity
nic_descriptor_manager
is
generic
(
g_desc_mode
:
string
:
=
"tx"
;
g_num_descriptors
:
integer
;
g_num_descriptors_log2
:
integer
);
g_num_descriptors_log2
:
integer
;
g_port_mask_bits
:
integer
:
=
32
);
--worth using only in TX mode
port
(
clk_sys_i
:
in
std_logic
;
rst_n_i
:
in
std_logic
;
...
...
@@ -77,7 +76,7 @@ end nic_descriptor_manager;
architecture
behavioral
of
nic_descriptor_manager
is
type
t_desc_arb_state
is
(
ARB_
DISABLED
,
ARB_
START_SCAN
,
ARB_CHECK_EMPTY
,
ARB_FETCH
,
ARB_GRANT
,
ARB_UPDATE
,
ARB_WRITE_DESC
);
type
t_desc_arb_state
is
(
ARB_START_SCAN
,
ARB_CHECK_EMPTY
,
ARB_FETCH
,
ARB_GRANT
,
ARB_UPDATE
,
ARB_WRITE_DESC
);
signal
state
:
t_desc_arb_state
;
...
...
@@ -85,15 +84,8 @@ architecture behavioral of nic_descriptor_manager is
signal
granted_desc_tx
:
t_tx_descriptor
;
signal
granted_desc_rx
:
t_rx_descriptor
;
signal
granted_desc_idx
:
unsigned
(
g_num_descriptors_log2
-1
downto
0
);
signal
desc_idx_d0
:
unsigned
(
g_num_descriptors_log2
-1
downto
0
);
signal
desc_idx
:
unsigned
(
g_num_descriptors_log2
-1
downto
0
);
signal
desc_subreg
:
unsigned
(
1
downto
0
);
signal
cntr
:
unsigned
(
1
downto
0
);
signal
check_count
:
unsigned
(
g_num_descriptors_log2
downto
0
);
signal
stupid_hack
:
std_logic
;
impure
function
f_write_marshalling
(
index
:
integer
)
return
std_logic_vector
is
...
...
@@ -112,6 +104,15 @@ begin -- behavioral
cur_desc_idx_o
<=
std_logic_vector
(
desc_idx
);
--GD can do that, those outputs are validated by desc_grant_o
--and nic_rx_fsm stores it in internal register too
GEN_TXDESC_CUR
:
if
g_desc_mode
=
"tx"
generate
txdesc_current_o
<=
granted_desc_tx
;
end
generate
;
GEN_RXDESC_CUR
:
if
g_desc_mode
=
"rx"
generate
rxdesc_current_o
<=
granted_desc_rx
;
end
generate
;
p_rxdesc_arbiter
:
process
(
clk_sys_i
,
rst_n_i
)
variable
tmp_desc_rx
:
t_rx_descriptor
;
variable
tmp_desc_tx
:
t_tx_descriptor
;
...
...
@@ -121,7 +122,7 @@ begin -- behavioral
if
(
rst_n_i
=
'0'
)
then
desc_write_done_o
<=
'0'
;
desc_grant_o
<=
'0'
;
state
<=
ARB_
DISABLED
;
state
<=
ARB_
START_SCAN
;
desc_idx
<=
(
others
=>
'0'
);
desc_subreg
<=
(
others
=>
'0'
);
dtbl_wr_o
<=
'0'
;
...
...
@@ -130,36 +131,24 @@ begin -- behavioral
else
case
state
is
when
ARB_DISABLED
=>
desc_idx
<=
(
others
=>
'0'
);
desc_subreg
<=
(
others
=>
'0'
);
if
(
enable_i
=
'1'
)
then
-- dtbl_rd_o <= '1';
state
<=
ARB_START_SCAN
;
desc_idx
<=
(
others
=>
'0'
);
check_count
<=
(
others
=>
'0'
);
end
if
;
when
ARB_START_SCAN
=>
if
(
enable_i
=
'0'
)
then
state
<=
ARB_DISABLED
;
else
-- wait until the current descriptor is read from the memorry
state
<=
ARB_CHECK_EMPTY
;
-- dtbl_rd_o <='1';
desc_subreg
<=
(
others
=>
'0'
);
dtbl_wr_o
<=
'0'
;
if
(
enable_i
=
'1'
)
then
state
<=
ARB_CHECK_EMPTY
;
else
desc_idx
<=
(
others
=>
'0'
);
end
if
;
when
ARB_CHECK_EMPTY
=>
p_unmarshall_rx_descriptor
(
dtbl_data_i
,
1
,
tmp_desc_rx
);
p_unmarshall_tx_descriptor
(
dtbl_data_i
,
1
,
tmp_desc_tx
);
if
((
tmp_desc_rx
.
empty
=
'1'
and
g_desc_mode
=
"rx"
)
or
(
tmp_desc_tx
.
ready
=
'1'
and
g_desc_mode
=
"tx"
))
then
dtbl_wr_o
<=
'0'
;
tmp_desc_rx
:
=
f_unmarshall_rx_descriptor
(
dtbl_data_i
,
1
);
tmp_desc_tx
:
=
f_unmarshall_tx_descriptor
(
dtbl_data_i
,
1
);
granted_desc_tx
<=
tmp_desc_tx
;
granted_desc_rx
<=
tmp_desc_rx
;
if
((
tmp_desc_rx
.
empty
=
'1'
and
g_desc_mode
=
"rx"
)
or
(
tmp_desc_tx
.
ready
=
'1'
and
g_desc_mode
=
"tx"
))
then
desc_subreg
<=
"01"
;
state
<=
ARB_FETCH
;
bna_o
<=
'0'
;
...
...
@@ -168,21 +157,22 @@ begin -- behavioral
end
if
;
when
ARB_FETCH
=>
dtbl_wr_o
<=
'0'
;
case
desc_subreg
is
when
"10"
=>
-- ignore the timestamps for RX
-- descriptors (they're
-- write-only by the NIC)
p_unmarshall_tx_descriptor
(
dtbl_data_i
,
2
,
tmp_desc_tx
);
tmp_desc_tx
:
=
f_unmarshall_tx_descriptor
(
dtbl_data_i
,
2
);
granted_desc_tx
.
len
<=
tmp_desc_tx
.
len
;
granted_desc_tx
.
offset
<=
tmp_desc_tx
.
offset
;
when
"11"
=>
p_unmarshall_tx_descriptor
(
dtbl_data_i
,
3
,
tmp_desc_tx
);
-- TX
granted_desc_tx
.
dpm
<=
tmp_desc_tx
.
dpm
;
tmp_desc_tx
:
=
f_unmarshall_tx_descriptor
(
dtbl_data_i
,
3
);
-- TX
granted_desc_tx
.
dpm
(
g_port_mask_bits
-1
downto
0
)
<=
tmp_desc_tx
.
dpm
(
g_port_mask_bits
-1
downto
0
)
;
p_unmarshall_rx_descriptor
(
dtbl_data_i
,
3
,
tmp_desc_rx
);
-- RX
tmp_desc_rx
:
=
f_unmarshall_rx_descriptor
(
dtbl_data_i
,
3
);
-- RX
granted_desc_rx
.
len
<=
tmp_desc_rx
.
len
;
granted_desc_rx
.
offset
<=
tmp_desc_rx
.
offset
;
...
...
@@ -193,67 +183,46 @@ begin -- behavioral
desc_subreg
<=
desc_subreg
+
1
;
when
ARB_GRANT
=>
dtbl_wr_o
<=
'0'
;
desc_subreg
<=
"11"
;
if
(
desc_request_next_i
=
'1'
)
then
desc_grant_o
<=
'1'
;
if
(
g_desc_mode
=
"tx"
)
then
txdesc_current_o
<=
granted_desc_tx
;
elsif
(
g_desc_mode
=
"rx"
)
then
rxdesc_current_o
<=
granted_desc_rx
;
end
if
;
state
<=
ARB_UPDATE
;
end
if
;
desc_write_done_o
<=
'0'
;
when
ARB_UPDATE
=>
dtbl_wr_o
<=
'0'
;
desc_grant_o
<=
'0'
;
desc_subreg
<=
"11"
;
if
(
desc_write_i
=
'1'
)
then
if
(
g_desc_mode
=
"rx"
)
then
granted_desc_rx
<=
rxdesc_new_i
;
elsif
(
g_desc_mode
=
"tx"
)
then
granted_desc_tx
<=
txdesc_new_i
;
end
if
;
desc_subreg
<=
(
others
=>
'0'
);
-- dtbl_rd_o <= '0';
state
<=
ARB_WRITE_DESC
;
cntr
<=
"00"
;
end
if
;
when
ARB_WRITE_DESC
=>
cntr
<=
cntr
+
1
;
-- fprint(output,l, "WriteDesc %b %b\n",fo(cntr),fo(f_write_marshalling(1)));
case
cntr
is
when
"00"
=>
desc_subreg
<=
"00"
;
dtbl_data_o
<=
f_write_marshalling
(
1
);
dtbl_wr_o
<=
'1'
;
when
"01"
=>
desc_subreg
<=
"01"
;
dtbl_data_o
<=
f_write_marshalling
(
2
);
dtbl_wr_o
<=
'1'
;
when
"10"
=>
desc_subreg
<=
"10"
;
dtbl_data_o
<=
f_write_marshalling
(
3
);
dtbl_wr_o
<=
'1'
;
when
"11"
=>
dtbl_data_o
<=
f_write_marshalling
(
to_integer
(
desc_subreg
));
if
(
desc_subreg
=
"10"
)
then
dtbl_wr_o
<=
'0'
;
desc_subreg
<=
(
others
=>
'0'
);
desc_subreg
<=
"00"
;
state
<=
ARB_START_SCAN
;
if
(
desc_reload_current_i
=
'0'
)
then
desc_idx
<=
desc_idx
+
1
;
end
if
;
desc_write_done_o
<=
'1'
;
when
others
=>
null
;
end
case
;
else
dtbl_wr_o
<=
'1'
;
desc_subreg
<=
desc_subreg
+
1
;
end
if
;
when
others
=>
null
;
end
case
;
...
...
modules/wrsw_nic/nic_descriptors_pkg.vhd
View file @
1cb9d610
...
...
@@ -65,13 +65,11 @@ package nic_descriptors_pkg is
function
f_marshall_rx_descriptor
(
desc
:
t_rx_descriptor
;
regnum
:
integer
)
return
std_logic_vector
;
procedure
p_unmarshall_tx_descriptor
(
mem_input
:
in
std_logic_vector
(
31
downto
0
);
regnum
:
in
integer
;
desc
:
inout
t_tx_descriptor
);
function
f_unmarshall_tx_descriptor
(
mem_input
:
std_logic_vector
(
31
downto
0
);
regnum
:
integer
)
return
t_tx_descriptor
;
procedure
p_unmarshall_rx_descriptor
(
mem_input
:
in
std_logic_vector
(
31
downto
0
);
regnum
:
in
integer
;
desc
:
inout
t_rx_descriptor
);
function
f_unmarshall_rx_descriptor
(
mem_input
:
std_logic_vector
(
31
downto
0
);
regnum
:
integer
)
return
t_rx_descriptor
;
function
f_resize_slv
(
x
:
std_logic_vector
;
newsize
:
integer
)
return
std_logic_vector
;
...
...
@@ -95,9 +93,9 @@ package body NIC_descriptors_pkg is
begin
case
regnum
is
when
1
=>
tmp
:
=
desc
.
ts_id
&
x"000"
&
desc
.
pad_e
&
desc
.
ts_e
&
desc
.
error
&
desc
.
ready
;
when
2
=>
tmp
:
=
f_resize_slv
(
desc
.
len
,
16
)
&
f_resize_slv
(
desc
.
offset
,
16
);
when
3
=>
tmp
:
=
desc
.
dpm
;
when
3
=>
tmp
:
=
desc
.
ts_id
&
x"000"
&
desc
.
pad_e
&
desc
.
ts_e
&
desc
.
error
&
desc
.
ready
;
when
0
=>
tmp
:
=
f_resize_slv
(
desc
.
len
,
16
)
&
f_resize_slv
(
desc
.
offset
,
16
);
when
1
=>
tmp
:
=
desc
.
dpm
;
when
others
=>
null
;
end
case
;
...
...
@@ -108,9 +106,9 @@ package body NIC_descriptors_pkg is
variable
tmp
:
std_logic_vector
(
31
downto
0
);
begin
case
regnum
is
when
1
=>
tmp
:
=
"0000000000000000"
&
desc
.
ts_incorrect
&
desc
.
got_ts
&
desc
.
port_id
&
"000000"
&
desc
.
error
&
desc
.
empty
;
when
2
=>
tmp
:
=
desc
.
ts_f
&
desc
.
ts_r
;
when
3
=>
tmp
:
=
f_resize_slv
(
desc
.
len
,
16
)
&
f_resize_slv
(
desc
.
offset
,
16
);
when
3
=>
tmp
:
=
"0000000000000000"
&
desc
.
ts_incorrect
&
desc
.
got_ts
&
desc
.
port_id
&
"000000"
&
desc
.
error
&
desc
.
empty
;
when
0
=>
tmp
:
=
desc
.
ts_f
&
desc
.
ts_r
;
when
1
=>
tmp
:
=
f_resize_slv
(
desc
.
len
,
16
)
&
f_resize_slv
(
desc
.
offset
,
16
);
when
others
=>
null
;
end
case
;
...
...
@@ -119,11 +117,10 @@ package body NIC_descriptors_pkg is
end
f_marshall_rx_descriptor
;
procedure
p_unmarshall_tx_descriptor
(
mem_input
:
in
std_logic_vector
(
31
downto
0
);
regnum
:
in
integer
;
desc
:
inout
t_tx_descriptor
)
is
function
f_unmarshall_tx_descriptor
(
mem_input
:
std_logic_vector
(
31
downto
0
);
regnum
:
integer
)
return
t_tx_descriptor
is
variable
desc
:
t_tx_descriptor
;
begin
case
regnum
is
when
1
=>
desc
.
ts_id
:
=
mem_input
(
31
downto
16
);
...
...
@@ -138,13 +135,13 @@ package body NIC_descriptors_pkg is
desc
.
dpm
:
=
mem_input
;
when
others
=>
null
;
end
case
;
end
p_unmarshall_tx_descriptor
;
return
desc
;
end
f_unmarshall_tx_descriptor
;
procedure
p_unmarshall_rx_descriptor
(
mem_input
:
in
std_logic_vector
(
31
downto
0
);
regnum
:
in
integer
;
desc
:
inout
t_rx_descriptor
)
is
function
f_unmarshall_rx_descriptor
(
mem_input
:
std_logic_vector
(
31
downto
0
);
regnum
:
integer
)
return
t_rx_descriptor
is
variable
desc
:
t_rx_descriptor
;
begin
case
regnum
is
when
1
=>
desc
.
empty
:
=
mem_input
(
0
);
...
...
@@ -162,7 +159,8 @@ package body NIC_descriptors_pkg is
desc
.
offset
:
=
mem_input
(
c_nic_buf_size_log2
-1
downto
0
);
when
others
=>
null
;
end
case
;
end
p_unmarshall_rx_descriptor
;
return
desc
;
end
f_unmarshall_rx_descriptor
;
end
package
body
;
modules/wrsw_nic/nic_elastic_buffer.vhd
View file @
1cb9d610
...
...
@@ -48,7 +48,8 @@ architecture rtl of nic_elastic_buffer is
signal
fifo_out_ser
:
std_logic_vector
(
c_fifo_width
-1
downto
0
);
signal
fifo_full
:
std_logic
;
signal
fifo_empty
:
std_logic
;
signal
fifo_usedw
:
std_logic_vector
(
log2
(
g_depth
)
-1
downto
0
);
signal
fifo_almost_empty
:
std_logic
;
signal
fifo_almost_full
:
std_logic
;
signal
output_valid
:
std_logic
;
signal
got_empty
:
std_logic
;
...
...
@@ -105,16 +106,12 @@ begin -- rtl
p_gen_stall
:
process
(
clk_sys_i
)
begin
if
rising_edge
(
clk_sys_i
)
then
if
rst_n_i
=
'0'
then
stall_int
<=
'0'
;
else
if
(
unsigned
(
fifo_usedw
)
<
g_depth
/
2
)
then
if
rst_n_i
=
'0'
or
fifo_almost_empty
=
'1'
then
stall_int
<=
'0'
;
elsif
(
unsigned
(
fifo_usedw
)
>
g_depth
-5
)
then
elsif
fifo_almost_full
=
'1'
then
stall_int
<=
'1'
;
end
if
;
end
if
;
end
if
;
end
process
;
snk_out
.
stall
<=
fifo_in
.
sof
or
stall_int
;
...
...
@@ -135,7 +132,11 @@ begin -- rtl
generic
map
(
g_data_width
=>
c_fifo_width
,
g_size
=>
g_depth
,
g_with_count
=>
true
)
g_with_almost_empty
=>
true
,
g_with_almost_full
=>
true
,
g_almost_empty_threshold
=>
g_depth
/
2
,
g_almost_full_threshold
=>
g_depth
-5
,
g_with_count
=>
false
)
port
map
(
rst_n_i
=>
rst_n_i
,
clk_i
=>
clk_sys_i
,
...
...
@@ -145,7 +146,8 @@ begin -- rtl
q_o
=>
fifo_out_ser
,
empty_o
=>
fifo_empty
,
full_o
=>
fifo_full
,
count_o
=>
fifo_usedw
almost_empty_o
=>
fifo_almost_empty
,
almost_full_o
=>
fifo_almost_full
);
fab_o
.
data
<=
fifo_out_ser
(
15
downto
0
);
...
...
modules/wrsw_nic/nic_rx_fsm.vhd
View file @
1cb9d610
...
...
@@ -109,7 +109,6 @@ architecture behavioral of NIC_RX_FSM is
signal
cur_rx_desc
:
t_rx_descriptor
;
signal
state
:
t_rx_fsm_state
;
signal
rx_avail
:
unsigned
(
c_nic_buf_size_log2
-1
downto
0
);
signal
rx_length
:
unsigned
(
c_nic_buf_size_log2
-1
downto
0
);
signal
rx_dreq_mask
:
std_logic
;
signal
rx_rdreg_toggle
:
std_logic
;
...
...
@@ -206,7 +205,6 @@ begin
rx_newpacket
<=
'0'
;
rx_dreq_mask
<=
'0'
;
rx_buf_addr
<=
(
others
=>
'0'
);
rx_avail
<=
(
others
=>
'0'
);
buf_wr_o
<=
'0'
;
increase_addr
<=
'0'
;
...
...
@@ -265,7 +263,6 @@ begin
-- easier.
rx_buf_addr
<=
unsigned
(
cur_rx_desc
.
offset
(
c_nic_buf_size_log2
-1
downto
2
));
rx_avail
<=
unsigned
(
cur_rx_desc
.
len
);
rx_length
<=
(
others
=>
'0'
);
oob_sreg
<=
"001"
;
...
...
@@ -283,6 +280,7 @@ begin
when
RX_DATA
=>
buf_wr_o
<=
'0'
;
-- increase the address 1 cycle after committing the data to the memory
if
(
increase_addr
=
'1'
)
then
rx_buf_addr
<=
rx_buf_addr
+
1
;
...
...
@@ -290,16 +288,14 @@ begin
end
if
;
-- check if we still have enough space in the buffer
if
(
fab_in
.
dvalid
=
'1'
and
rx_
avail
(
rx_avail
'length
-1
downto
1
)
=
to_unsigned
(
0
,
rx_avail
'length
-1
))
then
if
(
fab_in
.
dvalid
=
'1'
and
rx_
length
(
rx_length
'length
-1
downto
1
)
=
unsigned
(
cur_rx_desc
.
len
(
rx_length
'length
-1
downto
1
)
))
then
-- no space? drop an error
cur_rx_desc
.
error
<=
'1'
;
buf_wr_o
<=
'0'
;
state
<=
RX_UPDATE_DESC
;
end
if
;
else
-- got an abort/error/end-of-frame?
if
(
wrf_terminate
=
'1'
)
then
-- check if the ends with an error and eventually indicate it.
-- For the NIC, there's no difference between an abort and an RX
-- error.
...
...
@@ -312,16 +308,15 @@ begin
-- packet before we are done with the memory flush and RX descriptor update
rx_dreq_mask
<=
'0'
;
end
if
;
---------------------------------------
-- got a valid payload word?
if
(
fab_in
.
dvalid
=
'1'
and
wrf_is_payload
=
'1'
)
then
-- check if it's a byte or a word transfer and update the length
-- and buffer space counters accordingly
if
(
fab_in
.
bytesel
=
'1'
)
then
rx_avail
<=
rx_avail
-
1
;
rx_length
<=
rx_length
+
1
;
else
rx_avail
<=
rx_avail
-
2
;
rx_length
<=
rx_length
+
2
;
end
if
;
...
...
@@ -339,7 +334,6 @@ begin
end
if
;
else
-- CPU is little endian
if
(
rx_rdreg_toggle
=
'0'
)
then
-- 1st word
rx_buf_data
(
15
downto
8
)
<=
fab_in
.
data
(
7
downto
0
);
...
...
@@ -354,7 +348,7 @@ begin
-- toggle the current word
rx_rdreg_toggle
<=
not
rx_rdreg_toggle
;
end
if
;
---------------------------------------
-- got a valid OOB word?
if
(
fab_in
.
dvalid
=
'1'
and
wrf_is_oob
=
'1'
)
then
...
...
@@ -382,7 +376,7 @@ begin
cur_rx_desc
.
got_ts
<=
'1'
;
end
if
;
end
if
;
---------------------------------------
-- we've got 2 valid word of the payload in rx_buf_data, write them to the
-- memory
...
...
@@ -397,9 +391,10 @@ begin
if
(
buf_grant_i
=
'1'
)
then
state
<=
RX_MEM_RESYNC
;
end
if
;
else
--
else
-- nothing to write
buf_wr_o
<=
'0'
;
--buf_wr_o <= '0';
end
if
;
end
if
;
...
...
@@ -469,7 +464,7 @@ begin
-------------------------------------------------------------------------------
-- helper process for producing the RX fabric data request signal (combinatorial)
-------------------------------------------------------------------------------
gen_rx_dreq
:
process
(
rx_dreq_mask
,
buf_grant_i
,
rx_rdreg_toggle
,
fab_in
,
regs_i
)
gen_rx_dreq
:
process
(
rx_dreq_mask
,
buf_grant_i
,
rx_rdreg_toggle
,
fab_in
,
regs_i
,
state
)
begin
-- make sure we don't have any incoming data when the reception is masked (e.g.
-- the NIC is updating the descriptors of finishing the memory write.
...
...
modules/wrsw_nic/nic_tx_fsm.vhd
View file @
1cb9d610
This diff is collapsed.
Click to expand it.
modules/wrsw_nic/nic_wbgen2_pkg.vhd
View file @
1cb9d610
...
...
@@ -3,7 +3,7 @@
---------------------------------------------------------------------------------------
-- File : nic_wbgen2_pkg.vhd
-- Author : auto-generated by wbgen2 from wr_nic.wb
-- Created :
Fri Jul 5 14:53:50
2013
-- Created :
Thu Mar 28 09:24:42
2013
-- Standard : VHDL'87
---------------------------------------------------------------------------------------
-- THIS FILE WAS GENERATED BY wbgen2 FROM SOURCE FILE wr_nic.wb
...
...
@@ -43,27 +43,25 @@ package nic_wbgen2_pkg is
type
t_nic_out_registers
is
record
cr_rx_en_o
:
std_logic
;
cr_tx_en_o
:
std_logic
;
cr_sw_rst_o
:
std_logic
;
sr_rec_o
:
std_logic
;
sr_rec_load_o
:
std_logic
;
sr_tx_done_o
:
std_logic
;
sr_tx_done_load_o
:
std_logic
;
sr_tx_error_o
:
std_logic
;
sr_tx_error_load_o
:
std_logic
;
reset_o
:
std_logic_vector
(
31
downto
0
);
reset_wr_o
:
std_logic
;
end
record
;
constant
c_nic_out_registers_init_value
:
t_nic_out_registers
:
=
(
cr_rx_en_o
=>
'0'
,
cr_tx_en_o
=>
'0'
,
cr_sw_rst_o
=>
'0'
,
sr_rec_o
=>
'0'
,
sr_rec_load_o
=>
'0'
,
sr_tx_done_o
=>
'0'
,
sr_tx_done_load_o
=>
'0'
,
sr_tx_error_o
=>
'0'
,
sr_tx_error_load_o
=>
'0'
,
reset_o
=>
(
others
=>
'0'
),
reset_wr_o
=>
'0'
sr_tx_error_load_o
=>
'0'
);
function
"or"
(
left
,
right
:
t_nic_in_registers
)
return
t_nic_in_registers
;
function
f_x_to_zero
(
x
:
std_logic
)
return
std_logic
;
...
...
modules/wrsw_nic/nic_wishbone_slave.vhd
View file @
1cb9d610
...
...
@@ -3,7 +3,7 @@
---------------------------------------------------------------------------------------
-- File : nic_wishbone_slave.vhd
-- Author : auto-generated by wbgen2 from wr_nic.wb
-- Created :
Fri Jul 5 14:53:50
2013
-- Created :
Thu Mar 28 09:24:42
2013
-- Standard : VHDL'87
---------------------------------------------------------------------------------------
-- THIS FILE WAS GENERATED BY wbgen2 FROM SOURCE FILE wr_nic.wb
...
...
@@ -69,6 +69,8 @@ architecture syn of nic_wishbone_slave is
signal
nic_cr_rx_en_int
:
std_logic
;
signal
nic_cr_tx_en_int
:
std_logic
;
signal
nic_cr_sw_rst_dly0
:
std_logic
;
signal
nic_cr_sw_rst_int
:
std_logic
;
signal
nic_dtx_rddata_int
:
std_logic_vector
(
31
downto
0
);
signal
nic_dtx_rd_int
:
std_logic
;
signal
nic_dtx_wr_int
:
std_logic
;
...
...
@@ -114,10 +116,10 @@ begin
rddata_reg
<=
"00000000000000000000000000000000"
;
nic_cr_rx_en_int
<=
'0'
;
nic_cr_tx_en_int
<=
'0'
;
nic_cr_sw_rst_int
<=
'0'
;
regs_o
.
sr_rec_load_o
<=
'0'
;
regs_o
.
sr_tx_done_load_o
<=
'0'
;
regs_o
.
sr_tx_error_load_o
<=
'0'
;
regs_o
.
reset_wr_o
<=
'0'
;
eic_idr_write_int
<=
'0'
;
eic_ier_write_int
<=
'0'
;
eic_isr_write_int
<=
'0'
;
...
...
@@ -127,10 +129,10 @@ begin
ack_sreg
(
9
)
<=
'0'
;
if
(
ack_in_progress
=
'1'
)
then
if
(
ack_sreg
(
0
)
=
'1'
)
then
nic_cr_sw_rst_int
<=
'0'
;
regs_o
.
sr_rec_load_o
<=
'0'
;
regs_o
.
sr_tx_done_load_o
<=
'0'
;
regs_o
.
sr_tx_error_load_o
<=
'0'
;
regs_o
.
reset_wr_o
<=
'0'
;
eic_idr_write_int
<=
'0'
;
eic_ier_write_int
<=
'0'
;
eic_isr_write_int
<=
'0'
;
...
...
@@ -139,7 +141,6 @@ begin
regs_o
.
sr_rec_load_o
<=
'0'
;
regs_o
.
sr_tx_done_load_o
<=
'0'
;
regs_o
.
sr_tx_error_load_o
<=
'0'
;
regs_o
.
reset_wr_o
<=
'0'
;
end
if
;
else
if
((
wb_cyc_i
=
'1'
)
and
(
wb_stb_i
=
'1'
))
then
...
...
@@ -150,9 +151,11 @@ begin
if
(
wb_we_i
=
'1'
)
then
nic_cr_rx_en_int
<=
wrdata_reg
(
0
);
nic_cr_tx_en_int
<=
wrdata_reg
(
1
);
nic_cr_sw_rst_int
<=
wrdata_reg
(
31
);
end
if
;
rddata_reg
(
0
)
<=
nic_cr_rx_en_int
;
rddata_reg
(
1
)
<=
nic_cr_tx_en_int
;
rddata_reg
(
31
)
<=
'X'
;
rddata_reg
(
2
)
<=
'X'
;
rddata_reg
(
3
)
<=
'X'
;
rddata_reg
(
4
)
<=
'X'
;
...
...
@@ -182,8 +185,7 @@ begin
rddata_reg
(
28
)
<=
'X'
;
rddata_reg
(
29
)
<=
'X'
;
rddata_reg
(
30
)
<=
'X'
;
rddata_reg
(
31
)
<=
'X'
;
ack_sreg
(
0
)
<=
'1'
;
ack_sreg
(
2
)
<=
'1'
;
ack_in_progress
<=
'1'
;
when
"0001"
=>
if
(
wb_we_i
=
'1'
)
then
...
...
@@ -221,44 +223,6 @@ begin
rddata_reg
(
31
)
<=
'X'
;
ack_sreg
(
0
)
<=
'1'
;
ack_in_progress
<=
'1'
;
when
"0010"
=>
if
(
wb_we_i
=
'1'
)
then
regs_o
.
reset_wr_o
<=
'1'
;
end
if
;
rddata_reg
(
0
)
<=
'X'
;
rddata_reg
(
1
)
<=
'X'
;
rddata_reg
(
2
)
<=
'X'
;
rddata_reg
(
3
)
<=
'X'
;
rddata_reg
(
4
)
<=
'X'
;
rddata_reg
(
5
)
<=
'X'
;
rddata_reg
(
6
)
<=
'X'
;
rddata_reg
(
7
)
<=
'X'
;
rddata_reg
(
8
)
<=
'X'
;
rddata_reg
(
9
)
<=
'X'
;
rddata_reg
(
10
)
<=
'X'
;
rddata_reg
(
11
)
<=
'X'
;
rddata_reg
(
12
)
<=
'X'
;
rddata_reg
(
13
)
<=
'X'
;
rddata_reg
(
14
)
<=
'X'
;
rddata_reg
(
15
)
<=
'X'
;
rddata_reg
(
16
)
<=
'X'
;
rddata_reg
(
17
)
<=
'X'
;
rddata_reg
(
18
)
<=
'X'
;
rddata_reg
(
19
)
<=
'X'
;
rddata_reg
(
20
)
<=
'X'
;
rddata_reg
(
21
)
<=
'X'
;
rddata_reg
(
22
)
<=
'X'
;
rddata_reg
(
23
)
<=
'X'
;
rddata_reg
(
24
)
<=
'X'
;
rddata_reg
(
25
)
<=
'X'
;
rddata_reg
(
26
)
<=
'X'
;
rddata_reg
(
27
)
<=
'X'
;
rddata_reg
(
28
)
<=
'X'
;
rddata_reg
(
29
)
<=
'X'
;
rddata_reg
(
30
)
<=
'X'
;
rddata_reg
(
31
)
<=
'X'
;
ack_sreg
(
0
)
<=
'1'
;
ack_in_progress
<=
'1'
;
when
"1000"
=>
if
(
wb_we_i
=
'1'
)
then
eic_idr_write_int
<=
'1'
;
...
...
@@ -474,6 +438,19 @@ begin
regs_o
.
cr_rx_en_o
<=
nic_cr_rx_en_int
;
-- Transmit enable
regs_o
.
cr_tx_en_o
<=
nic_cr_tx_en_int
;
-- Software Reset
process
(
clk_sys_i
,
rst_n_i
)
begin
if
(
rst_n_i
=
'0'
)
then
nic_cr_sw_rst_dly0
<=
'0'
;
regs_o
.
cr_sw_rst_o
<=
'0'
;
elsif
rising_edge
(
clk_sys_i
)
then
nic_cr_sw_rst_dly0
<=
nic_cr_sw_rst_int
;
regs_o
.
cr_sw_rst_o
<=
nic_cr_sw_rst_int
and
(
not
nic_cr_sw_rst_dly0
);
end
if
;
end
process
;
-- Buffer Not Available
-- Frame Received
regs_o
.
sr_rec_o
<=
wrdata_reg
(
1
);
...
...
@@ -483,9 +460,6 @@ begin
regs_o
.
sr_tx_error_o
<=
wrdata_reg
(
3
);
-- Current TX descriptor
-- Current RX descriptor
-- Software reset
-- pass-through field: Software reset in register: SW_Reset
regs_o
.
reset_o
<=
wrdata_reg
(
31
downto
0
);
-- extra code for reg/fifo/mem: TX descriptors mem
-- RAM block instantiation for memory: TX descriptors mem
nic_dtx_raminst
:
wbgen2_dpssram
...
...
modules/wrsw_nic/wr_nic.wb
View file @
1cb9d610
...
...
@@ -36,9 +36,6 @@ top = peripheral {
* With EMPTY set to 0, the frame can now be copied from the NIC's memory and stats can be updated \
* Set READY bit to 1 \
\
Todo \
~~~~ \
* Descriptors in RAM, not as registers. wbgen2 doesn't support this yet. Working on it. \
Known issues \
~~~~~~~~~~~ \
* Only 32-bit aligned addresses are supported";
...
...
@@ -66,6 +63,16 @@ top = peripheral {
access_bus = READ_WRITE;
access_dev = READ_ONLY;
};
field {
name = "Software Reset";
description = "write 1: reset the NIC, zero all registers and reset the state of the module \
write 0: no effect";
prefix = "sw_rst";
size = 1;
align = 31;
type = MONOSTABLE;
};
};
reg {
...
...
@@ -145,18 +152,6 @@ top = peripheral {
};
};
reg {
name = "SW_Reset";
description = "Writing to this register resets the NIC, zeroing all registers and resetting the state of the module";
prefix = "reset";
field {
name = "Software reset";
type = PASS_THROUGH;
size = 32;
};
};
irq {
name = "Receive Complete";
prefix = "rcomp";
...
...
modules/wrsw_nic/wrsw_nic.vhd
View file @
1cb9d610
...
...
@@ -11,8 +11,8 @@ entity wrsw_nic is
(
g_interface_mode
:
t_wishbone_interface_mode
:
=
CLASSIC
;
g_address_granularity
:
t_wishbone_address_granularity
:
=
WORD
;
g_src_cyc_on_stall
:
boolean
:
=
false
);
g_src_cyc_on_stall
:
boolean
:
=
false
;
g_port_mask_bits
:
integer
:
=
32
);
--should be num_ports+1
port
(
clk_sys_i
:
in
std_logic
;
rst_n_i
:
in
std_logic
;
...
...
@@ -47,7 +47,7 @@ entity wrsw_nic is
-- "Fake" RTU interface
-------------------------------------------------------------------------------
rtu_dst_port_mask_o
:
out
std_logic_vector
(
3
1
downto
0
);
rtu_dst_port_mask_o
:
out
std_logic_vector
(
g_port_mask_bits
-
1
downto
0
);
rtu_prio_o
:
out
std_logic_vector
(
2
downto
0
);
rtu_drop_o
:
out
std_logic
;
rtu_rsp_valid_o
:
out
std_logic
;
...
...
@@ -66,7 +66,7 @@ entity wrsw_nic is
wb_dat_o
:
out
std_logic_vector
(
c_wishbone_data_width
-1
downto
0
);
wb_ack_o
:
out
std_logic
;
wb_stall_o
:
out
std_logic
;
wb_i
rq
_o
:
out
std_logic
wb_i
nt
_o
:
out
std_logic
);
...
...
@@ -78,7 +78,8 @@ architecture rtl of wrsw_nic is
generic
(
g_interface_mode
:
t_wishbone_interface_mode
;
g_address_granularity
:
t_wishbone_address_granularity
;
g_src_cyc_on_stall
:
boolean
);
g_src_cyc_on_stall
:
boolean
:
=
false
;
g_port_mask_bits
:
integer
:
=
32
);
port
(
clk_sys_i
:
in
std_logic
;
rst_n_i
:
in
std_logic
;
...
...
@@ -86,7 +87,7 @@ architecture rtl of wrsw_nic is
snk_o
:
out
t_wrf_sink_out
;
src_i
:
in
t_wrf_source_in
;
src_o
:
out
t_wrf_source_out
;
rtu_dst_port_mask_o
:
out
std_logic_vector
(
3
1
downto
0
);
rtu_dst_port_mask_o
:
out
std_logic_vector
(
g_port_mask_bits
-
1
downto
0
);
rtu_prio_o
:
out
std_logic_vector
(
2
downto
0
);
rtu_drop_o
:
out
std_logic
;
rtu_rsp_valid_o
:
out
std_logic
;
...
...
@@ -111,7 +112,8 @@ begin
generic
map
(
g_interface_mode
=>
g_interface_mode
,
g_address_granularity
=>
g_address_granularity
,
g_src_cyc_on_stall
=>
g_src_cyc_on_stall
)
g_src_cyc_on_stall
=>
g_src_cyc_on_stall
,
g_port_mask_bits
=>
g_port_mask_bits
)
port
map
(
clk_sys_i
=>
clk_sys_i
,
rst_n_i
=>
rst_n_i
,
...
...
@@ -158,6 +160,6 @@ begin
wb_dat_o
<=
wb_out
.
dat
;
wb_ack_o
<=
wb_out
.
ack
;
wb_stall_o
<=
wb_out
.
stall
;
wb_i
rq
_o
<=
wb_out
.
int
;
wb_i
nt
_o
<=
wb_out
.
int
;
end
rtl
;
modules/wrsw_nic/xwrsw_nic.vhd
View file @
1cb9d610
...
...
@@ -17,8 +17,8 @@ entity xwrsw_nic is
(
g_interface_mode
:
t_wishbone_interface_mode
:
=
CLASSIC
;
g_address_granularity
:
t_wishbone_address_granularity
:
=
WORD
;
g_src_cyc_on_stall
:
boolean
:
=
false
);
g_src_cyc_on_stall
:
boolean
:
=
false
;
g_port_mask_bits
:
integer
:
=
32
);
--should be num_ports+1
port
(
clk_sys_i
:
in
std_logic
;
rst_n_i
:
in
std_logic
;
...
...
@@ -37,7 +37,7 @@ entity xwrsw_nic is
-- "Fake" RTU interface
-------------------------------------------------------------------------------
rtu_dst_port_mask_o
:
out
std_logic_vector
(
3
1
downto
0
);
rtu_dst_port_mask_o
:
out
std_logic_vector
(
g_port_mask_bits
-
1
downto
0
);
rtu_prio_o
:
out
std_logic_vector
(
2
downto
0
);
rtu_drop_o
:
out
std_logic
;
rtu_rsp_valid_o
:
out
std_logic
;
...
...
@@ -59,7 +59,8 @@ architecture rtl of xwrsw_nic is
generic
(
g_desc_mode
:
string
;
g_num_descriptors
:
integer
;
g_num_descriptors_log2
:
integer
);
g_num_descriptors_log2
:
integer
;
g_port_mask_bits
:
integer
:
=
32
);
port
(
clk_sys_i
:
in
std_logic
;
rst_n_i
:
in
std_logic
;
...
...
@@ -162,14 +163,15 @@ architecture rtl of xwrsw_nic is
end
component
;
component
nic_tx_fsm
generic
(
g_cyc_on_stall
:
boolean
);
generic
(
g_port_mask_bits
:
integer
:
=
32
;
g_cyc_on_stall
:
boolean
:
=
false
);
port
(
clk_sys_i
:
in
std_logic
;
rst_n_i
:
in
std_logic
;
src_o
:
out
t_wrf_source_out
;
src_i
:
in
t_wrf_source_in
;
rtu_dst_port_mask_o
:
out
std_logic_vector
(
3
1
downto
0
);
rtu_dst_port_mask_o
:
out
std_logic_vector
(
g_port_mask_bits
-
1
downto
0
);
rtu_prio_o
:
out
std_logic_vector
(
2
downto
0
);
rtu_drop_o
:
out
std_logic
;
rtu_rsp_valid_o
:
out
std_logic
;
...
...
@@ -287,7 +289,7 @@ begin -- rtl
wb_out
.
err
<=
'0'
;
wb_out
.
rty
<=
'0'
;
nic_reset_n
<=
rst_n_i
and
(
not
regs_fromwb
.
reset_wr
_o
);
nic_reset_n
<=
rst_n_i
and
(
not
regs_fromwb
.
cr_sw_rst
_o
);
regs_towb
<=
regs_towb_tx
or
regs_towb_rx
or
regs_towb_main
;
...
...
@@ -303,7 +305,7 @@ begin -- rtl
wb_stb_i
=>
wb_in
.
stb
,
wb_we_i
=>
wb_in
.
we
,
wb_ack_o
=>
wb_ack_slave
,
wb_stall_o
=>
wb_out
.
stall
,
wb_stall_o
=>
wb_out
.
stall
,
wb_int_o
=>
wb_out
.
int
,
...
...
@@ -399,8 +401,8 @@ begin -- rtl
generic
map
(
g_desc_mode
=>
"rx"
,
g_num_descriptors
=>
c_nic_num_rx_descriptors
,
g_num_descriptors_log2
=>
c_nic_num_rx_descriptors_log2
)
g_num_descriptors_log2
=>
c_nic_num_rx_descriptors_log2
,
g_port_mask_bits
=>
g_port_mask_bits
)
port
map
(
clk_sys_i
=>
clk_sys_i
,
rst_n_i
=>
nic_reset_n
,
...
...
@@ -465,7 +467,8 @@ begin -- rtl
generic
map
(
g_desc_mode
=>
"tx"
,
g_num_descriptors
=>
c_nic_num_tx_descriptors
,
g_num_descriptors_log2
=>
c_nic_num_tx_descriptors_log2
)
g_num_descriptors_log2
=>
c_nic_num_tx_descriptors_log2
,
g_port_mask_bits
=>
g_port_mask_bits
)
port
map
(
clk_sys_i
=>
clk_sys_i
,
rst_n_i
=>
nic_reset_n
,
...
...
@@ -494,7 +497,8 @@ begin -- rtl
U_TX_FSM
:
nic_tx_fsm
generic
map
(
g_cyc_on_stall
=>
g_src_cyc_on_stall
)
g_cyc_on_stall
=>
g_src_cyc_on_stall
,
g_port_mask_bits
=>
g_port_mask_bits
)
port
map
(
clk_sys_i
=>
clk_sys_i
,
rst_n_i
=>
nic_reset_n
,
...
...
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