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White Rabbit core collection
Commits
07eda292
Commit
07eda292
authored
Jul 10, 2019
by
Grzegorz Daniluk
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Plain Diff
low phase drift: cleanup GTX
parent
5dd8a5a0
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2 changed files
with
15 additions
and
30 deletions
+15
-30
wr_gtx_phy_virtex6_lp.vhd
...gtp_phy/virtex6-low-phase-drift/wr_gtx_phy_virtex6_lp.vhd
+12
-27
wr_gtx_phy_virtex6.vhd
platform/xilinx/wr_gtp_phy/virtex6/wr_gtx_phy_virtex6.vhd
+3
-3
No files found.
platform/xilinx/wr_gtp_phy/virtex6-low-phase-drift/wr_gtx_phy_virtex6_lp.vhd
View file @
07eda292
...
@@ -57,8 +57,8 @@ entity wr_gtx_phy_virtex6_lp is
...
@@ -57,8 +57,8 @@ entity wr_gtx_phy_virtex6_lp is
-- set to non-zero value to speed up the simulation by reducing some delays
-- set to non-zero value to speed up the simulation by reducing some delays
g_simulation
:
integer
:
=
0
;
g_simulation
:
integer
:
=
0
;
g_use_slave_tx_clock
:
integer
:
=
0
;
g_use_slave_tx_clock
:
integer
:
=
0
;
g_
use_bufr_for_rx_clock
:
boolean
:
=
false
;
g_
rxclk_bufr
:
boolean
:
=
false
;
g_
use_bufr_for_tx_clock
:
boolean
:
=
false
;
g_
txclk_bufr
:
boolean
:
=
false
;
g_id
:
integer
:
=
0
g_id
:
integer
:
=
0
);
);
...
@@ -93,7 +93,7 @@ entity wr_gtx_phy_virtex6_lp is
...
@@ -93,7 +93,7 @@ entity wr_gtx_phy_virtex6_lp is
-- RX recovered clock
-- RX recovered clock
rx_rbclk_o
:
out
std_logic
;
rx_rbclk_o
:
out
std_logic
;
rx_rb
clk_sampled_o
:
out
std_logic
;
clk_sampled_o
:
out
std_logic
;
-- 8b10b-decoded data output. The data output must be kept invalid before
-- 8b10b-decoded data output. The data output must be kept invalid before
-- the transceiver is locked on the incoming signal to prevent the EP from
-- the transceiver is locked on the incoming signal to prevent the EP from
...
@@ -320,27 +320,20 @@ architecture rtl of wr_gtx_phy_virtex6_lp is
...
@@ -320,27 +320,20 @@ architecture rtl of wr_gtx_phy_virtex6_lp is
synced_o
=>
gtx_rx_rst_a
synced_o
=>
gtx_rx_rst_a
);
);
gen_bufr_for_tx_clock
:
if
g_
use_bufr_for_tx_clock
generate
gen_bufr_for_tx_clock
:
if
g_
txclk_bufr
generate
BUFR_
1
:
BUFR
BUFR_
TX
:
BUFR
port
map
(
port
map
(
O
=>
tx_out_clk
,
O
=>
tx_out_clk
,
I
=>
tx_out_clk_buf
);
I
=>
tx_out_clk_buf
);
end
generate
gen_bufr_for_tx_clock
;
end
generate
gen_bufr_for_tx_clock
;
gen_bufg_for_tx_clock
:
if
not
g_
use_bufr_for_tx_clock
and
g_id
<
12
generate
gen_bufg_for_tx_clock
:
if
not
g_
txclk_bufr
generate
BUFG_
1
:
BUFG
BUFG_
TX
:
BUFG
port
map
(
port
map
(
O
=>
tx_out_clk
,
O
=>
tx_out_clk
,
I
=>
tx_out_clk_buf
);
I
=>
tx_out_clk_buf
);
end
generate
gen_bufg_for_tx_clock
;
end
generate
gen_bufg_for_tx_clock
;
gen_no_tx_clock
:
if
g_id
>
11
generate
tx_out_clk
<=
'0'
;
end
generate
;
U_Sampler_RX
:
dmtd_sampler
U_Sampler_RX
:
dmtd_sampler
generic
map
(
generic
map
(
g_divide_input_by_2
=>
false
,
g_divide_input_by_2
=>
false
,
...
@@ -359,17 +352,9 @@ architecture rtl of wr_gtx_phy_virtex6_lp is
...
@@ -359,17 +352,9 @@ architecture rtl of wr_gtx_phy_virtex6_lp is
clk_dmtd_i
=>
clk_dmtd_i
,
clk_dmtd_i
=>
clk_dmtd_i
,
clk_sampled_o
=>
tx_out_clk_sampled
);
clk_sampled_o
=>
tx_out_clk_sampled
);
process
(
rx_rec_clk_sampled
,
tx_out_clk_sampled
,
debug_i
)
clk_sampled_o
<=
rx_rec_clk_sampled
when
debug_i
(
15
downto
14
)
=
"00"
else
begin
tx_out_clk_sampled
when
debug_i
(
15
downto
14
)
=
"01"
else
case
debug_i
(
15
downto
14
)
is
'0'
;
when
"00"
=>
rx_rbclk_sampled_o
<=
rx_rec_clk_sampled
;
when
"01"
=>
rx_rbclk_sampled_o
<=
tx_out_clk_sampled
;
when
others
=>
rx_rbclk_sampled_o
<=
'0'
;
end
case
;
end
process
;
tx_enc_err_o
<=
'0'
;
tx_enc_err_o
<=
'0'
;
...
@@ -411,7 +396,7 @@ architecture rtl of wr_gtx_phy_virtex6_lp is
...
@@ -411,7 +396,7 @@ architecture rtl of wr_gtx_phy_virtex6_lp is
debug_o
(
0
)
<=
tx_reset_done
;
debug_o
(
0
)
<=
tx_reset_done
;
gen_rx_bufg
:
if
(
g_
use_bufr_for_rx_clock
=
false
)
generate
gen_rx_bufg
:
if
(
g_
rxclk_bufr
=
false
)
generate
U_BUF_RxRecClk
:
BUFG
U_BUF_RxRecClk
:
BUFG
port
map
(
port
map
(
...
@@ -420,7 +405,7 @@ architecture rtl of wr_gtx_phy_virtex6_lp is
...
@@ -420,7 +405,7 @@ architecture rtl of wr_gtx_phy_virtex6_lp is
end
generate
gen_rx_bufg
;
end
generate
gen_rx_bufg
;
gen_rx_bufr
:
if
(
g_
use_bufr_for_rx_clock
=
true
)
generate
gen_rx_bufr
:
if
(
g_
rxclk_bufr
=
true
)
generate
U_BUF_RxRecClk
:
BUFR
U_BUF_RxRecClk
:
BUFR
port
map
(
port
map
(
I
=>
rx_rec_clk_bufin
,
I
=>
rx_rec_clk_bufin
,
...
...
platform/xilinx/wr_gtp_phy/virtex6/wr_gtx_phy_virtex6.vhd
View file @
07eda292
...
@@ -57,7 +57,7 @@ entity wr_gtx_phy_virtex6 is
...
@@ -57,7 +57,7 @@ entity wr_gtx_phy_virtex6 is
-- set to non-zero value to speed up the simulation by reducing some delays
-- set to non-zero value to speed up the simulation by reducing some delays
g_simulation
:
integer
:
=
0
;
g_simulation
:
integer
:
=
0
;
g_use_slave_tx_clock
:
integer
:
=
0
;
g_use_slave_tx_clock
:
integer
:
=
0
;
g_
use
_bufr
:
boolean
:
=
false
g_
rxclk
_bufr
:
boolean
:
=
false
);
);
port
(
port
(
...
@@ -303,7 +303,7 @@ begin -- rtl
...
@@ -303,7 +303,7 @@ begin -- rtl
txpll_lockdet_i
=>
txpll_lockdet
,
txpll_lockdet_i
=>
txpll_lockdet
,
gtx_test_o
=>
gtx_test
);
gtx_test_o
=>
gtx_test
);
gen_rx_bufg
:
if
(
g_
use
_bufr
=
false
)
generate
gen_rx_bufg
:
if
(
g_
rxclk
_bufr
=
false
)
generate
U_BUF_RxRecClk
:
BUFG
U_BUF_RxRecClk
:
BUFG
port
map
(
port
map
(
...
@@ -312,7 +312,7 @@ begin -- rtl
...
@@ -312,7 +312,7 @@ begin -- rtl
end
generate
gen_rx_bufg
;
end
generate
gen_rx_bufg
;
gen_rx_bufr
:
if
(
g_
use
_bufr
=
true
)
generate
gen_rx_bufr
:
if
(
g_
rxclk
_bufr
=
true
)
generate
U_BUF_RxRecClk
:
BUFR
U_BUF_RxRecClk
:
BUFR
port
map
(
port
map
(
I
=>
rx_rec_clk_bufin
,
I
=>
rx_rec_clk_bufin
,
...
...
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