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White Rabbit core collection
Commit 06d5a438 authored by Andela Kostic's avatar Andela Kostic
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Ensure functionality of wrc_core testbench for wrpc-v5 

In wrpc-v5, LM32 is replaced by RISC-V. Hence, the new compiled WRPC software
for the simulation is added (wrc.bram file).
Also, the size of the RAM used by the WRPC software is increased.
The testbench sets hdl_testbench structure used for communication with the software.
The simulation works with ModelSim.
parent cf7ae807
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    bin/wrpc/wrc.bram 0 → 100644
    View file @ 06d5a438
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    modules/wrc_core/wrc_urv_wrapper.vhd
    View file @ 06d5a438
    ......@@ -127,7 +127,7 @@ begin
    dwb_o <= dwb_out;
    U_cpu_core : urv_cpu
    U_cpu_core : entity work.urv_cpu
    generic map (
    g_with_hw_debug => 1,
    g_with_hw_mulh => 1,
    ......
    testbench/wrc_core/Manifest.py
    View file @ 06d5a438
    ......@@ -3,12 +3,14 @@ target = "xilinx"
    syn_device = "xc6slx45t"
    syn_grade = "-3"
    syn_package = "fgg484"
    #sim_tool = "modelsim"
    sim_tool = "riviera"
    sim_tool = "modelsim"
    #sim_tool = "riviera"
    top_module = "main"
    fetchto = "../../ip_cores"
    vlog_opt = "+incdir+../../sim"
    vcom_opt="-mixedsvvh"
    files = [ "main.sv" ]
    include_dirs = [ "../../sim",
    ......
    testbench/wrc_core/functions.svh
    View file @ 06d5a438
    ......@@ -48,14 +48,14 @@ semaphore txPkt = new(1);
    */
    task send_frames(WBPacketSource src, int n_packets, int ifg = 0 /*[us]*/);
    // TODO: improve the IFG: allow to make it tighter
    int i, seed = 0,n1=0,n2=0;
    automatic int i, seed = 0,n1=0,n2=0;
    int cur_size, dir;
    EthPacket pkt, tmpl;
    EthPacket to_ext[$], to_minic[$];
    EthPacketGenerator gen = new;
    automatic EthPacketGenerator gen = new;
    int random_ifg; //us
    int min_ifg = 1; //us
    int max_ifg = 100;//us
    automatic int min_ifg = 1; //us
    automatic int max_ifg = 100;//us
    tmpl = new;
    tmpl.src = '{'h22,'h33,'h44,'h44,'h55,'h66};
    ......
    testbench/wrc_core/main.sv
    View file @ 06d5a438
    ......@@ -88,6 +88,15 @@
    `define BASE_SYSCON 'h20400
    `define BASE_MINIC 'h20000
    `define BASE_WRC_CPU_REGS 'hb00
    `define WRC_CPU_RESET 'h00
    `define WRC_CPU_UADDR 'h4
    `define WRC_CPU_UDATA 'h8
    /* the simulation sends frame_number frames with forced Inter-frame gap of 1 us
    and frame_number frames with random Inter-frame gap, between 1 and 100us */
    int frame_number = 100;
    module main;
    wire clk_ref;
    ......@@ -164,8 +173,8 @@ module main;
    .g_address_granularity (BYTE),
    .g_tx_runt_padding (1),
    .g_with_external_clock_input(1),
    .g_dpram_initf ("../../bin/wrpc/wrc_phy8_sim.bram"),
    .g_dpram_size (131072/4),
    .g_dpram_initf ("../../bin/wrpc/wrc.bram"),
    .g_dpram_size (196608/4),
    .g_diag_id (1),
    .g_diag_ver (2),
    .g_diag_ro_size (5),
    ......@@ -353,7 +362,6 @@ module main;
    CSimDrv_WR_Endpoint ep_drv;
    uint64_t val;
    int frame_number = 10000;
    @(posedge rst_n);
    repeat(3) @(posedge clk_sys);
    ......@@ -381,6 +389,21 @@ module main;
    #1us;
    acc_wrc.write(`BASE_SYSCON + `ADDR_SYSC_RSTR, 'hdeadbee );
    // set hdl_testbench structure used for communication with risc-v software
    acc_wrc.write(`BASE_WRC_CPU_REGS + `WRC_CPU_RESET, 1);
    // magic - addr = 0x4000 (in bytes), data = 0x4d433ebc
    acc_wrc.write(`BASE_WRC_CPU_REGS + `WRC_CPU_UADDR, 'h1000);
    acc_wrc.write(`BASE_WRC_CPU_REGS + `WRC_CPU_UDATA, 'hbc3e434d);
    // version - addr = 0x4004 (in bytes), data = 1
    acc_wrc.write(`BASE_WRC_CPU_REGS + `WRC_CPU_UADDR, 'h1001);
    acc_wrc.write(`BASE_WRC_CPU_REGS + `WRC_CPU_UDATA, 'h01000000);
    // test_num - addr = 0x4008 (in bytes), data = 1
    acc_wrc.write(`BASE_WRC_CPU_REGS + `WRC_CPU_UADDR, 'h1002);
    acc_wrc.write(`BASE_WRC_CPU_REGS + `WRC_CPU_UDATA, 'h01000000);
    // flag - addr = 0x400C (in bytes), data = 0x12345678
    acc_wrc.write(`BASE_WRC_CPU_REGS + `WRC_CPU_UADDR, 'h1003);
    acc_wrc.write(`BASE_WRC_CPU_REGS + `WRC_CPU_UDATA, 'h78563412);
    acc_wrc.write(`BASE_WRC_CPU_REGS + `WRC_CPU_RESET, 0);
    $display("");$display("");$display("");$display("");
    $display("====================================================");
    ......@@ -404,27 +427,27 @@ module main;
    tx_sth = 0; //after having received all the frames, indicate that no frames
    //are being transmitted, i.e. betweeen tx and rx
    #100us;
    $finish; //finish
    //$stop; //finish
    end
    initial begin /// receive frames from WRPC (looped back or sent by LM32), loopback frames
    /// sent from LM32
    EthPacket pkt;
    mac_addr_t PTP_MAC='{'h01,'h1b,'h19,'h00,'h00,'h00};
    mac_addr_t SELF_MAC='{'h22,'h33,'h44,'h44,'h55,'h66};
    automatic mac_addr_t PTP_MAC='{'h01,'h1b,'h19,'h00,'h00,'h00};
    automatic mac_addr_t SELF_MAC='{'h22,'h33,'h44,'h44,'h55,'h66};
    string codes [integer];
    int i = 0, correct = 0, j;
    int drop_first = 1;
    automatic int i = 0, correct = 0, j;
    automatic int drop_first = 1;
    int size_pos;
    CSimDrv_Minic minic;
    EthPacket rxp;
    int prev_size=0;
    automatic int prev_size=0;
    uint64_t val64;
    uint32_t seqID=0;
    int cnt = 0, stat = 0, ret = 0;
    int total_cnt=0;
    int self_seqID_reg=0, self_seqID_rx=0; //registered/expected and received seqID from simulation
    int lm32_seqID_reg=0, lm32_seqID_rx=0; //registered/expected and received seqID from LM32
    automatic uint32_t seqID=0;
    automatic int cnt = 0, stat = 0, ret = 0;
    automatic int total_cnt=0;
    automatic int self_seqID_reg=0, self_seqID_rx=0; //registered/expected and received seqID from simulation
    automatic int lm32_seqID_reg=0, lm32_seqID_rx=0; //registered/expected and received seqID from LM32
    codes['hAA]="Frame OK - first";
    codes['hBB]="Frame OK";
    ......@@ -485,6 +508,9 @@ module main;
    if(self_seqID_reg != self_seqID_rx)
    $warning("simulation-generated ERROR: wrong seqID");
    self_seqID_reg = self_seqID_rx +1;
    // reset self_seqID_reg when send_frames is called again
    if (self_seqID_reg == frame_number)
    self_seqID_reg = 0;
    end
    /// ///////////////////////////////////////////////////////////////////////////////////
    /// received something else, probably corrupted frame
    ......@@ -515,7 +541,7 @@ module main;
    #0.5us;
    if (wait_cnt > 2000) begin // this is too much waiting, error
    $warning("ERROR: RX TIMEOUT, no frame was received within expected timeout");
    $finish;
    $stop;
    end
    else if(rx_sth==0 & tx_sth == 1) // if transmission ongoing and nothing received, count
    wait_cnt++;
    ......
    testbench/wrc_core/wave.do
    View file @ 06d5a438
    ......@@ -26,14 +26,14 @@ add wave -noupdate -group EP_PCS /main/DUT/U_Endpoint/U_Wrapped_Endpoint/U_PCS_1
    add wave -noupdate -group EP_PCS /main/DUT/U_Endpoint/U_Wrapped_Endpoint/U_PCS_1000BASEX/gen_8bit/U_TX_PCS/phy_tx_k_o
    add wave -noupdate -group EP_PCS /main/DUT/U_Endpoint/U_Wrapped_Endpoint/U_PCS_1000BASEX/gen_8bit/U_TX_PCS/phy_tx_disparity_i
    add wave -noupdate -group EP_PCS /main/DUT/U_Endpoint/U_Wrapped_Endpoint/U_PCS_1000BASEX/gen_8bit/U_TX_PCS/phy_tx_enc_err_i
    add wave -noupdate -group EP_PCS -height 16 /main/DUT/U_Endpoint/U_Wrapped_Endpoint/U_PCS_1000BASEX/gen_8bit/U_TX_PCS/tx_state
    add wave -noupdate -group EP_PCS /main/DUT/U_Endpoint/U_Wrapped_Endpoint/U_PCS_1000BASEX/gen_8bit/U_TX_PCS/tx_state
    add wave -noupdate -group EP_PCS /main/DUT/U_Endpoint/U_Wrapped_Endpoint/U_PCS_1000BASEX/gen_8bit/U_TX_PCS/pcs_fab_i
    add wave -noupdate -group EP_PCS /main/DUT/U_Endpoint/U_Wrapped_Endpoint/U_PCS_1000BASEX/gen_8bit/U_TX_PCS/pcs_busy_o
    add wave -noupdate -expand -group Minic /main/DUT/MINI_NIC/src_i
    add wave -noupdate -expand -group Minic /main/DUT/MINI_NIC/src_o
    add wave -noupdate -expand -group Minic /main/DUT/MINI_NIC/wb_i
    add wave -noupdate -expand -group Minic /main/DUT/MINI_NIC/wb_o
    add wave -noupdate -expand -group Minic -height 16 /main/DUT/MINI_NIC/U_Wrapped_Minic/ntx_state
    add wave -noupdate -expand -group Minic /main/DUT/MINI_NIC/U_Wrapped_Minic/ntx_state
    add wave -noupdate -expand -group Minic /main/DUT/MINI_NIC/U_Wrapped_Minic/tx_fifo_d
    add wave -noupdate -expand -group Minic /main/DUT/MINI_NIC/U_Wrapped_Minic/tx_fifo_empty
    add wave -noupdate -expand -group Minic /main/DUT/MINI_NIC/U_Wrapped_Minic/tx_fifo_full
    ......@@ -97,7 +97,7 @@ add wave -noupdate -group DUT->EP-TxPCS /main/DUT/U_Endpoint/U_Wrapped_Endpoint/
    add wave -noupdate -group DUT->EP-TxPCS /main/DUT/U_Endpoint/U_Wrapped_Endpoint/U_PCS_1000BASEX/gen_8bit/U_TX_PCS/fifo_fab
    add wave -noupdate -group DUT->EP-TxPCS /main/DUT/U_Endpoint/U_Wrapped_Endpoint/U_PCS_1000BASEX/gen_8bit/U_TX_PCS/fifo_packed_in
    add wave -noupdate -group DUT->EP-TxPCS /main/DUT/U_Endpoint/U_Wrapped_Endpoint/U_PCS_1000BASEX/gen_8bit/U_TX_PCS/fifo_packed_out
    add wave -noupdate -group DUT->EP-TxPCS -height 16 /main/DUT/U_Endpoint/U_Wrapped_Endpoint/U_PCS_1000BASEX/gen_8bit/U_TX_PCS/tx_state
    add wave -noupdate -group DUT->EP-TxPCS /main/DUT/U_Endpoint/U_Wrapped_Endpoint/U_PCS_1000BASEX/gen_8bit/U_TX_PCS/tx_state
    add wave -noupdate -group DUT->EP-TxPCS /main/DUT/U_Endpoint/U_Wrapped_Endpoint/U_PCS_1000BASEX/gen_8bit/U_TX_PCS/fifo_rd
    add wave -noupdate -group DUT->EP-TxPCS /main/DUT/U_Endpoint/U_Wrapped_Endpoint/U_PCS_1000BASEX/gen_8bit/U_TX_PCS/fifo_ready
    add wave -noupdate -group DUT->EP-TxPCS /main/DUT/U_Endpoint/U_Wrapped_Endpoint/U_PCS_1000BASEX/gen_8bit/U_TX_PCS/fifo_wr
    ......@@ -124,10 +124,10 @@ add wave -noupdate -group DUT->EP-TxPCS /main/DUT/U_Endpoint/U_Wrapped_Endpoint/
    add wave -noupdate -group DUT->EP-TxPCS /main/DUT/U_Endpoint/U_Wrapped_Endpoint/U_PCS_1000BASEX/gen_8bit/U_TX_PCS/tx_is_k
    add wave -noupdate -group DUT->EP-TxPCS /main/DUT/U_Endpoint/U_Wrapped_Endpoint/U_PCS_1000BASEX/gen_8bit/U_TX_PCS/tx_odata_reg
    add wave -noupdate -group DUT->EP-TxPCS /main/DUT/U_Endpoint/U_Wrapped_Endpoint/U_PCS_1000BASEX/gen_8bit/U_TX_PCS/tx_odd_length
    add wave -noupdate -group DUT->EP-TxPCS -height 16 /main/DUT/U_Endpoint/U_Wrapped_Endpoint/U_PCS_1000BASEX/gen_8bit/U_TX_PCS/tx_state
    add wave -noupdate -group DUT->EP-TxPCS /main/DUT/U_Endpoint/U_Wrapped_Endpoint/U_PCS_1000BASEX/gen_8bit/U_TX_PCS/tx_state
    add wave -noupdate -group DUT->EP-TxPCS /main/DUT/U_Endpoint/U_Wrapped_Endpoint/U_PCS_1000BASEX/gen_8bit/U_TX_PCS/tx_rdreq_toggle
    add wave -noupdate -group EP->txPCS /main/EP/U_PCS_1000BASEX/gen_8bit/U_TX_PCS/an_tx_en_i
    add wave -noupdate -group EP->txPCS -height 16 /main/EP/U_PCS_1000BASEX/gen_8bit/U_TX_PCS/tx_state
    add wave -noupdate -group EP->txPCS /main/EP/U_PCS_1000BASEX/gen_8bit/U_TX_PCS/tx_state
    add wave -noupdate -group EP->txPCS /main/EP/U_PCS_1000BASEX/gen_8bit/U_TX_PCS/an_tx_en_synced
    add wave -noupdate -group EP->txPCS /main/EP/U_PCS_1000BASEX/gen_8bit/U_TX_PCS/an_tx_val_i
    add wave -noupdate -group EP->txPCS /main/EP/U_PCS_1000BASEX/gen_8bit/U_TX_PCS/clk_sys_i
    ......@@ -166,33 +166,171 @@ add wave -noupdate -group EP->txPCS /main/EP/U_PCS_1000BASEX/gen_8bit/U_TX_PCS/t
    add wave -noupdate -group EP->txPCS /main/EP/U_PCS_1000BASEX/gen_8bit/U_TX_PCS/tx_odata_reg
    add wave -noupdate -group EP->txPCS /main/EP/U_PCS_1000BASEX/gen_8bit/U_TX_PCS/tx_odd_length
    add wave -noupdate -group EP->txPCS /main/EP/U_PCS_1000BASEX/gen_8bit/U_TX_PCS/tx_rdreq_toggle
    add wave -noupdate -expand -group DUT->MUX /main/DUT/U_WBP_Mux/clk_sys_i
    add wave -noupdate -expand -group DUT->MUX -height 16 /main/DUT/U_WBP_Mux/demux
    add wave -noupdate -expand -group DUT->MUX /main/DUT/U_WBP_Mux/dmux_others
    add wave -noupdate -expand -group DUT->MUX /main/DUT/U_WBP_Mux/dmux_sel
    add wave -noupdate -expand -group DUT->MUX /main/DUT/U_WBP_Mux/dmux_sel_zero
    add wave -noupdate -expand -group DUT->MUX /main/DUT/U_WBP_Mux/dmux_select
    add wave -noupdate -expand -group DUT->MUX /main/DUT/U_WBP_Mux/dmux_snd_stat
    add wave -noupdate -expand -group DUT->MUX /main/DUT/U_WBP_Mux/dmux_status_reg
    add wave -noupdate -expand -group DUT->MUX /main/DUT/U_WBP_Mux/ep_snk_i
    add wave -noupdate -expand -group DUT->MUX /main/DUT/U_WBP_Mux/ep_snk_o
    add wave -noupdate -expand -group DUT->MUX /main/DUT/U_WBP_Mux/ep_snk_out_stall
    add wave -noupdate -expand -group DUT->MUX /main/DUT/U_WBP_Mux/ep_src_i
    add wave -noupdate -expand -group DUT->MUX /main/DUT/U_WBP_Mux/ep_src_o
    add wave -noupdate -expand -group DUT->MUX /main/DUT/U_WBP_Mux/ep_stall_mask
    add wave -noupdate -expand -group DUT->MUX /main/DUT/U_WBP_Mux/g_muxed_ports
    add wave -noupdate -expand -group DUT->MUX /main/DUT/U_WBP_Mux/mux
    add wave -noupdate -expand -group DUT->MUX /main/DUT/U_WBP_Mux/mux_class_i
    add wave -noupdate -expand -group DUT->MUX /main/DUT/U_WBP_Mux/mux_cycs
    add wave -noupdate -expand -group DUT->MUX /main/DUT/U_WBP_Mux/mux_rrobin
    add wave -noupdate -expand -group DUT->MUX /main/DUT/U_WBP_Mux/mux_select
    add wave -noupdate -expand -group DUT->MUX /main/DUT/U_WBP_Mux/mux_snk_i
    add wave -noupdate -expand -group DUT->MUX /main/DUT/U_WBP_Mux/mux_snk_o
    add wave -noupdate -expand -group DUT->MUX /main/DUT/U_WBP_Mux/mux_src_i
    add wave -noupdate -expand -group DUT->MUX /main/DUT/U_WBP_Mux/mux_src_o
    add wave -noupdate -expand -group DUT->MUX /main/DUT/U_WBP_Mux/rst_n_i
    add wave -noupdate -group DUT->MUX /main/DUT/U_WBP_Mux/clk_sys_i
    add wave -noupdate -group DUT->MUX /main/DUT/U_WBP_Mux/demux
    add wave -noupdate -group DUT->MUX /main/DUT/U_WBP_Mux/dmux_others
    add wave -noupdate -group DUT->MUX /main/DUT/U_WBP_Mux/dmux_sel
    add wave -noupdate -group DUT->MUX /main/DUT/U_WBP_Mux/dmux_sel_zero
    add wave -noupdate -group DUT->MUX /main/DUT/U_WBP_Mux/dmux_select
    add wave -noupdate -group DUT->MUX /main/DUT/U_WBP_Mux/dmux_snd_stat
    add wave -noupdate -group DUT->MUX /main/DUT/U_WBP_Mux/dmux_status_reg
    add wave -noupdate -group DUT->MUX /main/DUT/U_WBP_Mux/ep_snk_i
    add wave -noupdate -group DUT->MUX /main/DUT/U_WBP_Mux/ep_snk_o
    add wave -noupdate -group DUT->MUX /main/DUT/U_WBP_Mux/ep_snk_out_stall
    add wave -noupdate -group DUT->MUX /main/DUT/U_WBP_Mux/ep_src_i
    add wave -noupdate -group DUT->MUX /main/DUT/U_WBP_Mux/ep_src_o
    add wave -noupdate -group DUT->MUX /main/DUT/U_WBP_Mux/ep_stall_mask
    add wave -noupdate -group DUT->MUX /main/DUT/U_WBP_Mux/g_muxed_ports
    add wave -noupdate -group DUT->MUX /main/DUT/U_WBP_Mux/mux
    add wave -noupdate -group DUT->MUX /main/DUT/U_WBP_Mux/mux_class_i
    add wave -noupdate -group DUT->MUX /main/DUT/U_WBP_Mux/mux_cycs
    add wave -noupdate -group DUT->MUX /main/DUT/U_WBP_Mux/mux_rrobin
    add wave -noupdate -group DUT->MUX /main/DUT/U_WBP_Mux/mux_select
    add wave -noupdate -group DUT->MUX /main/DUT/U_WBP_Mux/mux_snk_i
    add wave -noupdate -group DUT->MUX /main/DUT/U_WBP_Mux/mux_snk_o
    add wave -noupdate -group DUT->MUX /main/DUT/U_WBP_Mux/mux_src_i
    add wave -noupdate -group DUT->MUX /main/DUT/U_WBP_Mux/mux_src_o
    add wave -noupdate -group DUT->MUX /main/DUT/U_WBP_Mux/rst_n_i
    add wave -noupdate -group cpu /main/DUT/U_CPU/U_cpu_core/clk_i
    add wave -noupdate -group cpu /main/DUT/U_CPU/U_cpu_core/rst_i
    add wave -noupdate -group cpu /main/DUT/U_CPU/U_cpu_core/irq_i
    add wave -noupdate -group cpu /main/DUT/U_CPU/U_cpu_core/fault_o
    add wave -noupdate -group cpu /main/DUT/U_CPU/U_cpu_core/im_addr_o
    add wave -noupdate -group cpu /main/DUT/U_CPU/U_cpu_core/im_rd_o
    add wave -noupdate -group cpu /main/DUT/U_CPU/U_cpu_core/im_data_i
    add wave -noupdate -group cpu /main/DUT/U_CPU/U_cpu_core/im_valid_i
    add wave -noupdate -group cpu /main/DUT/U_CPU/U_cpu_core/dm_addr_o
    add wave -noupdate -group cpu /main/DUT/U_CPU/U_cpu_core/dm_data_s_o
    add wave -noupdate -group cpu /main/DUT/U_CPU/U_cpu_core/dm_data_l_i
    add wave -noupdate -group cpu /main/DUT/U_CPU/U_cpu_core/dm_data_select_o
    add wave -noupdate -group cpu /main/DUT/U_CPU/U_cpu_core/dm_store_o
    add wave -noupdate -group cpu /main/DUT/U_CPU/U_cpu_core/dm_load_o
    add wave -noupdate -group cpu /main/DUT/U_CPU/U_cpu_core/dm_load_done_i
    add wave -noupdate -group cpu /main/DUT/U_CPU/U_cpu_core/dm_store_done_i
    add wave -noupdate -group cpu /main/DUT/U_CPU/U_cpu_core/dbg_force_i
    add wave -noupdate -group cpu /main/DUT/U_CPU/U_cpu_core/dbg_enabled_o
    add wave -noupdate -group cpu /main/DUT/U_CPU/U_cpu_core/dbg_insn_i
    add wave -noupdate -group cpu /main/DUT/U_CPU/U_cpu_core/dbg_insn_set_i
    add wave -noupdate -group cpu /main/DUT/U_CPU/U_cpu_core/dbg_insn_ready_o
    add wave -noupdate -group cpu /main/DUT/U_CPU/U_cpu_core/dbg_mbx_data_i
    add wave -noupdate -group cpu /main/DUT/U_CPU/U_cpu_core/dbg_mbx_write_i
    add wave -noupdate -group cpu /main/DUT/U_CPU/U_cpu_core/dbg_mbx_data_o
    add wave -noupdate -group cpu /main/DUT/U_CPU/U_cpu_core/f_stall
    add wave -noupdate -group cpu /main/DUT/U_CPU/U_cpu_core/x_stall
    add wave -noupdate -group cpu /main/DUT/U_CPU/U_cpu_core/x_kill
    add wave -noupdate -group cpu /main/DUT/U_CPU/U_cpu_core/d_stall
    add wave -noupdate -group cpu /main/DUT/U_CPU/U_cpu_core/d_kill
    add wave -noupdate -group cpu /main/DUT/U_CPU/U_cpu_core/d_stall_req
    add wave -noupdate -group cpu /main/DUT/U_CPU/U_cpu_core/w_stall_req
    add wave -noupdate -group cpu /main/DUT/U_CPU/U_cpu_core/x_stall_req
    add wave -noupdate -group cpu /main/DUT/U_CPU/U_cpu_core/x_fault
    add wave -noupdate -group cpu /main/DUT/U_CPU/U_cpu_core/x2f_pc_bra
    add wave -noupdate -group cpu /main/DUT/U_CPU/U_cpu_core/x2f_bra
    add wave -noupdate -group cpu /main/DUT/U_CPU/U_cpu_core/x2f_dbg_toggle
    add wave -noupdate -group cpu /main/DUT/U_CPU/U_cpu_core/f2d_pc
    add wave -noupdate -group cpu /main/DUT/U_CPU/U_cpu_core/f2d_ir
    add wave -noupdate -group cpu /main/DUT/U_CPU/U_cpu_core/f2d_valid
    add wave -noupdate -group cpu /main/DUT/U_CPU/U_cpu_core/rf_rs1
    add wave -noupdate -group cpu /main/DUT/U_CPU/U_cpu_core/rf_rs2
    add wave -noupdate -group cpu /main/DUT/U_CPU/U_cpu_core/rf_rd
    add wave -noupdate -group cpu /main/DUT/U_CPU/U_cpu_core/rf_rd_value
    add wave -noupdate -group cpu /main/DUT/U_CPU/U_cpu_core/rf_rd_ecc
    add wave -noupdate -group cpu /main/DUT/U_CPU/U_cpu_core/rf_rd_ecc_flip
    add wave -noupdate -group cpu /main/DUT/U_CPU/U_cpu_core/rf_rd_write
    add wave -noupdate -group cpu /main/DUT/U_CPU/U_cpu_core/d2x_valid
    add wave -noupdate -group cpu /main/DUT/U_CPU/U_cpu_core/d2x_pc
    add wave -noupdate -group cpu /main/DUT/U_CPU/U_cpu_core/d2x_rs1
    add wave -noupdate -group cpu /main/DUT/U_CPU/U_cpu_core/d2x_rs2
    add wave -noupdate -group cpu /main/DUT/U_CPU/U_cpu_core/d2x_rd
    add wave -noupdate -group cpu /main/DUT/U_CPU/U_cpu_core/d2x_fun
    add wave -noupdate -group cpu /main/DUT/U_CPU/U_cpu_core/d2x_opcode
    add wave -noupdate -group cpu /main/DUT/U_CPU/U_cpu_core/d2x_shifter_sign
    add wave -noupdate -group cpu /main/DUT/U_CPU/U_cpu_core/d2x_is_load
    add wave -noupdate -group cpu /main/DUT/U_CPU/U_cpu_core/d2x_is_store
    add wave -noupdate -group cpu /main/DUT/U_CPU/U_cpu_core/d2x_is_undef
    add wave -noupdate -group cpu /main/DUT/U_CPU/U_cpu_core/d2x_is_write_ecc
    add wave -noupdate -group cpu /main/DUT/U_CPU/U_cpu_core/d2x_is_fix_ecc
    add wave -noupdate -group cpu /main/DUT/U_CPU/U_cpu_core/d2x_imm
    add wave -noupdate -group cpu /main/DUT/U_CPU/U_cpu_core/d2x_is_signed_alu_op
    add wave -noupdate -group cpu /main/DUT/U_CPU/U_cpu_core/d2x_is_add_o
    add wave -noupdate -group cpu /main/DUT/U_CPU/U_cpu_core/d2x_rd_source
    add wave -noupdate -group cpu /main/DUT/U_CPU/U_cpu_core/d2x_rd_write
    add wave -noupdate -group cpu /main/DUT/U_CPU/U_cpu_core/d2x_csr_sel
    add wave -noupdate -group cpu /main/DUT/U_CPU/U_cpu_core/d2x_csr_imm
    add wave -noupdate -group cpu /main/DUT/U_CPU/U_cpu_core/d2x_is_csr
    add wave -noupdate -group cpu /main/DUT/U_CPU/U_cpu_core/d2x_is_mret
    add wave -noupdate -group cpu /main/DUT/U_CPU/U_cpu_core/d2x_is_ebreak
    add wave -noupdate -group cpu /main/DUT/U_CPU/U_cpu_core/d2x_csr_load_en
    add wave -noupdate -group cpu /main/DUT/U_CPU/U_cpu_core/d2x_alu_op1
    add wave -noupdate -group cpu /main/DUT/U_CPU/U_cpu_core/d2x_alu_op2
    add wave -noupdate -group cpu /main/DUT/U_CPU/U_cpu_core/d2x_use_op1
    add wave -noupdate -group cpu /main/DUT/U_CPU/U_cpu_core/d2x_use_op2
    add wave -noupdate -group cpu /main/DUT/U_CPU/U_cpu_core/d2x_use_rs1
    add wave -noupdate -group cpu /main/DUT/U_CPU/U_cpu_core/d2x_use_rs2
    add wave -noupdate -group cpu /main/DUT/U_CPU/U_cpu_core/d2x_is_multiply
    add wave -noupdate -group cpu /main/DUT/U_CPU/U_cpu_core/d2x_is_divide
    add wave -noupdate -group cpu /main/DUT/U_CPU/U_cpu_core/x2w_rd
    add wave -noupdate -group cpu /main/DUT/U_CPU/U_cpu_core/x2w_rd_value
    add wave -noupdate -group cpu /main/DUT/U_CPU/U_cpu_core/x2w_rd_shifter
    add wave -noupdate -group cpu /main/DUT/U_CPU/U_cpu_core/x2w_rd_multiply
    add wave -noupdate -group cpu /main/DUT/U_CPU/U_cpu_core/x2w_dm_addr
    add wave -noupdate -group cpu /main/DUT/U_CPU/U_cpu_core/x2w_rd_write
    add wave -noupdate -group cpu /main/DUT/U_CPU/U_cpu_core/x2w_fun
    add wave -noupdate -group cpu /main/DUT/U_CPU/U_cpu_core/x2w_store
    add wave -noupdate -group cpu /main/DUT/U_CPU/U_cpu_core/x2w_load
    add wave -noupdate -group cpu /main/DUT/U_CPU/U_cpu_core/x2w_rd_source
    add wave -noupdate -group cpu /main/DUT/U_CPU/U_cpu_core/x2w_valid
    add wave -noupdate -group cpu /main/DUT/U_CPU/U_cpu_core/x2w_ecc_flip
    add wave -noupdate -group cpu /main/DUT/U_CPU/U_cpu_core/x_rs2_value
    add wave -noupdate -group cpu /main/DUT/U_CPU/U_cpu_core/x_rs1_value
    add wave -noupdate -group cpu /main/DUT/U_CPU/U_cpu_core/x_rs1_ecc_err
    add wave -noupdate -group cpu /main/DUT/U_CPU/U_cpu_core/x_rs2_ecc_err
    add wave -noupdate -group cpu /main/DUT/U_CPU/U_cpu_core/rf_bypass_rd_value
    add wave -noupdate -group cpu /main/DUT/U_CPU/U_cpu_core/rf_bypass_rd_write
    add wave -noupdate -group cpu /main/DUT/U_CPU/U_cpu_core/csr_time
    add wave -noupdate -group cpu /main/DUT/U_CPU/U_cpu_core/csr_cycles
    add wave -noupdate -group cpu /main/DUT/U_CPU/U_cpu_core/d2x_is_add
    add wave -noupdate -group cpu /main/DUT/U_CPU/U_cpu_core/sys_tick
    add wave -noupdate -group cpu /main/DUT/U_CPU/U_cpu_core/x2f_bra_d0
    add wave -noupdate -group cpu /main/DUT/U_CPU/U_cpu_core/x2f_bra_d1
    add wave -noupdate -expand -group wrc-cpu /main/DUT/U_CPU/clk_sys_i
    add wave -noupdate -expand -group wrc-cpu /main/DUT/U_CPU/rst_n_i
    add wave -noupdate -expand -group wrc-cpu /main/DUT/U_CPU/irq_i
    add wave -noupdate -expand -group wrc-cpu /main/DUT/U_CPU/dwb_o
    add wave -noupdate -expand -group wrc-cpu /main/DUT/U_CPU/dwb_i
    add wave -noupdate -expand -group wrc-cpu /main/DUT/U_CPU/host_slave_i
    add wave -noupdate -expand -group wrc-cpu /main/DUT/U_CPU/host_slave_o
    add wave -noupdate -expand -group wrc-cpu /main/DUT/U_CPU/cpu_rst
    add wave -noupdate -expand -group wrc-cpu /main/DUT/U_CPU/cpu_rst_d
    add wave -noupdate -expand -group wrc-cpu /main/DUT/U_CPU/im_addr
    add wave -noupdate -expand -group wrc-cpu /main/DUT/U_CPU/im_data
    add wave -noupdate -expand -group wrc-cpu /main/DUT/U_CPU/im_valid
    add wave -noupdate -expand -group wrc-cpu /main/DUT/U_CPU/ha_im_addr
    add wave -noupdate -expand -group wrc-cpu /main/DUT/U_CPU/ha_im_wdata
    add wave -noupdate -expand -group wrc-cpu /main/DUT/U_CPU/ha_im_write
    add wave -noupdate -expand -group wrc-cpu /main/DUT/U_CPU/im_addr_muxed
    add wave -noupdate -expand -group wrc-cpu /main/DUT/U_CPU/dm_addr
    add wave -noupdate -expand -group wrc-cpu /main/DUT/U_CPU/dm_data_s
    add wave -noupdate -expand -group wrc-cpu /main/DUT/U_CPU/dm_data_l
    add wave -noupdate -expand -group wrc-cpu /main/DUT/U_CPU/dm_data_select
    add wave -noupdate -expand -group wrc-cpu /main/DUT/U_CPU/dm_load
    add wave -noupdate -expand -group wrc-cpu /main/DUT/U_CPU/dm_store
    add wave -noupdate -expand -group wrc-cpu /main/DUT/U_CPU/dm_load_done
    add wave -noupdate -expand -group wrc-cpu /main/DUT/U_CPU/dm_store_done
    add wave -noupdate -expand -group wrc-cpu /main/DUT/U_CPU/dm_cycle_in_progress
    add wave -noupdate -expand -group wrc-cpu /main/DUT/U_CPU/dm_is_wishbone
    add wave -noupdate -expand -group wrc-cpu /main/DUT/U_CPU/dm_mem_rdata
    add wave -noupdate -expand -group wrc-cpu /main/DUT/U_CPU/dm_wb_rdata
    add wave -noupdate -expand -group wrc-cpu /main/DUT/U_CPU/dm_wb_write
    add wave -noupdate -expand -group wrc-cpu /main/DUT/U_CPU/dm_select_wb
    add wave -noupdate -expand -group wrc-cpu /main/DUT/U_CPU/dm_data_write
    add wave -noupdate -expand -group wrc-cpu /main/DUT/U_CPU/dbg_insn
    add wave -noupdate -expand -group wrc-cpu /main/DUT/U_CPU/dwb_out
    add wave -noupdate -expand -group wrc-cpu /main/DUT/U_CPU/regs_in
    add wave -noupdate -expand -group wrc-cpu /main/DUT/U_CPU/regs_out
    TreeUpdate [SetDefaultTree]
    WaveRestoreCursors {{Cursor 2} {402323834470 fs} 1} {{Cursor 2} {1203233669880 fs} 0} {{Cursor 3} {1419940330 fs} 0}
    WaveRestoreCursors {{Cursor 2} {402323834470 fs} 1} {{Cursor 2} {1203233669880 fs} 0} {{Cursor 3} {548446650000 fs} 0}
    quietly wave cursor active 3
    configure wave -namecolwidth 363
    configure wave -valuecolwidth 163
    configure wave -justifyvalue left
    ......@@ -207,4 +345,4 @@ configure wave -griddelta 40
    configure wave -timeline 0
    configure wave -timelineunits ns
    update
    WaveRestoreZoom {1202933155800 fs} {1203674570090 fs}
    WaveRestoreZoom {0 fs} {2525250 ns}
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