... | ... | @@ -16,92 +16,19 @@ The White Rabbit PTP Core can operate in one of the following modes: |
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- **Slave**: synchronizes its internal oscillator to another WR Master
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device
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-----
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### FPGA platforms and boards supported by the White Rabbit PTP Core
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<table>
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<tbody>
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<tr class="odd">
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<td><strong>Platform</strong></td>
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<td><strong>Family</strong></td>
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<td><strong>Tranceiver</strong></td>
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<td><b> Reference designs </b></td>
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<td><strong>Boards</strong></td>
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</tr>
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<tr class="even">
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<td>Xilinx</td>
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<td>Spartan-6</td>
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<td>GTP-6</td>
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<td><a href="https://www.ohwr.org/project/wr-cores/tree/master/">spec_ref_design</a>, [svec_ref_design](https://www.ohwr.org/project/wr-cores/tree/master/)</td>
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<td><a href="https://www.ohwr.org/spec/wiki">SPEC</a>, <a href="https://www.ohwr.org/svec/wiki">SVEC</a>, <a href="https://www.ohwr.org/spexi/wiki">SPEXI</a>, ....</td>
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</tr>
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<tr class="odd">
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<td>Xilinx</td>
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<td>Virtex-6</td>
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<td>GTX-6</td>
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<td><a href="https://www.ohwr.org/project/wr-switch-hdl/tree/proposed_master/top"> wr-switch-hdl</a></td>
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<td>WR Switch</td>
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</tr>
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<tr class="even">
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<td>Xilinx</td>
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<td>Artix-7</td>
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<td>GTP-7</td>
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<td>[CLBv3](https://www.ohwr.org/project/wr-cores/tree/master/)</td>
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<td>Nikhef.</td>
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</tr>
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<tr class="odd">
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<td>Xilinx</td>
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<td>Kintex-7</td>
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<td>GTX-7</td>
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<td><a href="https://www.ohwr.org/project/wr-cores/tree/master/">CLBv2</a>, <a href="https://www.xilinx.com/products/boards-and-kits/ek-k7-kc705-g.html">KC705</a> with [Rabbit_FX FMC](https://redmine.nikhef.nl/et/project/rabbit_fx/wiki)</td>
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<td>Nikhef, Seven Solutions</td>
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</tr>
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<tr class="even">
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<td>Xilinx</td>
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<td>Virtex-7</td>
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<td>GTX-7</td>
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<td></td>
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<td>Nikhef, Seven Solutions (TxRx in wr-cores)</td>
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</tr>
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<tr class="odd">
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<td>Xilinx</td>
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<td>Virtex-7</td>
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<td>GTH-7</td>
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<td></td>
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<td>Nikhef. Not yet fully supported. [Contact us](/Wrpc-core#contacts) <br />(TxRx in wr-cores)</td>
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</tr>
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<tr class="even">
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<td>Xilinx</td>
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<td>Kintex Ultrascale</td>
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<td>GTH-US</td>
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<td>SIS8300</td>
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<td><em>Prototype working</em> (uses different Serdes (GTH) than Kintex,
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requires a new wrapper with bitslide, and making sure the Serdes is deterministic). [Contact us](/Wrpc-core#contacts)</td>
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</tr>
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<tr class="odd">
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<td>Xilinx</td>
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<td>Zynq-7 (=Kintex-7 + ARM uP)</td>
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<td>GTX-7</td>
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<td>[fasec_ref_design](https://www.ohwr.org/project/wr-cores/tree/master/)</td>
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<td><a href="https://www.ohwr.org/project/fasec/wiki">FASEC</a>, Seven Solutions.</td>
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</tr>
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<tr class="even">
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<td>Altera</td>
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<td>Arria II</td>
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<td></td>
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<td></td>
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<td>GSI</td>
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</tr>
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<tr class="odd">
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<td>Altera</td>
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<td>[Arria V](platform-arria5)</td>
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<td></td>
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<td>[vfchd_ref_design](https://www.ohwr.org/project/wr-cores/tree/master/)</td>
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<td><a href="board-vfc-hd">VFC-HD</a>, GSI</td>
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</tr>
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</tbody>
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</table>
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|**Platform**|**Family**|**Tranceiver**|**Reference designs**|**Boards**|
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|----|----|----|----|----|
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|Xilinx|Spartan-6|GTP-6|[spec_ref_design](https://www.ohwr.org/project/wr-cores/tree/master/), [svec_ref_design](https://www.ohwr.org/project/wr-cores/tree/master/)|[SPEC](https://www.ohwr.org/spec/wiki), [SVEC](https://www.ohwr.org/svec/wiki), [SPEXI](https://www.ohwr.org/spexi/wiki), ....|
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|Xilinx|Virtex-6|GTX-6|||
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|Xilinx|Artix-7|GTP-7|[CLBv3](https://www.ohwr.org/project/wr-cores/tree/master/)|Nikhef.|
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|Xilinx|Kintex-7|GTX-7|[CLBv2](https://www.ohwr.org/project/wr-cores/tree/master/), [KC705](https://www.xilinx.com/products/boards-and-kits/ek-k7-kc705-g.html) with [Rabbit_FX FMC](https://redmine.nikhef.nl/et/project/rabbit_fx/wiki)|Nikhef, Seven Solutions|
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|Xilinx|Virtex-7|GTX-7||Nikhef, Seven Solutions|
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|Xilinx|Virtex-7|GTH-7||Nikhef. Not yet fully supported. [Contact us](/Wrpc-core#contacts)|
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|Xilinx|Kintex Ultrascale|GTH-US, GTY-US||Work in progress (uses different Serdes (GTH, GTY) than Kintex,
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requires a new wrapper with bitslide, and making sure the Serdes is deterministic). [Contact us](/Wrpc-core#contacts)|
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|Xilinx|Zynq-7 (=Kintex-7 + ARM uP)|GTX-7|[fasec_ref_design](https://www.ohwr.org/project/wr-cores/tree/master/)|[FASEC](https://www.ohwr.org/project/fasec/wiki), Seven Solutions.|
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|Altera|Arria II|||GSI|
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|Altera|[Arria V](platform-arria5)||[vfchd_ref_design](https://www.ohwr.org/project/wr-cores/tree/master/)|[VFC-HD](board-vfc-hd), GSI|
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-----
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... | ... | @@ -162,96 +89,26 @@ requires a new wrapper with bitslide, and making sure the Serdes is deterministi |
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## Roadmap for WR PTP Core releases
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<table>
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<tbody>
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<tr class="odd">
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<td></td>
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<td><b> v4.1 </b></td>
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<td><b> v4.2 </b></td>
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</tr>
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<tr class="even">
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<td><strong>Release date</strong></td>
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<td>7/07/2017</td>
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<td>19/12/2017</td>
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</tr>
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<tr class="odd">
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<td>[PCIe reset bugfix for standalone operation](https://www.ohwr.org/work_packages/1567)</td>
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<td><b> x </b></td>
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<td></td>
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</tr>
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<tr class="even">
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<td>Fixes and updates in HDL wrappers:<br />
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<a href="https://www.ohwr.org/project/wr-cores/issues/33">[1599]</a>, <a href="https://www.ohwr.org/project/wr-cores/issues/32">[1600]</a>, [[1604]](https://www.ohwr.org/project/wr-cores/issues/28)</td>
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<td><b> x </b></td>
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<td></td>
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</tr>
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<tr class="odd">
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<td>[Fixed Rx termination scheme for Spartan6 PHY](https://www.ohwr.org/work_packages/1598)</td>
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<td><b> x </b></td>
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<td></td>
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</tr>
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<tr class="even">
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<td>[WRPC diagnostics over Wishbone, and host tool to read it](https://www.ohwr.org/project/wr-cores/issues/30)</td>
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<td><b> x </b></td>
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<td></td>
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</tr>
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<tr class="odd">
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<td>Built-in <a href="https://www.ohwr.org/work_packages/1605">default init script</a> and [VLANs support](https://www.ohwr.org/work_packages/1612)</td>
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<td><b> x </b></td>
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<td></td>
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</tr>
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<tr class="even">
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<td>[PPSi updated incl. fixed p2p mode](https://www.ohwr.org/project/wr-cores/issues/26)</td>
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<td><b> x </b></td>
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<td></td>
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</tr>
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<tr class="odd">
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<td>[Added _mode abscal_ for absolute calibration](https://www.ohwr.org/work_packages/1603)</td>
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<td><b> x </b></td>
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<td></td>
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</tr>
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<tr class="even">
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<td>[New documentation: _WRPC Failures and Diagnostics_](https://www.ohwr.org/project/wr-cores/issues/24)</td>
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<td><b> x </b></td>
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<td></td>
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</tr>
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<tr class="odd">
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<td>[Vivado synthesis support](https://www.ohwr.org/work_packages/1706)</td>
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<td></td>
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<td><b> x </b></td>
|
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</tr>
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<tr class="even">
|
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<td>Xilinx <a href="https://www.ohwr.org/work_packages/1705">Zynq</a> , <a href="https://www.ohwr.org/work_packages/1708">Artix-7, Kintex-7</a> reference designs</td>
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<td></td>
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<td><b> x </b></td>
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</tr>
|
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<tr class="odd">
|
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<td>Fixed testbench: <a href="https://www.ohwr.org/work_packages/1658">[1658]</a>, [[1659]](https://www.ohwr.org/work_packages/1659)</td>
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<td></td>
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<td><b> x </b></td>
|
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</tr>
|
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<tr class="even">
|
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<td>[Fixed PTP calculations for links longer than 13km](https://www.ohwr.org/work_packages/1627)</td>
|
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<td></td>
|
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|
<td><b> x </b></td>
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</tr>
|
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<tr class="odd">
|
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<td>[Fixed synchronization for VFC-HD board with SNMP](https://www.ohwr.org/work_packages/1649)</td>
|
|
|
<td></td>
|
|
|
<td><b> x </b></td>
|
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</tr>
|
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<tr class="even">
|
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|
<td>[New WRPC Shell command to create SDBFS image](https://www.ohwr.org/work_packages/1581)</td>
|
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<td></td>
|
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|
<td><b> x </b></td>
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</tr>
|
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<tr class="odd">
|
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<td>[LLDP support](https://www.ohwr.org/work_packages/1711)</td>
|
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|
<td></td>
|
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|
<td><b> x </b></td>
|
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</tr>
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</tbody>
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</table>
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||**v4.1**|**v4.2**|
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|----|----|----|
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|**Release date**|7/07/2017|19/12/2017|
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|[PCIe reset bugfix for standalone operation](https://www.ohwr.org/work_packages/1567)|**x**||
|
|
|
|Fixes and updates in HDL wrappers:
|
|
|
[[1599]](https://www.ohwr.org/project/wr-cores/issues/33), [[1600]](https://www.ohwr.org/project/wr-cores/issues/32), [[1604]](https://www.ohwr.org/project/wr-cores/issues/28)|**x**||
|
|
|
|[Fixed Rx termination scheme for Spartan6 PHY](https://www.ohwr.org/work_packages/1598)|**x**||
|
|
|
|[WRPC diagnostics over Wishbone, and host tool to read it](https://www.ohwr.org/project/wr-cores/issues/30)|**x**||
|
|
|
|Built-in [default init script](https://www.ohwr.org/work_packages/1605) and [VLANs support](https://www.ohwr.org/work_packages/1612)|**x**||
|
|
|
|[PPSi updated incl. fixed p2p mode](https://www.ohwr.org/project/wr-cores/issues/26)|**x**||
|
|
|
|[Added _mode abscal_ for absolute calibration](https://www.ohwr.org/work_packages/1603)|**x**||
|
|
|
|[New documentation: _WRPC Failures and Diagnostics_](https://www.ohwr.org/project/wr-cores/issues/24)|**x**||
|
|
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|[Vivado synthesis support](https://www.ohwr.org/work_packages/1706)||**x**|
|
|
|
|Xilinx [Zynq](https://www.ohwr.org/work_packages/1705) , [Artix-7, Kintex-7](https://www.ohwr.org/work_packages/1708) reference designs||**x**|
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|Fixed testbench: [[1658]](https://www.ohwr.org/work_packages/1658), [[1659]](https://www.ohwr.org/work_packages/1659)||**x**|
|
|
|
|[Fixed PTP calculations for links longer than 13km](https://www.ohwr.org/work_packages/1627)||**x**|
|
|
|
|[Fixed synchronization for VFC-HD board with SNMP](https://www.ohwr.org/work_packages/1649)||**x**|
|
|
|
|[New WRPC Shell command to create SDBFS image](https://www.ohwr.org/work_packages/1581)||**x**|
|
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|
|[LLDP support](https://www.ohwr.org/work_packages/1711)||**x**|
|
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|
|
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|
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-----
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|
... | ... | @@ -264,43 +121,17 @@ requires a new wrapper with bitslide, and making sure the Serdes is deterministi |
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|
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## Project Status
|
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|
|
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<table>
|
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<tbody>
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<tr class="odd">
|
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<td><strong>Date</strong></td>
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<td><strong>Event</strong></td>
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</tr>
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<tr class="even">
|
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<td>11-08-2012</td>
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<td>v2.0 Release</td>
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</tr>
|
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<tr class="odd">
|
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<td>20-12-2013</td>
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<td>v2.1 Release</td>
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</tr>
|
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|
<tr class="even">
|
|
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<td>16-12-2015</td>
|
|
|
<td>v3.0 Release</td>
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|
|
</tr>
|
|
|
<tr class="odd">
|
|
|
<td>15-03-2017</td>
|
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|
<td>v4.0 Release</td>
|
|
|
</tr>
|
|
|
<tr class="even">
|
|
|
<td>7-07-2017</td>
|
|
|
<td>v4.1 Release</td>
|
|
|
</tr>
|
|
|
<tr class="odd">
|
|
|
<td>19-12-2017</td>
|
|
|
<td>v4.2 Release</td>
|
|
|
</tr>
|
|
|
<tr class="even">
|
|
|
<td>31-01-2018</td>
|
|
|
<td>li hongming from Tsinghua University showed it is possible to use only a single external oscillator<br />
|
|
|
instead of two by using an internal PLL of the FPGA. Not available in a Release.</td>
|
|
|
</tr>
|
|
|
</tbody>
|
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|
</table>
|
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|
|**Date**|**Event**|
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|
|
|----|----|
|
|
|
|11-08-2012|v2.0 Release|
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|
|20-12-2013|v2.1 Release|
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|
|
|16-12-2015|v3.0 Release|
|
|
|
|15-03-2017|v4.0 Release|
|
|
|
|7-07-2017|v4.1 Release|
|
|
|
|19-12-2017|v4.2 Release|
|
|
|
|31-01-2018|li hongming from Tsinghua University showed it is possible to use only a single external oscillator
|
|
|
instead of two by using an internal PLL of the FPGA. Not available in a Release.|
|
|
|
|
|
|
|
|
|
-----
|
|
|
|
... | ... | |