... | @@ -104,13 +104,16 @@ Streamer words and |
... | @@ -104,13 +104,16 @@ Streamer words and |
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*\* the time the first word transported in this Etherent frame is
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*\* the time the first word transported in this Etherent frame is
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presented (`rx_valid_` and `rx_first_p1_o` are HIGH)
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presented (`rx_valid_` and `rx_first_p1_o` are HIGH)
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*Note:** The fixed latency value guarantees a fixed internal delay to
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*Note:** The configured value of fixed network latency guarantees a
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the output of data from the rx streamer. During lab tests, when fixed
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fixed latency internally (inside the FPGA) with a jitter of + /- one
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latency is measured from transmission to reception, an error of one
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clock cycle (+/-8ns). The latency observed by the application might see
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reference clock cycle (8ns for 125MHz clock) is seen compared to the
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a static offset to the configured value. During lab tests, when fixed
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fixed latency set in the rx\_streamer entity. This is due to a static
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latency was measured from transmission to reception of BTrain frame, a
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offset that is repeatable and measurable and that can be accounted for
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static offset of 30ns and 40ns was seen for two different FPGAs, when
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during system calibration when a strict fixed-latency must be
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observing the transmission latency on a scope. This static offset should
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be repeatable and measurable (per board, per bitstream) and can be
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accounted for during system calibration when a strict fixed-latency must
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be
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observed.
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observed.
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### **WR timing input (optional, to allow latency measurement, Tx and Rx Streamer):**
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### **WR timing input (optional, to allow latency measurement, Tx and Rx Streamer):**
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