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# Interface of Transmit and Receive Streamer modules
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# Interface of Transmit and Receive Streamer modules
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The Transmit and Receive Streamers are xtx\_streamer.vhd and
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xrx\_streamer.vhd located in modules/wr\_streamers folder of
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[wr-cores](https://www.ohwr.org/project/wr-cores/tree/master) .
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### **Transceiver configuration:**
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### **Transceiver configuration:**
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VHDL generics to specify Tx and Rx pair configuration:
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VHDL generics to specify Tx and Rx pair configuration:
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... | @@ -49,12 +53,14 @@ VHDL generics to specify Tx and Rx pair configuration: |
... | @@ -49,12 +53,14 @@ VHDL generics to specify Tx and Rx pair configuration: |
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### **Networking configuration (Tx and Rx Streamer):**
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### **Networking configuration (Tx and Rx Streamer):**
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Information on network configuration is stored in VHDL records,
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Information on network configuration is provided in VHDL records,
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respectively `t_tx_streamer_cfg` and `t_rx_streamer_cfg`. These can be
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respectively `t_tx_streamer_cfg` and `t_rx_streamer_cfg`. This interface
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written to directly from the application or can take their value from
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allows application-specific logic to provide network configuration
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the [wishbone memory
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directly. This network configuration provided directly in the VHDL
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records can be overriden by configuration provided in wishbone
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registers, see [wishbone memory
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map](https://www.ohwr.org/project/wr-cores/uploads/123c8f37ddad8747f18e780978d7bc03/wr_streamers_wb.pdf)
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map](https://www.ohwr.org/project/wr-cores/uploads/123c8f37ddad8747f18e780978d7bc03/wr_streamers_wb.pdf)
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(External configuration)
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(External configuration).
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`t_tx_streamer_cfg` contains the following fields:
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`t_tx_streamer_cfg` contains the following fields:
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