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Development-instructions.md

@@ -21,7 +21,18 @@ The repo is organized as follows:
     `hw_platform`/@firmware\_name`. For example,
     `spec\_1\_1/wr\_core\_demo@ means a demo project for the WR core
     synthesized for the SPEC 1.1. card. FPGA pin assignment files should
-    be also stored in top/ subdirectory.
+    be also stored in `top/` subdirectory.
+  - `syn` - synthesis-specific files and resulting binaries - for
+    example ISE/Quartus projects. Only the files which are necessary to
+    run a synthesis (i.e. `hdlmake` manifests, `.xise` or `.qpf` files
+    may be uploaded here). Pushing synthesis outputs (reports,
+    intermediate netlists, etc.) is forbidden, with an exception of
+    tested FPGA bitstreams which may take long time to build from
+    sources.
+  - `testbench` - testbenches, grouped in subdirectories with names
+    corresponding to the names of the modules being tested. Each
+    testbench must contain a simulation run script and a `hdlmake`
+    manifest.
 
 ## Coding style