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## Todo List
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## Todo List
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A very temporary todo list:
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[WRCore-todo](WRCore-todo)
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<table>
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<tbody>
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<tr class="odd">
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<td><strong>What</strong></td>
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<td><strong>Explanation</strong></td>
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<td><strong>Who</strong></td>
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</tr>
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<tr class="even">
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<td>Flexible Auxillary clock synchronization unit – hardware support.</td>
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<td>Add more auxilary clock inputs to <code>wr_softpll</code>, so a single WR core can support more than 1 FMC slot. Add a possibility of working with clocks of frequencies different than 125 MHz (impelent programmable dividers)</td>
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<td>tbd</td>
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</tr>
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<tr class="odd">
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<td>SoftPLL code optimization</td>
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<td>Make the SoftPLL work faster, possibly rewrite critical parts of the code in assembly. Currently it consumes quite a lot of the LM32 CPU time.</td>
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<td>tbd</td>
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</tr>
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<tr class="even">
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<td>SoftPLL performance optimization</td>
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<td>Fine-tune the control algorithm to obtain the lowest jitter and the best stability</td>
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<td>Pedro (?)</td>
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</tr>
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<tr class="odd">
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<td>Aux clock DAC control</td>
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<td>Define a way of telling the WR Core what type of DAC (or a programmable oscillator, such as Si57x) it has to drive without need for changes inside the WRPC software. That means, what hardware interface (I2C, SPI), part type, PI controller gains and thresholds, etc.</td>
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<td>tbd</td>
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</tr>
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<tr class="even">
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<td>Fix WR Fabric Mux (<code>wbp_mux</code>)</td>
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<td>The WBP mux module in <code>wr_core</code> randomly drops the status register of frames outputted from the core. Investigate and fix.</td>
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<td>Greg</td>
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</tr>
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<tr class="odd">
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<td>WR Core V2 interconnect</td>
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<td>Now Wesley's crossbar is fully operational - replace the intercon & LM32 CPU with the new components, using Pipelined Wishbone. Preserve one interconnect port of the intercon (accessible from outside the WR Core) for optional JTAG-over-Wishbone.</td>
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<td>Greg</td>
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</tr>
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<tr class="even">
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<td>WR Core mini-NIC RX DMA memory corruption</td>
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<td>The Minic sometimes goes out of the DMA RX buffer area designeted in RX_ADDR and RX_AVAIL registers, causing random crashes of the core. This has been temporarily fixed by adding MPROT registerm but must be properly investigated and fixed sometime.</td>
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<td>Greg</td>
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</tr>
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<tr class="odd">
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<td>Packets dropped in the Endpoint's FIFO</td>
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<td>Sometimes packets are lost (1 per 3000, depending on the ratio between the RX and refence clock frequencies) due to a bug in the RX or TX clock alignment FIFO. Find and fix.</td>
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<td>Tom</td>
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</tr>
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<tr class="even">
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<td>WR Core – manual skew adjustment causes errors in PTP</td>
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<td>Trying to manually adjust the skew on the PPS output causes the PTP servo to get crazy, entering a positive feedback look and trying to compensate this extra offset (and so, getting out of sync)</td>
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<td>Greg (?)</td>
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</tr>
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<tr class="odd">
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<td>WR Core – error in seconds field in timestamps</td>
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<td>After a few hours of operation, timestamps with invalid seconds value appear.</td>
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<td>Greg (?)</td>
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</tr>
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</tbody>
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</table>
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