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# Development
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*Coding style:**
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## Repo layout:
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The repository contains only generic and reusable White Rabbit cores, which should not be tied to any particular piece of hardware. If there are any platform dependencies, the platform-specific part should be clearly separated from the generic part.
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The repo is organized as follows:
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- `modules` - "big" modules, such as the WR Endpoint of WR Core - each
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in a separate subdirectory, with dir name matching the name of of
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the top level entity. Only platform-independent RTL code is allowed.
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- `platform` - platform dependent code, for example wrappers for
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gigabit transceivers or Chipscope cores.
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- `sim` - simulation models and header files
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- `top` - top level entities for actual hardware implementations (i.e.
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FPGA-wide top levels). Each design should be placed in a separate
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subdirectory with the name matching the pattern
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`hw_platform`/@firmware\_name`. For example,
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`spec\_1\_1/wr\_core\_demo@ means a demo project for the WR core
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synthesized for the SPEC 1.1. card. FPGA pin assignment files should
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be also stored in top/ subdirectory.
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## Coding style:
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In general, the OHR VHDL coding guidelines should be followed. However,
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due to large complexity of some of the modules, there are some
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