... | ... | @@ -114,13 +114,15 @@ C/HDL languages `c_prefix`, `hd_prefix` a single `prefix` for both. | |
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*Table 2. Peripheral attributes**
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| \* Attribute \*| **Status**| \* Description \*|
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|`hdl_entity`|mandatory|Name of the VHDL entity or Verilog module of the
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slave core to be
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generated|
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slave core to be generated|
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## Register attributes
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*Table 3. Register attributes**
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| \* Attribute \*| **Status**| \* Description \*|
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|`align = num`|optional|Alignment value for the field address. When given, wbgen2 will align the address of this register to the nearest multiple of `num`. \!\!|
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|`align = num`|optional|Alignment value for the field address. When
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given, wbgen2 will align the address of this register to the nearest
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multiple of `num`. \!\!|
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... | ... | |