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## Introduction
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## Introduction
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In wbgen2 terminology, a ”slave core” is an HDL entity which is
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In wbgen2 terminology, a ”slave core” is an HDL entity which is
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connected to
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connected to Wishbone bus on one side, and on the other side it provides
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Wishbone bus on one side, and on the other side it provides ports for
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ports for accessing memory mapped registers, FIFOs and RAMs, as shown on
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accessing memory mapped
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the following
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registers, FIFOs and RAMs, as shown on the following
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figure:
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figure:
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![](/uploads/a55ac5d2f8a96f02e8add8102574a55e/overwiew.png)
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![](/uploads/a55ac5d2f8a96f02e8add8102574a55e/overwiew.png)
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... | @@ -49,7 +48,10 @@ single peripheral which may consist of: |
... | @@ -49,7 +48,10 @@ single peripheral which may consist of: |
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- FIFO registers
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- FIFO registers
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- Interrupt lines
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- Interrupt lines
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Registers and FIFO registers can be split into fields of different
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Registers and FIFO registers can be split into fields of different
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types and sizes, as shown on the figure below:
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types and sizes, as shown on the figure
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below:
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![](/uploads/6e5799be4d901ccacb4d9e83a731fb41/reglayout.png)
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Below you can find a sample of WB file syntax:
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Below you can find a sample of WB file syntax:
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