... | @@ -16,7 +16,7 @@ HDL code, C code and documentation from a single, easily editable file. |
... | @@ -16,7 +16,7 @@ HDL code, C code and documentation from a single, easily editable file. |
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*Features supported by the latest version:**
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*Features supported by the latest version:**
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- Customizable register types, with multiple access options and
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- Customisable register types, with multiple access options and
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multiple clocking schemes
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multiple clocking schemes
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- Configurable memory blocks
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- Configurable memory blocks
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- Peripheral-level interrupts via Embedded Interrupt Controller
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- Peripheral-level interrupts via Embedded Interrupt Controller
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... | @@ -108,13 +108,13 @@ provided in peripheral, register, RAM, FIFO and IRQ block sections. |
... | @@ -108,13 +108,13 @@ provided in peripheral, register, RAM, FIFO and IRQ block sections. |
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## 3.1. [Peripheral block](wbgen2-peripheral)
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## 3.1. [Peripheral block](wbgen2-peripheral)
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Main block in file, represeting an entire Wishbone peripheral.
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Main block in file, representing an entire Wishbone peripheral.
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## 3.2. [Register (reg) block](wbgen2-reg).
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## 3.2. [Register (reg) block](wbgen2-reg).
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Block describing a memory-mapped register.
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Block describing a memory-mapped register.
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## 3.3. [FIFO registeter (fifo) block](wbgen2-fifo)
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## 3.3. [FIFO register (fifo) block](wbgen2-fifo)
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Block describing a memory-mapped FIFO register.
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Block describing a memory-mapped FIFO register.
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... | @@ -130,7 +130,7 @@ Block describing an configurable IRQ line |
... | @@ -130,7 +130,7 @@ Block describing an configurable IRQ line |
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## 4.1. Command line options
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## 4.1. Command line options
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## 4.2. Troubleshooting, known problems
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## 4.2. Limitations and known bugs
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