... | @@ -109,6 +109,17 @@ signal name of register "DDR" would be `gpio_ddr_o`. The format of |
... | @@ -109,6 +109,17 @@ signal name of register "DDR" would be `gpio_ddr_o`. The format of |
|
coding style. Note that you can provide either separate prefixes for
|
|
coding style. Note that you can provide either separate prefixes for
|
|
C/HDL languages `c_prefix`, `hd_prefix` a single `prefix` for both. |
|
|
C/HDL languages `c_prefix`, `hd_prefix` a single `prefix` for both. |
|
|
|
|
|
|
|
|
*Table 2. Peripheral attributes**
|
|
|
|
| \* Attribute \*| **Status**| \* Description \*|
|
|
|
|
|`hdl_entity`|mandatory|Name of the VHDL entity or Verilog module of the
|
|
|
|
slave core to be generated|
|
|
|
|
|
|
|
|
*Table 3. Register attributes**
|
|
|
|
| \* Attribute \*| **Status**| \* Description \*|
|
|
|
|
|`align = num`|optional|Alignment value for the field address. When
|
|
|
|
given, wbgen2 will align the address of this register to the nearest
|
|
|
|
multiple of `num`. \!\!|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
### Files
|
|
### Files
|
... | | ... | |