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# wbgen2 Documentation
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*Purpose of wbgen2**
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wbgen2 is a tool that generates a VHDL/Verilog core that implements a
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Wishbone bus slave containing certain registers, memory blocks, FIFOs
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and interrupts. The input is a C-like syntax file with an abstract
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description of what do we want to have in the slave. wbgen2 does then
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all the dirty work for us:
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\- Automatically allocates the memory layout
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\- Generates VHDL/Verilog code
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\- Generates C header file for the driver development
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\- Generates nice HTML documentation
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\- and much more\!
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### Files
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* [overwiew.png](/uploads/a55ac5d2f8a96f02e8add8102574a55e/overwiew.png)
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* [slavecore.png](/uploads/84b682a744ead2218666ab886efa09ee/slavecore.png)
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* [reglayout.png](/uploads/6e5799be4d901ccacb4d9e83a731fb41/reglayout.png)
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* [alignment.png](/uploads/d839884b9044380e0a915051af9e57c9/alignment.png) |
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