... | ... | @@ -6,24 +6,28 @@ In wbgen2 terminology, a ”slave core” is an HDL entity which is |
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connected to
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Wishbone bus on one side, and on the other side it provides ports for
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accessing memory mapped
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registers, FIFOs and RAMs, as shown on the following figure:
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Generation of VHDL code for slaves consisting of memory mapped
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registers, FIFO regis-
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ters and RAMs
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• Automatic minimal address space generation
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• Generation of C header files containing addresses consistent with the
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VHDL core
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• Customizable register types, with multiple access options and multiple
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clocking schemes
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• Support for most common VHDL types
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• (optional) automatic instantiation and wiring of slave core into the
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VHDL design
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• (optional) documentation
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generator.
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registers, FIFOs and RAMs, as shown on the following
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figure:
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![](/uploads/a55ac5d2f8a96f02e8add8102574a55e/overwiew.png)
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*Features supported by the latest version:**
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- Customizable register types, with multiple access options and
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multiple clocking schemes
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- Configurable memory blocks
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- Peripheral-level interrupts via Embedded Interrupt Controller
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- Generation of VHDL/Verilog synthesizable code
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- Automatic address space layout generation
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- Generation of C header files containing memory map consistent with
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the HDL core
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- Support for popular synthesizable VHDL data types
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*Foreseen in near future**
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- FIFO register support
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- Pipelined Wishbone support
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### Files
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