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## wbgen2 Documentation
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1. h2. Introduction
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## Introduction
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In wbgen2 terminology, a ”slave core” is an HDL entity which is
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connected to
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... | ... | @@ -29,6 +29,11 @@ figure: |
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- FIFO register support
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- Pipelined Wishbone support
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The primitives are accessible from outside the slave core as
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VHDL/Verilog signals:
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## Input file syntax
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### Files
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