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*Purpose of wbgen2**
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wbgen2 is a tool that generates a VHDL/Verilog core that implements a
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Wishbone bus slave containing certain registers, memory blocks, FIFOs
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and interrupts. The input is a C-like syntax file with an abstract
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wbgen2 is a tool for generating VHDL/Verilog cores which implement
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Wishbone bus slaves with certain registers, memory blocks, FIFOs and
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interrupts. The input is a C-like syntax file with an abstract
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description of what do we want to have in the slave. wbgen2 does then
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all the dirty work for us:
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