|
|
# wbgen2 Documentation
|
|
|
|
|
|
1. Purpose of wbgen2\*
|
|
|
|
|
|
wbgen2 is a tool for generating VHDL/Verilog cores which implement
|
|
|
Wishbone bus slaves with certain registers, memory blocks, FIFOs and
|
|
|
interrupts. The input is a C-like syntax file with an abstract
|
|
|
description of what do we want to have in the slave. As a result, we get
|
|
|
(see fig. 1):
|
|
|
|
|
|
\- Automatically allocated memory layout
|
|
|
|
|
|
\- VHDL/Verilog code for the slave module
|
|
|
|
|
|
\- C header files for driver development
|
|
|
\- Nice HTML
|
|
|
documentation
|
|
|
1. **Purpose of
|
|
|
wbgen2**
|
|
|
|
|
|
![](/uploads/49f4784118ae42e07cb7c2b7b0c8388b/overview.png)
|
|
|
|
|
|
1. **Introduction**
|
|
|
|
|
|
In wbgen2 terminology, a ”slave core” is an HDL entity which is
|
|
|
connected to
|
|
|
Wishbone bus on one side, and on the other side it provides ports for
|
|
|
accessing memory mapped
|
|
|
registers, FIFOs and RAMs, as shown on the following figure:
|
|
|
|
|
|
Generation of VHDL code for slaves consisting of memory mapped
|
|
|
registers, FIFO regis-
|
|
|
ters and RAMs
|
|
|
• Automatic minimal address space generation
|
|
|
• Generation of C header files containing addresses consistent with the
|
|
|
VHDL core
|
|
|
• Customizable register types, with multiple access options and multiple
|
|
|
clocking schemes
|
|
|
• Support for most common VHDL types
|
|
|
• (optional) automatic instantiation and wiring of slave core into the
|
|
|
VHDL design
|
|
|
• (optional) documentation generator.
|
|
|
|
|
|
|
|
|
|
|
|
### Files
|
... | ... | |