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... | @@ -31,11 +31,28 @@ figure: |
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The primitives are accessible from outside the slave core as
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The primitives are accessible from outside the slave core as
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VHDL/Verilog
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VHDL/Verilog
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signals:
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signals:
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![](/uploads/84b682a744ead2218666ab886efa09ee/slavecore.png)
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![](/uploads/84b682a744ead2218666ab886efa09ee/slavecore.png)
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## Input file syntax
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## Input file syntax
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In order to generate anything, wbgen2 requires a file (later referred as
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*WB** file) with a description of what we want to have inside the slave
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core. The syntax of description files is very similar to C language,
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hence they are easily editable without need for any special tools
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(unlike XML-based formats). Each WB file contains description of a
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single peripheral which may consist of:
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- Registers
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- RAM blocks
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- FIFO registers
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- Interrupt lines
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Registers and FIFO registers can be split into fields of different
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types and sizes, as shown on the figure below:
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Below you can find a sample of WB file syntax:
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### Files
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### Files
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