... | ... | @@ -19,9 +19,10 @@ clocking schemes |
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• Support for most common VHDL types
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• (optional) automatic instantiation and wiring of slave core into the
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VHDL design
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• (optional) documentation generator.
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• (optional) documentation
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generator.
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\!\!overview.png
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![](/uploads/49f4784118ae42e07cb7c2b7b0c8388b/overview.png)
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