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# wbgen2 Documentation
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*Purpose of wbgen2**
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1. Purpose of wbgen2\*
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wbgen2 is a tool for generating VHDL/Verilog cores which implement
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Wishbone bus slaves with certain registers, memory blocks, FIFOs and
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interrupts. The input is a C-like syntax file with an abstract
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description of what do we want to have in the slave. wbgen2 does then
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all the dirty work for us:
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description of what do we want to have in the slave. As a result, we get
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(see fig. 1):
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\- Automatically allocates the memory layout
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\- Automatically allocated memory layout
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\- Generates VHDL/Verilog code
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\- VHDL/Verilog code for the slave module
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\- Generates C header file for the drivers
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\- C header files for driver development
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\- Nice HTML
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documentation
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\- Generates nice HTML documentation
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\- and much more\!
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![](/uploads/49f4784118ae42e07cb7c2b7b0c8388b/overview.png)
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