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## wbgen2 Documentation
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overview
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h2. wbgen2 Documentation
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1. **Introduction**
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... | ... | @@ -8,8 +9,6 @@ Wishbone bus on one side, and on the other side it provides ports for |
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accessing memory mapped
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registers, FIFOs and RAMs, as shown on the following figure:
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overview
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Generation of VHDL code for slaves consisting of memory mapped
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registers, FIFO regis-
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ters and RAMs
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