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# wbgen2 Documentation
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## wbgen2 Documentation
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# Introduction
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## Introduction
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In wbgen2 terminology, a ”slave core” is an HDL entity which is
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In wbgen2 terminology, a ”slave core” is an HDL entity which is
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connected to Wishbone bus on one side, and on the other side it provides
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connected to Wishbone bus on one side, and on the other side it provides
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... | @@ -34,7 +34,7 @@ signals: |
... | @@ -34,7 +34,7 @@ signals: |
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![](/uploads/84b682a744ead2218666ab886efa09ee/slavecore.png)
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![](/uploads/84b682a744ead2218666ab886efa09ee/slavecore.png)
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# Input file syntax
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## Input file syntax
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In order to generate anything, wbgen2 requires a file (later referred as
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In order to generate anything, wbgen2 requires a file (later referred as
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*WB** file) with a description of what we want to have inside the slave
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*WB** file) with a description of what we want to have inside the slave
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... | @@ -82,47 +82,19 @@ More [WB-file-syntax-examples](WB-file-syntax-examples) |
... | @@ -82,47 +82,19 @@ More [WB-file-syntax-examples](WB-file-syntax-examples) |
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There are two classes of attributes:
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There are two classes of attributes:
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- **common attributes** - applicable for all blocks in the WB file
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- **common attributes** - applicable for all blocks in the WB file
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(*table 1*)
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(see *table 1*)
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- **object-specific attributes** - applicable only to blocks of
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- **object-specific attributes** - applicable only to blocks of
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certain type
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certain type
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- **peripheral** attributes (*table 2*)
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Some of the attributes are mandatory - they always have to be
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- **register** attributes (*table 3*)
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defined, while the others may be optional.
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- **RAM block** attributes (*table 4*)
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Some of the attributes are mandatory - they always have to be defined,
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while the others may be optional.
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*Table 1. Common attributes**
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*Table 1. Common attributes**
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| \* Attribute \*| **Status**| \* Description \*|
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| \* Attribute \*| **Status**| \_. Description |
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|`name` | mandatory | Short (single line) human readable name for the
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|`name` | mandatory | Short (single line) human readable name for the
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block. The name is used for commenting the generated code and producing
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block. The name is used for commenting the generated code and producing
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documentation. |
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documentation. |
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|`description` | optional | Longer description of the block, used by the
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|`description` | optional | Longer description of the block, used by the
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documentation generator. May contain inline HTML code. |
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documentation generator. Can contain some inline HTML code. |
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|`c_prefix`, `hdl_prefix`, `prefix` | mandatory | contains a short
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prefix for each block which is used for generation of VHDL port/signal
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names and C macros. Names are generated by concatenating the prefixes:
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`peripheral_reg_field`. In this
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[example](WB-file-syntax-examples#simple-general-purpose-i/o-port), the
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signal name of register "DDR" would be `gpio_ddr_o`. The format of
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`prefix` value must follow the HDL/C language syntax rules and your
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coding style. Note that you can provide either separate prefixes for
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C/HDL languages `c_prefix`, `hd_prefix` a single `prefix` for both. |
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## Peripheral attributes
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*Table 2. Peripheral attributes**
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| \* Attribute \*| **Status**| \* Description \*|
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|`hdl_entity`|mandatory|Name of the VHDL entity or Verilog module of the
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slave core to be generated|
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## Register attributes
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*Table 3. Register attributes**
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| \* Attribute \*| **Status**| \* Description \*|
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|`align = num`|optional|Alignment value for the field address. When
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given, wbgen2 will align the address of this register to the nearest
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multiple of `num`. \!\!|
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... | | ... | |