... | @@ -6,7 +6,10 @@ In wbgen2 terminology, a ”slave core” is an HDL entity which is |
... | @@ -6,7 +6,10 @@ In wbgen2 terminology, a ”slave core” is an HDL entity which is |
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connected to
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connected to
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Wishbone bus on one side, and on the other side it provides ports for
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Wishbone bus on one side, and on the other side it provides ports for
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accessing memory mapped
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accessing memory mapped
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registers, FIFOs and RAMs, as shown on the following figure:
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registers, FIFOs and RAMs, as shown on the following
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figure:
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![](/uploads/49f4784118ae42e07cb7c2b7b0c8388b/overview.png)
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Generation of VHDL code for slaves consisting of memory mapped
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Generation of VHDL code for slaves consisting of memory mapped
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registers, FIFO regis-
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registers, FIFO regis-
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