... | @@ -9,7 +9,7 @@ ports for accessing memory mapped registers, FIFOs and RAMs, as shown on |
... | @@ -9,7 +9,7 @@ ports for accessing memory mapped registers, FIFOs and RAMs, as shown on |
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the following
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the following
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figure:
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figure:
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![](/uploads/a55ac5d2f8a96f02e8add8102574a55e/overwiew.png)
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![](https://ohwr.org/project/wishbone-gen/uploads/a55ac5d2f8a96f02e8add8102574a55e/overwiew.png)
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wbgen2 simplifies creation of such cores, by automatically generating
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wbgen2 simplifies creation of such cores, by automatically generating
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HDL code, C code and documentation from a single, easily editable file.
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HDL code, C code and documentation from a single, easily editable file.
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... | @@ -35,7 +35,7 @@ The primitives are accessible from outside the slave core as |
... | @@ -35,7 +35,7 @@ The primitives are accessible from outside the slave core as |
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VHDL/Verilog
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VHDL/Verilog
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signals:
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signals:
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![](/uploads/84b682a744ead2218666ab886efa09ee/slavecore.png)
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![](https://ohwr.org/project/wishbone-gen/uploads/84b682a744ead2218666ab886efa09ee/slavecore.png)
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# 2\. Input file syntax
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# 2\. Input file syntax
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... | @@ -54,7 +54,7 @@ single peripheral which may consist of: |
... | @@ -54,7 +54,7 @@ single peripheral which may consist of: |
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types and sizes, as shown on the figure
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types and sizes, as shown on the figure
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below:
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below:
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![](/uploads/6e5799be4d901ccacb4d9e83a731fb41/reglayout.png)
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![](https://ohwr.org/project/wishbone-gen/uploads/6e5799be4d901ccacb4d9e83a731fb41/reglayout.png)
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General syntax of WB file looks like:
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General syntax of WB file looks like:
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... | @@ -179,7 +179,7 @@ Example to generate vhdl code and html |
... | @@ -179,7 +179,7 @@ Example to generate vhdl code and html |
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### Files
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### Files
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* [overwiew.png](/uploads/a55ac5d2f8a96f02e8add8102574a55e/overwiew.png)
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* [overwiew.png](https://ohwr.org/project/wishbone-gen/uploads/a55ac5d2f8a96f02e8add8102574a55e/overwiew.png)
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* [slavecore.png](/uploads/84b682a744ead2218666ab886efa09ee/slavecore.png)
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* [slavecore.png](https://ohwr.org/project/wishbone-gen/uploads/84b682a744ead2218666ab886efa09ee/slavecore.png)
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* [reglayout.png](/uploads/6e5799be4d901ccacb4d9e83a731fb41/reglayout.png)
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* [reglayout.png](https://ohwr.org/project/wishbone-gen/uploads/6e5799be4d901ccacb4d9e83a731fb41/reglayout.png)
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* [alignment.png](/uploads/d839884b9044380e0a915051af9e57c9/alignment.png) |
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* [alignment.png](https://ohwr.org/project/wishbone-gen/uploads/d839884b9044380e0a915051af9e57c9/alignment.png) |
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