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Mch mini backplane

Last edited by Tomasz Wlostowski
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MCH Mini backplane

The MCH Mini Backplane can be used as a replacement for the microTCA crate when only the switch functionality of the MCH is required.

Features:

- replaces the microTCA crate for switch-only applications.

- provides 8 downlink ports with SFP sockets
- provides PHY autocalibration (not supported by the MCH) on downlink ports

Mini-backplane + MCH together = standalone 10-port switch, as shown below:

The drawing below shows the block diagram of the mini backplane:

The diagram contains 4 subblocks:

MCH connector

It's an AMC right-angle connector (CN1) typically used to attach AMC cards onto AdvancedTCA blades. The PCB footprint has been modified (reversed pin order), so the MCH can be plugged in with the component side facing upwards (unlike AMC cards, where the bottom side of the PCB is facing the top). The AMC socket has the following MCH lines connected:

  • +12 V bulk power / +3.3 V management power and power enable pin
  • fabric A lanes 1-8: downlink ports
  • fast I2C bus (normally used as inter-MCH IPMB)
  • reset and interrupt line (normally used as slot 6 IPMB)
  • calibration feedback input (normally used as MCH fabric update RX input)

Power supply

The PSU takes +12 V input from an external AC power module via CN2 and provides:

  • +12 V / 3 A bulk power for the MCH (via a MOSFET switch controlled by the watchdog MCU)
  • +3.3 V / 3 A for the SFPs and the backplane logic
  • +3.3 V / 200 mA microTCA management power.

SFP assemblies

There are 8 SFP assemblies, each of them having:

  • an SFP socket
  • 2 status LEDs
  • calibration buffers for RX and TX lanes
  • I2C I/O expander for controlling the LEDs, cal. buffers and SFP lines

Below there is a block diagram of a single SFP assemly:

The calibration buffers are placed very close to the SFP connector pins to avoid making stubs. The outputs of the buffers are connected together between two adjacent SFPs (e.g. SFP0 + SFP1, SFP2 + SFP3, ...) to avoid excessively long stubs on the feedback trace. Since the buffer outputs are tri-stated, it makes a nice and cheap multiplexer suitable for the calibration of the PHY asymmetry.

All the digital lines (except for the SFP builtin I2C memory) are controlled by an 8-bit I2C GPIO expander (PCA9534):

  • P0: Link LED
  • P1: Status LED
  • P2: SFP Tx disable
  • P3: SFP Tx fault
  • P4: Calibration feedback enable for TX path
  • P5: Calibration feedback enable for RX path
  • P6: SFP loss-of-signal
  • P7: SFP detect

Calibration feedback lines from SFP0+1, SFP2+3, SFP4+5, SFP6+7 are again multiplexed by another set of LVDS buffers, controlled by a separate I2C expander (PCA9534A).

h4: I2C Logic

Apart from the SFP assembly I/O expanders, there are 2 additional I2C chips:

  • 8-port I2C hub - PCA9548A (for multiplexing access to the SFP identification memories which have identical addresses)
  • 8-port I2C GPIO - PCA9535A for controlling layer2 calibration feedback muxes

I2C peripheral address map:

  • port 0 GPIO: 0x40 (with IRQ line)
  • port 1 GPIO: 0x42 (with IRQ line)
  • port 2 GPIO: 0x44 (with IRQ line)
  • port 3 GPIO: 0x46 (with IRQ line)
  • port 4 GPIO: 0x48 (with IRQ line)
  • port 5 GPIO: 0x4a (with IRQ line)
  • port 6 GPIO: 0x4c (with IRQ line)
  • port 7 GPIO: 0x4e (with IRQ line)
  • calibration mux GPIO: 0x70
  • I2C HUB: 0xe0

Schematics & PCBs

The PCB project (4-layer FR4, 1.55mm, 2S+2P) is here: http://svn.ohwr.org/white-rabbit/trunk/circuit_board/mini_backplane
PDF schematics and layout: http://svn.ohwr.org/white-rabbit/trunk/circuit_board/mini_backplane/mini_backplane.pdf

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