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ISPCS2016: submitted for review

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papers/ISPCS2016/wrClockCharacteristics.tex
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......@@ -11,7 +11,7 @@
\setlength{\belowcaptionskip}{0pt}
\title{White Rabbit clock characteristics }
\title{White Rabbit clock characteristics\vspace{-0.3cm} }
\author{
\IEEEauthorblockN{Mattia Rizzi}
......@@ -55,7 +55,7 @@ the latter was achieved merely by modifying the software that implements the
WR PLL.
\end{abstract}
\vspace{-0.3cm}
\section{Introduction}
The White Rabbit (WR) project is a multilaboratory, multicompany, and multinational
......@@ -89,6 +89,7 @@ metrics and
phase noise transfer analysis. These measurements allow to suggest a number of possible
modifications to optimize phase-noise and to achieve compliance with SyncE.
In both cases, the impact on the L1 syntonisation performance is measured.
\vspace{-0.1cm}
\section{PTP synchronisation and L1 syntonisation in White Rabbit}
......@@ -108,7 +109,7 @@ the medium.
\includegraphics[width=0.5\textwidth]{p1588/1588-ha-L1vsPTP.jpg}
\caption{L1 and PTP clock signals.}
\label{fig:clocks}
\end{figure}\vspace{-0.2cm}
\end{figure}\vspace{-0.3cm}
Unlike in many PTP implementations, in WR the PTP synchronisation and the L1 syntonisation
are made to tightly cooperate. In particular, the local PTP time and the \textit{L1 tx/rx clock signals}
......@@ -142,13 +143,14 @@ rather than manipulating the \textit{time counter} value. The WR PLL not only sy
\textit{L1 rx clock signal} but also maintains the desired phase offset between these two
clock signals, a value so-called \textit{setpoint}. The architecture of the WR PLL is
explained in the next section.
\vspace{-0,4cm}
\section{WR Phase-Locked Loop}
The WR PLL, detailed in \cite{tom}, is a phase-shifting digital PLL that uses
Digital Dual Mixer Time Difference (DDMTD) \cite{ddmtd} to obtain the phase error between
the input clock signals.
\vspace{-0,4cm}
\subsection{Digital Dual Mixer Time Difference (DDMTD)}
\label{sec:ddmtd}
The DDMTD uses digital mixing to produce output clock signals of lower frequency than that of
......@@ -175,10 +177,12 @@ that is proportional to the frequency of the input clock signals. The phase, exp
between the input signals is equal to that between the output signals. Therefore,
the time-difference between the edges of the input and output clock signals is
proportional and can be expressed as follows:
% \vspace{-0,1cm}
\begin{equation}
\label{eq:fddmtd}
x_{in}[ns] = \frac{1}{1 + 2^N} \cdot x_{out} [ns]
\end{equation}
% \vspace{-0,1cm}
The output time-difference is significantly larger and it can be measured with much greater
precision than the input phase. It is used to calculate the time-difference between the
input clocks. This technique is used in the WR PLL described in the next section.
......@@ -230,7 +234,7 @@ its bandwidth is 35Hz.
The SoftPLL determines the characteristics of the frequency transfer through a WR switch. These
are characterised in the next section according to the ITU-T G.8262 guidelines.
\vspace{-0,2cm}
\section{SyncE characteristics of L1 syntonisation}
\label{sec:syncEchar}
......@@ -269,7 +273,8 @@ development can be found in \cite{syncEtest2}.
The results in Table~\ref{tab:SyncEchar} were obtained using a dedicated SyncE tester,
Calnex Paragon-X, and general-purpose measurement equipment. The measurement setups are depicted in
Fig.~\ref{fig:allSetups} and described below:
\begin{enumerate}[1]
\begin{enumerate}
\small
\item A CS4000 Cesium Frequency Standard (Cs) is the external reference for the Paragon-X.
The WR Switch, which is the device under test (DUT), is free-running. The Paragon-X is syntonised
to the DUT over a 1GbE fiber link.
......@@ -292,14 +297,14 @@ Fig.~\ref{fig:allSetups} and described below:
configured to make Time Interval Error (TIE) measurements of the 10MHz outputs of the
GM and the DUT at a 1kHz sampling rate.
\end{enumerate}\vspace{-0.3cm}
The tests results in Table~\ref{tab:SyncEchar} show clearly that the currently available WR switches are not compliant with SyncE.
\begin{figure}[!ht]
\centering
\includegraphics[width=0.4\textwidth]{measurements/WRclockChar/allSetups.jpg}
\caption{Set-ups used to obtain WR clock characteristics.}
\label{fig:allSetups}
\end{figure}\vspace{-0.2cm}
The tests results in Table~\ref{tab:SyncEchar} show clearly that the currently available WR switches are not compliant with SyncE.
\end{figure}\vspace{-0.3cm}
Although the wander and jitter generation of the WR switch are orders of magnitude better
than required by ITU-T G.8262, the WR switch fails the tests of wander transfer as well as wander
and jitter tolerance. Fig.~\ref{fig:wanderTransfer1} shows that the transfer function of the
......@@ -315,7 +320,7 @@ for EEC-Option~2.
\end{figure}\vspace{-0.5cm}
\begin{figure}[!ht]
\centering
\includegraphics[width=0.3\textwidth]{measurements/WRclockChar/wanderTransfer1.jpg}
\includegraphics[width=0.25\textwidth]{measurements/WRclockChar/wanderTransfer1.jpg}
\caption{Transfer function of the WR switch.}
\label{fig:wanderTransfer1}
\end{figure}\vspace{-0.2cm}
......@@ -331,7 +336,7 @@ The section that follows characterizes L1 syntonisation using phase noise analy
The phase noise of frequency transfer through a WR network is measured to evaluate the
current performance and identify potential improvements. The measurement is done
at each state of a linear daisy chain of 3 WR switches in a setup depicted in Fig.~\ref{fig:phaseNoise-setup}.
\begin{figure}[!ht]\vspace{-0.5cm}
\begin{figure}[!ht]\vspace{-0.3cm}
\centering
\includegraphics[width=0.28\textwidth]{measurements/WRclockChar/phaseNoise-setup.jpg}
\caption{Phase noise measurement.}
......@@ -361,20 +366,7 @@ Fig.~\ref{fig:noiseTransfer} shows the results of these three measurements.
The effect of gain peaking is clearly visible in the graph. The increase of
phase noise in the 1Hz-10Hz region suggests possible phase noise leaking from the voltage
controlled oscillator (VM53S3). Table~\ref{tab:phaseNoise}
provides the integrated RMS jitter in different regions of the spectrum, i.e. 1Hz to 10Hz,
1Hz to 2kHz and 1Hz to 100kHz. The values of jitter in the first region allow to evaluate
the jitter in the bandwidth of the SoftPLL with respect to the jitter over the entire
measurement bandwidth.
Additionally to frequency-domain analysis, Table~\ref{tab:adev} provides time-domain analysis.
Allan Deviation is measured by the Symmetricom 3120A Test Probe at each
of the three switches for different values of integration time with an
equivalent noise bandwidth (ENBW) of 50Hz. Both, Allan Deviation and phase noise analysis
confirm an accumulation of phase noise in the lower frequencies of the spectrum.
The source of the phase noise in the lower frequencies of the spectrum is analysed in the
next section and methods to improve the frequency transfer over WR network are proposed.
\vspace{-0.4cm}
\vspace{-0.2cm}
\begin{table}[!ht]
\centering
\scriptsize
......@@ -394,7 +386,21 @@ ext. PLL & 30Hz & SW 1 & 4.4ps & 4.8p
\end{tabular}
\caption{Integrated RMS jitter in different regions of the spectrum.}
\label{tab:phaseNoise}
\end{table}\vspace{-0.6cm}
\end{table}\vspace{-0.3cm}
provides the integrated RMS jitter in different regions of the spectrum, i.e. 1Hz to 10Hz,
1Hz to 2kHz and 1Hz to 100kHz. The values of jitter in the first region allow to evaluate
the jitter in the bandwidth of the SoftPLL with respect to the jitter over the entire
measurement bandwidth.
Additionally to frequency-domain analysis, Table~\ref{tab:adev} provides time-domain analysis.
Allan Deviation is measured by the Symmetricom 3120A Test Probe at each
of the three switches for different values of integration time with an
equivalent noise bandwidth (ENBW) of 50Hz. Both, Allan Deviation and phase noise analysis
confirm an accumulation of phase noise in the lower frequencies of the spectrum.
The source of the phase noise in the lower frequencies of the spectrum is analysed in the
next section and methods to improve the frequency transfer over WR network are proposed.
\vspace{-0.5cm}
\begin{table}[!ht]
\centering
\scriptsize
......@@ -429,7 +435,7 @@ The measurements presented in the previous section indicate that the phase noise
of the frequency transfer in the WR network can be improved at 1) the GM syntonizing
to the external reference, and 2) the WR switches syntonizing to the GM. These improvements
are described in the following subsection.
\vspace{-0.2cm}
\subsection{VCO noise leaking}
The phase noise spectrum of the WR Switch between 1Hz-10Hz suggest a undesired phase noise
......@@ -449,6 +455,12 @@ In order to prevent the phase noise leaking, the SoftPLL was modified to provide
stronger rejection of the VCO phase noise. The modified SoftPLL has a bandwidth of 200Hz
with the VCO rejection characteristics of -58dB@1Hz, -34dB@5Hz and -24db@10Hz (compared
with the characteristics of the current SoftPLL: -48dB@1Hz, -20dB@5Hz and -7db@10Hz).
% in Table~\ref{tab:VCOrejectionParams}.
The phase noise
of the WR Switch 1 with modified SoftPLL is depicted in Fig.~\ref{fig:slaveVCOLeaking} (green
line). The phase noise of WR Switch 1 with modified SoftPLL does not exhibit any
phase noise accumulation in the 1Hz-10Hz range. This improves the Allan Deviation. The new ADEV measurements are
provided in Table~\ref{tab:adev}.
\vspace{-0.3cm}
\begin{figure}[!ht]
\centering
......@@ -456,18 +468,12 @@ with the characteristics of the current SoftPLL: -48dB@1Hz, -20dB@5Hz and -7db@1
\caption{Phase noise.}
\label{fig:slaveVCOLeaking}
\end{figure}\vspace{-0.3cm}
% in Table~\ref{tab:VCOrejectionParams}.
The phase noise
of the WR Switch 1 with modified SoftPLL is depicted in Fig.~\ref{fig:slaveVCOLeaking} (green
line). The phase noise of WR Switch 1 with modified SoftPLL does not exhibit any
phase noise accumulation in the 1Hz-10Hz range. This improves the Allan Deviation. The new ADEV measurements are
provided in Table~\ref{tab:adev}.
Theoretically, the larger bandwidth of the modified SoftPLL could lead to
increased due to a less aggressive filtering of the phase noise above 35Hz. However,
measurement with a cascade of two WR Switches running the modified SoftPLL and connected to the GM show a decrease
of jitter compared to the non-modified SoftPLL, as presented in
Table~\ref{tab:phaseNoise}.
\vspace{-0.2cm}
\subsection{Syntonisation of GM to the external 10MHz reference}
The GM WR Switch locks to the external 10MHz reference using a SoftPLL that requires 62.5MHz
......@@ -523,6 +529,7 @@ phase noise accumulation. A controlled oscillator with at least 10dB better phas
1-10Hz spectrum would help to pick
the best noise profile since less bandwidth would be required to reject the noise coming from
the local oscillator.
\vspace{-0.3cm}
\begin{figure}[!ht]
\centering
\includegraphics[width=0.35\textwidth]{measurements/WRclockChar/improvedGM.jpg}
......@@ -549,23 +556,37 @@ local oscillator (VM53S3) out of it's range.
In order to meet the SyncE characteristics without changing the hardware, the SoftPLL
software was modified as follows:
\begin{enumerate}
\item \textbf{The bandwidth was reduced to 5Hz}. This allows to the meet the SyncE EEC-Option 1
specification and filter the low frequency wander noise that can drive the
oscillator outside its pull-range.
\item \textbf{Multiple Unit Interval (UI) tracking of error was implemented.} This
allows the SoftPLL to track errors greater than $\pm$16ns.
\item \textbf{Locking logic was modified to allow tracking of large zero-mean wander.}
The default locking logic detects an out-of-lock situation if the error signal is outside a
threshold for a predetermined amount of time. This logic cannot work with large
wander errors since it would require a threshold equal to the
wander amplitude. The modified locking logic implements out-of-lock detection
based on averaged error, with a 3-second moving window.
\item The bandwidth was reduced to 5Hz.
\item Multiple Unit Interval (UI) tracking of error was implemented.
\item Locking logic was modified to allow tracking of large zero-mean wander.
\end{enumerate}
% \begin{enumerate}
% \item \textbf{The bandwidth was reduced to 5Hz}. This allows to the meet the SyncE EEC-Option 1
% specification and filter the low frequency wander noise that can drive the
% oscillator outside its pull-range.
% \item \textbf{Multiple Unit Interval (UI) tracking of error was implemented.} This
% allows the SoftPLL to track errors greater than $\pm$16ns.
% \item \textbf{Locking logic was modified to allow tracking of large zero-mean wander.}
% The default locking logic detects an out-of-lock situation if the error signal is outside a
% threshold for a predetermined amount of time. This logic cannot work with large
% wander errors since it would require a threshold equal to the
% wander amplitude. The modified locking logic implements out-of-lock detection
% based on averaged error, with a 3-second moving window.
% \end{enumerate}
The 3 tests from subsection~\ref{sec:syncEchar} were repeated using the modified
SoftPLL: wander tolerance (op-1 only), jitter tolerance, and wander transfer. All tests
were successfully passed. The transfer function of the modified SoftPLL is depicted in
Fig.~\ref{fig:SyncEcombo}-1. It meets the noise transfer (sec. 10 of G.8262)
Fig.~\ref{fig:SyncEcombo}-1.
\vspace{-0.3cm}
\begin{figure}[!ht]
\centering
\includegraphics[width=0.5\textwidth]{measurements/WRclockChar/SyncECompliantCcombo.jpg}
\caption{Characteristics of WR switch with SyncE-compliant SoftPLL.}
\label{fig:SyncEcombo}
\end{figure}\vspace{-0.3cm}
It meets the noise transfer (sec. 10 of G.8262)
requirement of below 0.2dB gain peaking and confirms that the bandwidth is within the range
specified for the EEC-option-1. Fig.~\ref{fig:SyncEcombo}-2 shows that the WR switch
with the modified SoftPLL correctly transferred the wander noise defined in
......@@ -586,23 +607,16 @@ that the unmodified SoftPLL (blue) has a very low integrated jitter of 4ps RMS (
The SyncE-compliant SoftPLL (pink) has a much higher jitter in the 1-10Hz bandwidth that results
in a total integrated jitter of 100ps RMS. This is attributed to the the VCO (VM53S3)
that exhibits high phase noise in the 1-10Hz region when not controlled (red trace).
\vspace{-0.3cm}
\begin{figure}[!ht]
\centering
\includegraphics[width=0.5\textwidth]{measurements/WRclockChar/SyncECompliantCcombo.jpg}
\caption{Characteristics of WR switch with SyncE-compliant SoftPLL.}
\label{fig:SyncEcombo}
\end{figure}\vspace{-0.3cm}
An
oscillator with a better phase noise profile in that region (e.g. -70 dBc/Hz at 1Hz) can lower the
disparity of performance between the two versions of the SoftPLL.
\vspace{-0.4cm}
\vspace{-0.5cm}
\begin{figure}[!ht]
\centering
\includegraphics[width=0.4\textwidth]{measurements/WRclockChar/SyncE-compare.jpg}
\includegraphics[width=0.35\textwidth]{measurements/WRclockChar/SyncE-compare.jpg}
\caption{Phase noise transfer.}
\label{fig:SyncE-compare}
\end{figure}\vspace{-0.9cm}
\end{figure}\vspace{-0.5cm}
\section{Conclusions}
\label{conclusions}
......@@ -620,7 +634,7 @@ the standardisation makes it likely to be used in less stringent applications th
compatibility with legacy equipment. We have shown that adaptation in different directions is
feasible, straightforward and often requires only software modifications.
\vspace{-0.1cm}
......
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