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48899fc0
Commit
48899fc0
authored
Jun 28, 2019
by
Maciej Lipinski
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Cosmetic corrections
parent
36d0b7be
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wr_efts_2019.tex
presentations/WR_Maciej_EFTS_2019/wr_efts_2019.tex
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presentations/WR_Maciej_EFTS_2019/wr_efts_2019.tex
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48899fc0
...
...
@@ -447,8 +447,8 @@ INRIM & Italy & 70~km & 610ps $\pm$47ps\\ \hline
\item
<2->
\textbf
{
Bitslide
}
-- measurement uncertainty
\begin{itemize}
\scriptsize
\item
Measured each time link goes up
\item
Value provided by
GTX of
FPGA
\item
Error:
$
\
pm
$
35ps for GTX
\item
Value provided by
transceiver in
FPGA
\item
Error:
$
\
approx\pm
$
50ps for GTX (Virtex 6)
\item
Remedy: ensure bitslide is zero
\\
(ongoing work at CERN)
\end{itemize}
\end{itemize}
...
...
@@ -557,13 +557,13 @@ INRIM & Italy & 70~km & 610ps $\pm$47ps\\ \hline
\begin{itemize}
\scriptsize
\item
<1->
\textbf
{
DDMTD
}
\begin{itemize}
\scriptsize
\item
Flicker PM noise: -100 dBc at 1 Hz
\item
Flicker PM noise: -100 dBc
/Hz
at 1 Hz
\begin{itemize}
\tiny
\item
Dominant
$
<
$
10Hz,
\item
MDEV 4E-13 at
$
\tau
=
1
s
$
\item
LVDS input clock buffer and clock routing
\end{itemize}
\item
White PM noise: -108 dBc
\item
White PM noise: -108 dBc
/Hz
\begin{itemize}
\tiny
\item
Limits the phase noise to -108 dBc/Hz
\item
Thermal, DFF meta-stability, noise due to aliasing
...
...
@@ -572,8 +572,8 @@ INRIM & Italy & 70~km & 610ps $\pm$47ps\\ \hline
\end{itemize}
\item
<3->
\textbf
{
GTX
}
\begin{itemize}
\scriptsize
\item
Flicker PM noise: -100 dBc at 1 Hz
\item
White PM noise: -106 dBc
\\
MDEV 4E-13 at
$
\tau
=
1
s
$
\item
Flicker PM noise: -100 dBc
/Hz
at 1 Hz
\item
White PM noise: -106 dBc
/Hz
\\
MDEV 4E-13 at
$
\tau
=
1
s
$
\end{itemize}
\item
<4-> Remedy: none, inherent to technology
\end{itemize}
...
...
@@ -609,7 +609,7 @@ INRIM & Italy & 70~km & 610ps $\pm$47ps\\ \hline
\begin{itemize}
\scriptsize
\item
Noisy internal Virtex-6 MMCM PLL
\item
Large phase noise power at 10kHz to 2MHz
\item
Phase noise above DDMTD Nyquist (1.9kHz) bandwidth folds back to baseband
\item
Phase noise above DDMTD Nyquist (1.9kHz) bandwidth folds back to baseband
[14]
\item
Remedy: external PLL to synthesize 62.5MHz from 10MHz (see daughterboard [16])
\end{itemize}
...
...
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