... | @@ -44,30 +44,26 @@ configuration etc.). WRPC has been successfully tested with GTP and GTX |
... | @@ -44,30 +44,26 @@ configuration etc.). WRPC has been successfully tested with GTP and GTX |
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transceivers of Xilinx's FPGAs (e.g. Spartan-6 LXT family), support for
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transceivers of Xilinx's FPGAs (e.g. Spartan-6 LXT family), support for
|
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Altera GX PHYs is currently being implemented.
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Altera GX PHYs is currently being implemented.
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### Block Diagram:
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### External Components
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/3374
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/3374
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The necessary external components are the fiber optic transceiver (SFP
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The necessary external components are the fiber optic transceiver (SFP
|
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module) and two digitally tunable clock generators (one for the main
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module) and two digitally tunable clock generators (one for the main
|
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PLL, one for producing the DMTD offset frequency).
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PLL, one for producing the DMTD offset frequency).
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The remaining components are optional but supported by WRPC:
|
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The use of the remaining components in the block diagram is optional
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(supported by WRPC):
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- EEPROM (I2C), which can store the device's configuration data
|
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- EEPROM (I2C interface), which can store the device's configuration
|
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- Unique ID / Temperature sensor (one-wire), which can be used to
|
|
data
|
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build the MAC address
|
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- Unique ID / Temperature sensor (one-wire interface), which can be
|
|
|
|
used to build the MAC address
|
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- I/O connector with user I/O signals
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- I/O connector with user I/O signals
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|
|
|
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The total cost of the external components, including the SFP module is
|
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The total cost of the external components, including the SFP module is
|
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around 75 Euros to which a part of the price of the Xilinx ([search
|
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around 75 Euros to which a part of the price of the Xilinx ([search
|
|
price](http://www.eciaauthorized.com/search?pn=XC6SLX45T-3FGG484C))
|
|
price](http://www.eciaauthorized.com/search?pn=XC6SLX45T-3FGG484C))
|
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still should be
|
|
still should be added.
|
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added.
|
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|
|
|
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|
|
### FPGA Utilization Summary
|
|
|
|
The table below shows the FPGA utilization summary of the WRPC relevant resources only (Spartan-6, XC6SLX45T-3FGG484, ISE 13.4):
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/3366
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|
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### Operating Power
|
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### Operating Power
|
|
|
|
|
... | @@ -75,6 +71,14 @@ The table below shows the FPGA utilization summary of the WRPC relevant resource |
... | @@ -75,6 +71,14 @@ The table below shows the FPGA utilization summary of the WRPC relevant resource |
|
- Clock generators: ~ 700 mW
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- Clock generators: ~ 700 mW
|
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- FO Transceiver: ~ 500 mW
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- FO Transceiver: ~ 500 mW
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|
|
|
|
|
|
|
### FPGA Utilization Summary
|
|
|
|
|
|
|
|
The table below shows the FPGA utilization summary of the WRPC relevant
|
|
|
|
resources only (WRPC v2.1, Spartan-6, XC6SLX45T-3FGG484, ISE
|
|
|
|
13.4):
|
|
|
|
|
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|
|
![](/uploads/9324814d56fff42202ac64e068137152/WRPC_FPGA_utilization_summary.jpg)
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### More information:
|
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### More information:
|
|
|
|
|
|
- Schematic diagram - PDF
|
|
- Schematic diagram - PDF
|
... | @@ -91,7 +95,7 @@ The table below shows the FPGA utilization summary of the WRPC relevant resource |
... | @@ -91,7 +95,7 @@ The table below shows the FPGA utilization summary of the WRPC relevant resource |
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## Compact standalone solutions
|
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## Compact standalone solutions
|
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|
|
|
|
### Some projects which are standalone White Rabbit Node implementations:
|
|
Some projects which are standalone White Rabbit Node implementations:
|
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|
|
- [CUTE-WR](https://www.ohwr.org/project/cute-wr/wiki), FPGA Mezzanine
|
|
- [CUTE-WR](https://www.ohwr.org/project/cute-wr/wiki), FPGA Mezzanine
|
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Card
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Card
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... | | ... | |